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Merging r367019: ------------------------------------------------------------------------ r367019 | chill | 2019-07-25 15:56:04 +0200 (Thu, 25 Jul 2019) | 10 lines [AArch64][SVE] Allow explicit size specifier for predicate operand ... for the vector forms of `{SQ,UQ,}{INC,DEC}P` instructions. Also continue supporting the exsting behaviour of not requiring an explicit size specifier. The preferred disasembly is *with* the specifier. This is implemented by redefining intruction forms to require vector predicates with explicit size and adding aliases, which allow a predicate with no size. Differential Revision: https://reviews.llvm.org/D65145 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_90@369086 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 1 year, 3 months ago
7 changed file(s) with 154 addition(s) and 39 deletion(s). Raw diff Collapse all Expand all
402402 }
403403
404404 class sve_int_count_v sz8_64, bits<5> opc, string asm,
405 ZPRRegOp zprty>
406 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, PPRAny:$Pg),
407 asm, "\t$Zdn, $Pg",
408 "",
409 []>, Sched<[]> {
410 bits<4> Pg;
405 ZPRRegOp zprty, PPRRegOp pprty>
406 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, pprty:$Pm),
407 asm, "\t$Zdn, $Pm",
408 "",
409 []>, Sched<[]> {
410 bits<4> Pm;
411411 bits<5> Zdn;
412412 let Inst{31-24} = 0b00100101;
413413 let Inst{23-22} = sz8_64;
415415 let Inst{18-16} = opc{4-2};
416416 let Inst{15-11} = 0b10000;
417417 let Inst{10-9} = opc{1-0};
418 let Inst{8-5} = Pg;
418 let Inst{8-5} = Pm;
419419 let Inst{4-0} = Zdn;
420420
421421 let Constraints = "$Zdn = $_Zdn";
424424 }
425425
426426 multiclass sve_int_count_v opc, string asm> {
427 def _H : sve_int_count_v<0b01, opc, asm, ZPR16>;
428 def _S : sve_int_count_v<0b10, opc, asm, ZPR32>;
429 def _D : sve_int_count_v<0b11, opc, asm, ZPR64>;
427 def _H : sve_int_count_v<0b01, opc, asm, ZPR16, PPR16>;
428 def _S : sve_int_count_v<0b10, opc, asm, ZPR32, PPR32>;
429 def _D : sve_int_count_v<0b11, opc, asm, ZPR64, PPR64>;
430
431 def : InstAlias
432 (!cast(NAME # "_H") ZPR16:$Zdn, PPRAny:$Pm), 0>;
433 def : InstAlias
434 (!cast(NAME # "_S") ZPR32:$Zdn, PPRAny:$Pm), 0>;
435 def : InstAlias
436 (!cast(NAME # "_D") ZPR64:$Zdn, PPRAny:$Pm), 0>;
430437 }
431438
432439 class sve_int_pcount_pred sz8_64, bits<4> opc, string asm,
5555 // CHECK-UNKNOWN: ff 89 ed 25
5656
5757 decp z31.h, p15
58 // CHECK-INST: decp z31.h, p15
58 // CHECK-INST: decp z31.h, p15.h
59 // CHECK-ENCODING: [0xff,0x81,0x6d,0x25]
60 // CHECK-ERROR: instruction requires: sve
61 // CHECK-UNKNOWN: ff 81 6d 25
62
63 decp z31.h, p15.h
64 // CHECK-INST: decp z31.h, p15.h
5965 // CHECK-ENCODING: [0xff,0x81,0x6d,0x25]
6066 // CHECK-ERROR: instruction requires: sve
6167 // CHECK-UNKNOWN: ff 81 6d 25
6268
6369 decp z31.s, p15
64 // CHECK-INST: decp z31.s, p15
70 // CHECK-INST: decp z31.s, p15.s
71 // CHECK-ENCODING: [0xff,0x81,0xad,0x25]
72 // CHECK-ERROR: instruction requires: sve
73 // CHECK-UNKNOWN: ff 81 ad 25
74
75 decp z31.s, p15.s
76 // CHECK-INST: decp z31.s, p15.s
6577 // CHECK-ENCODING: [0xff,0x81,0xad,0x25]
6678 // CHECK-ERROR: instruction requires: sve
6779 // CHECK-UNKNOWN: ff 81 ad 25
6880
6981 decp z31.d, p15
70 // CHECK-INST: decp z31.d, p15
82 // CHECK-INST: decp z31.d, p15.d
83 // CHECK-ENCODING: [0xff,0x81,0xed,0x25]
84 // CHECK-ERROR: instruction requires: sve
85 // CHECK-UNKNOWN: ff 81 ed 25
86
87 decp z31.d, p15.d
88 // CHECK-INST: decp z31.d, p15.d
7189 // CHECK-ENCODING: [0xff,0x81,0xed,0x25]
7290 // CHECK-ERROR: instruction requires: sve
7391 // CHECK-UNKNOWN: ff 81 ed 25
82100 // CHECK-ERROR: instruction requires: sve
83101 // CHECK-UNKNOWN: df bc 20 04
84102
85 decp z31.d, p15
103 decp z31.d, p15.d
86104 // CHECK-INST: decp z31.d, p15
87105 // CHECK-ENCODING: [0xff,0x81,0xed,0x25]
88106 // CHECK-ERROR: instruction requires: sve
5555 // CHECK-UNKNOWN: ff 89 ec 25
5656
5757 incp z31.h, p15
58 // CHECK-INST: incp z31.h, p15
58 // CHECK-INST: incp z31.h, p15.h
59 // CHECK-ENCODING: [0xff,0x81,0x6c,0x25]
60 // CHECK-ERROR: instruction requires: sve
61 // CHECK-UNKNOWN: ff 81 6c 25
62
63 incp z31.h, p15.h
64 // CHECK-INST: incp z31.h, p15.h
5965 // CHECK-ENCODING: [0xff,0x81,0x6c,0x25]
6066 // CHECK-ERROR: instruction requires: sve
6167 // CHECK-UNKNOWN: ff 81 6c 25
6268
6369 incp z31.s, p15
64 // CHECK-INST: incp z31.s, p15
70 // CHECK-INST: incp z31.s, p15.s
71 // CHECK-ENCODING: [0xff,0x81,0xac,0x25]
72 // CHECK-ERROR: instruction requires: sve
73 // CHECK-UNKNOWN: ff 81 ac 25
74
75 incp z31.s, p15.s
76 // CHECK-INST: incp z31.s, p15.s
6577 // CHECK-ENCODING: [0xff,0x81,0xac,0x25]
6678 // CHECK-ERROR: instruction requires: sve
6779 // CHECK-UNKNOWN: ff 81 ac 25
6880
6981 incp z31.d, p15
70 // CHECK-INST: incp z31.d, p15
82 // CHECK-INST: incp z31.d, p15.d
83 // CHECK-ENCODING: [0xff,0x81,0xec,0x25]
84 // CHECK-ERROR: instruction requires: sve
85 // CHECK-UNKNOWN: ff 81 ec 25
86
87 incp z31.d, p15.d
88 // CHECK-INST: incp z31.d, p15.d
7189 // CHECK-ENCODING: [0xff,0x81,0xec,0x25]
7290 // CHECK-ERROR: instruction requires: sve
7391 // CHECK-UNKNOWN: ff 81 ec 25
82100 // CHECK-ERROR: instruction requires: sve
83101 // CHECK-UNKNOWN: df bc 20 04
84102
85 incp z31.d, p15
86 // CHECK-INST: incp z31.d, p15
103 incp z31.d, p15.d
104 // CHECK-INST: incp z31.d, p15.d
87105 // CHECK-ENCODING: [0xff,0x81,0xec,0x25]
88106 // CHECK-ERROR: instruction requires: sve
89107 // CHECK-UNKNOWN: ff 81 ec 25
5555 // CHECK-UNKNOWN: ff 89 ea 25
5656
5757 sqdecp z0.h, p0
58 // CHECK-INST: sqdecp z0.h, p0
58 // CHECK-INST: sqdecp z0.h, p0.h
59 // CHECK-ENCODING: [0x00,0x80,0x6a,0x25]
60 // CHECK-ERROR: instruction requires: sve
61 // CHECK-UNKNOWN: 00 80 6a 25
62
63 sqdecp z0.h, p0.h
64 // CHECK-INST: sqdecp z0.h, p0.h
5965 // CHECK-ENCODING: [0x00,0x80,0x6a,0x25]
6066 // CHECK-ERROR: instruction requires: sve
6167 // CHECK-UNKNOWN: 00 80 6a 25
6268
6369 sqdecp z0.s, p0
64 // CHECK-INST: sqdecp z0.s, p0
70 // CHECK-INST: sqdecp z0.s, p0.s
71 // CHECK-ENCODING: [0x00,0x80,0xaa,0x25]
72 // CHECK-ERROR: instruction requires: sve
73 // CHECK-UNKNOWN: 00 80 aa 25
74
75 sqdecp z0.s, p0.s
76 // CHECK-INST: sqdecp z0.s, p0.s
6577 // CHECK-ENCODING: [0x00,0x80,0xaa,0x25]
6678 // CHECK-ERROR: instruction requires: sve
6779 // CHECK-UNKNOWN: 00 80 aa 25
6880
6981 sqdecp z0.d, p0
70 // CHECK-INST: sqdecp z0.d, p0
82 // CHECK-INST: sqdecp z0.d, p0.d
83 // CHECK-ENCODING: [0x00,0x80,0xea,0x25]
84 // CHECK-ERROR: instruction requires: sve
85 // CHECK-UNKNOWN: 00 80 ea 25
86
87 sqdecp z0.d, p0.d
88 // CHECK-INST: sqdecp z0.d, p0.d
7189 // CHECK-ENCODING: [0x00,0x80,0xea,0x25]
7290 // CHECK-ERROR: instruction requires: sve
7391 // CHECK-UNKNOWN: 00 80 ea 25
82100 // CHECK-ERROR: instruction requires: sve
83101 // CHECK-UNKNOWN: e0 bc 20 04
84102
85 sqdecp z0.d, p0
86 // CHECK-INST: sqdecp z0.d, p0
103 sqdecp z0.d, p0.d
104 // CHECK-INST: sqdecp z0.d, p0.d
87105 // CHECK-ENCODING: [0x00,0x80,0xea,0x25]
88106 // CHECK-ERROR: instruction requires: sve
89107 // CHECK-UNKNOWN: 00 80 ea 25
5555 // CHECK-UNKNOWN: ff 89 e8 25
5656
5757 sqincp z0.h, p0
58 // CHECK-INST: sqincp z0.h, p0
58 // CHECK-INST: sqincp z0.h, p0.h
59 // CHECK-ENCODING: [0x00,0x80,0x68,0x25]
60 // CHECK-ERROR: instruction requires: sve
61 // CHECK-UNKNOWN: 00 80 68 25
62
63 sqincp z0.h, p0.h
64 // CHECK-INST: sqincp z0.h, p0.h
5965 // CHECK-ENCODING: [0x00,0x80,0x68,0x25]
6066 // CHECK-ERROR: instruction requires: sve
6167 // CHECK-UNKNOWN: 00 80 68 25
6268
6369 sqincp z0.s, p0
64 // CHECK-INST: sqincp z0.s, p0
70 // CHECK-INST: sqincp z0.s, p0.s
71 // CHECK-ENCODING: [0x00,0x80,0xa8,0x25]
72 // CHECK-ERROR: instruction requires: sve
73 // CHECK-UNKNOWN: 00 80 a8 25
74
75 sqincp z0.s, p0.s
76 // CHECK-INST: sqincp z0.s, p0.s
6577 // CHECK-ENCODING: [0x00,0x80,0xa8,0x25]
6678 // CHECK-ERROR: instruction requires: sve
6779 // CHECK-UNKNOWN: 00 80 a8 25
6880
6981 sqincp z0.d, p0
70 // CHECK-INST: sqincp z0.d, p0
82 // CHECK-INST: sqincp z0.d, p0.d
83 // CHECK-ENCODING: [0x00,0x80,0xe8,0x25]
84 // CHECK-ERROR: instruction requires: sve
85 // CHECK-UNKNOWN: 00 80 e8 25
86
87 sqincp z0.d, p0.d
88 // CHECK-INST: sqincp z0.d, p0.d
7189 // CHECK-ENCODING: [0x00,0x80,0xe8,0x25]
7290 // CHECK-ERROR: instruction requires: sve
7391 // CHECK-UNKNOWN: 00 80 e8 25
82100 // CHECK-ERROR: instruction requires: sve
83101 // CHECK-UNKNOWN: e0 bc 20 04
84102
85 sqincp z0.d, p0
86 // CHECK-INST: sqincp z0.d, p0
103 sqincp z0.d, p0.d
104 // CHECK-INST: sqincp z0.d, p0.d
87105 // CHECK-ENCODING: [0x00,0x80,0xe8,0x25]
88106 // CHECK-ERROR: instruction requires: sve
89107 // CHECK-UNKNOWN: 00 80 e8 25
5555 // CHECK-UNKNOWN: ff 89 eb 25
5656
5757 uqdecp z0.h, p0
58 // CHECK-INST: uqdecp z0.h, p0
58 // CHECK-INST: uqdecp z0.h, p0.h
59 // CHECK-ENCODING: [0x00,0x80,0x6b,0x25]
60 // CHECK-ERROR: instruction requires: sve
61 // CHECK-UNKNOWN: 00 80 6b 25
62
63 uqdecp z0.h, p0.h
64 // CHECK-INST: uqdecp z0.h, p0.h
5965 // CHECK-ENCODING: [0x00,0x80,0x6b,0x25]
6066 // CHECK-ERROR: instruction requires: sve
6167 // CHECK-UNKNOWN: 00 80 6b 25
6268
6369 uqdecp z0.s, p0
64 // CHECK-INST: uqdecp z0.s, p0
70 // CHECK-INST: uqdecp z0.s, p0.s
71 // CHECK-ENCODING: [0x00,0x80,0xab,0x25]
72 // CHECK-ERROR: instruction requires: sve
73 // CHECK-UNKNOWN: 00 80 ab 25
74
75 uqdecp z0.s, p0.s
76 // CHECK-INST: uqdecp z0.s, p0.s
6577 // CHECK-ENCODING: [0x00,0x80,0xab,0x25]
6678 // CHECK-ERROR: instruction requires: sve
6779 // CHECK-UNKNOWN: 00 80 ab 25
6880
6981 uqdecp z0.d, p0
70 // CHECK-INST: uqdecp z0.d, p0
82 // CHECK-INST: uqdecp z0.d, p0.d
83 // CHECK-ENCODING: [0x00,0x80,0xeb,0x25]
84 // CHECK-ERROR: instruction requires: sve
85 // CHECK-UNKNOWN: 00 80 eb 25
86
87 uqdecp z0.d, p0.d
88 // CHECK-INST: uqdecp z0.d, p0.d
7189 // CHECK-ENCODING: [0x00,0x80,0xeb,0x25]
7290 // CHECK-ERROR: instruction requires: sve
7391 // CHECK-UNKNOWN: 00 80 eb 25
82100 // CHECK-ERROR: instruction requires: sve
83101 // CHECK-UNKNOWN: e0 bc 20 04
84102
85 uqdecp z0.d, p0
86 // CHECK-INST: uqdecp z0.d, p0
103 uqdecp z0.d, p0.d
104 // CHECK-INST: uqdecp z0.d, p0.d
87105 // CHECK-ENCODING: [0x00,0x80,0xeb,0x25]
88106 // CHECK-ERROR: instruction requires: sve
89107 // CHECK-UNKNOWN: 00 80 eb 25
5555 // CHECK-UNKNOWN: ff 89 e9 25
5656
5757 uqincp z0.h, p0
58 // CHECK-INST: uqincp z0.h, p0
58 // CHECK-INST: uqincp z0.h, p0.h
59 // CHECK-ENCODING: [0x00,0x80,0x69,0x25]
60 // CHECK-ERROR: instruction requires: sve
61 // CHECK-UNKNOWN: 00 80 69 25
62
63 uqincp z0.h, p0.h
64 // CHECK-INST: uqincp z0.h, p0.h
5965 // CHECK-ENCODING: [0x00,0x80,0x69,0x25]
6066 // CHECK-ERROR: instruction requires: sve
6167 // CHECK-UNKNOWN: 00 80 69 25
6268
6369 uqincp z0.s, p0
64 // CHECK-INST: uqincp z0.s, p0
70 // CHECK-INST: uqincp z0.s, p0.s
71 // CHECK-ENCODING: [0x00,0x80,0xa9,0x25]
72 // CHECK-ERROR: instruction requires: sve
73 // CHECK-UNKNOWN: 00 80 a9 25
74
75 uqincp z0.s, p0.s
76 // CHECK-INST: uqincp z0.s, p0.s
6577 // CHECK-ENCODING: [0x00,0x80,0xa9,0x25]
6678 // CHECK-ERROR: instruction requires: sve
6779 // CHECK-UNKNOWN: 00 80 a9 25
6880
6981 uqincp z0.d, p0
70 // CHECK-INST: uqincp z0.d, p0
82 // CHECK-INST: uqincp z0.d, p0.d
83 // CHECK-ENCODING: [0x00,0x80,0xe9,0x25]
84 // CHECK-ERROR: instruction requires: sve
85 // CHECK-UNKNOWN: 00 80 e9 25
86
87 uqincp z0.d, p0.d
88 // CHECK-INST: uqincp z0.d, p0.d
7189 // CHECK-ENCODING: [0x00,0x80,0xe9,0x25]
7290 // CHECK-ERROR: instruction requires: sve
7391 // CHECK-UNKNOWN: 00 80 e9 25
82100 // CHECK-ERROR: instruction requires: sve
83101 // CHECK-UNKNOWN: e0 bc 20 04
84102
85 uqincp z0.d, p0
86 // CHECK-INST: uqincp z0.d, p0
103 uqincp z0.d, p0.d
104 // CHECK-INST: uqincp z0.d, p0.d
87105 // CHECK-ENCODING: [0x00,0x80,0xe9,0x25]
88106 // CHECK-ERROR: instruction requires: sve
89107 // CHECK-UNKNOWN: 00 80 e9 25