llvm.org GIT mirror llvm / 0fa1b6d
By default, spills kills the register being stored. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34515 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 12 years ago
5 changed file(s) with 32 addition(s) and 27 deletion(s). Raw diff Collapse all Expand all
6767 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
6868 if (RC == Alpha::F4RCRegisterClass)
6969 BuildMI(MBB, MI, TII.get(Alpha::STS))
70 .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
70 .addReg(SrcReg, false, false, true)
71 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
7172 else if (RC == Alpha::F8RCRegisterClass)
7273 BuildMI(MBB, MI, TII.get(Alpha::STT))
73 .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
74 .addReg(SrcReg, false, false, true)
75 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
7476 else if (RC == Alpha::GPRCRegisterClass)
7577 BuildMI(MBB, MI, TII.get(Alpha::STQ))
76 .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
78 .addReg(SrcReg, false, false, true)
79 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
7780 else
7881 abort();
7982 }
4141 const TargetRegisterClass *RC) const{
4242
4343 if (RC == IA64::FPRegisterClass) {
44 BuildMI(MBB, MI, TII.get(IA64::STF_SPILL)).addFrameIndex(FrameIdx).addReg(SrcReg);
44 BuildMI(MBB, MI, TII.get(IA64::STF_SPILL)).addFrameIndex(FrameIdx)
45 .addReg(SrcReg, false, false, true);
4546 } else if (RC == IA64::GRRegisterClass) {
46 BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(SrcReg);
47 }
48 else if (RC == IA64::PRRegisterClass) {
47 BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx)
48 .addReg(SrcReg, false, false, true);
49 } else if (RC == IA64::PRRegisterClass) {
4950 /* we use IA64::r2 as a temporary register for doing this hackery. */
5051 // first we load 0:
5152 BuildMI(MBB, MI, TII.get(IA64::MOV), IA64::r2).addReg(IA64::r0);
5253 // then conditionally add 1:
5354 BuildMI(MBB, MI, TII.get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2)
54 .addImm(1).addReg(SrcReg);
55 .addImm(1).addReg(SrcReg, false, false, true);
5556 // and then store it to the stack
5657 BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2);
5758 } else assert(0 &&
103103 const TargetRegisterClass *RC) const {
104104 if (RC == PPC::GPRCRegisterClass) {
105105 if (SrcReg != PPC::LR) {
106 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(SrcReg),
107 FrameIdx);
106 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW))
107 .addReg(SrcReg, false, false, true), FrameIdx);
108108 } else {
109109 // FIXME: this spills LR immediately to memory in one step. To do this,
110110 // we use R11, which we know cannot be used in the prolog/epilog. This is
111111 // a hack.
112112 BuildMI(MBB, MI, TII.get(PPC::MFLR), PPC::R11);
113 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(PPC::R11),
114 FrameIdx);
113 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW))
114 .addReg(PPC::R11, false, false, true), FrameIdx);
115115 }
116116 } else if (RC == PPC::G8RCRegisterClass) {
117117 if (SrcReg != PPC::LR8) {
118 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)).addReg(SrcReg),
119 FrameIdx);
118 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD))
119 .addReg(SrcReg, false, false, true), FrameIdx);
120120 } else {
121121 // FIXME: this spills LR immediately to memory in one step. To do this,
122122 // we use R11, which we know cannot be used in the prolog/epilog. This is
123123 // a hack.
124124 BuildMI(MBB, MI, TII.get(PPC::MFLR8), PPC::X11);
125 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)).addReg(PPC::X11),
126 FrameIdx);
125 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD))
126 .addReg(PPC::X11, false, false, true), FrameIdx);
127127 }
128128 } else if (RC == PPC::F8RCRegisterClass) {
129 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFD)).addReg(SrcReg),
130 FrameIdx);
129 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFD))
130 .addReg(SrcReg, false, false, true), FrameIdx);
131131 } else if (RC == PPC::F4RCRegisterClass) {
132 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFS)).addReg(SrcReg),
133 FrameIdx);
132 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFS))
133 .addReg(SrcReg, false, false, true), FrameIdx);
134134 } else if (RC == PPC::CRRCRegisterClass) {
135135 // FIXME: We use R0 here, because it isn't available for RA.
136136 // We need to store the CR in the low 4-bits of the saved value. First,
146146 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31);
147147 }
148148
149 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(PPC::R0),
150 FrameIdx);
149 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW))
150 .addReg(PPC::R0, false, false, true), FrameIdx);
151151 } else if (RC == PPC::VRRCRegisterClass) {
152152 // We don't have indexed addressing for vector loads. Emit:
153153 // R11 = ADDI FI#
157157 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),
158158 FrameIdx, 0, 0);
159159 BuildMI(MBB, MI, TII.get(PPC::STVX))
160 .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
160 .addReg(SrcReg, false, false, true).addReg(PPC::R0).addReg(PPC::R0);
161161 } else {
162162 assert(0 && "Unknown regclass!");
163163 abort();
3636 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
3737 if (RC == SP::IntRegsRegisterClass)
3838 BuildMI(MBB, I, TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
39 .addReg(SrcReg);
39 .addReg(SrcReg, false, false, true);
4040 else if (RC == SP::FPRegsRegisterClass)
4141 BuildMI(MBB, I, TII.get(SP::STFri)).addFrameIndex(FI).addImm(0)
42 .addReg(SrcReg);
42 .addReg(SrcReg, false, false, true);
4343 else if (RC == SP::DFPRegsRegisterClass)
4444 BuildMI(MBB, I, TII.get(SP::STDFri)).addFrameIndex(FI).addImm(0)
45 .addReg(SrcReg);
45 .addReg(SrcReg, false, false, true);
4646 else
4747 assert(0 && "Can't store this register to stack slot");
4848 }
9292 assert(0 && "Unknown regclass");
9393 abort();
9494 }
95 addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx).addReg(SrcReg);
95 addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx)
96 .addReg(SrcReg, false, false, true);
9697 }
9798
9899 void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,