llvm.org GIT mirror llvm / 0f4e225
[ARM] Make fullfp16 instructions not conditionalisable. More or less all the instructions defined in the v8.2a full-fp16 extension are defined as UNPREDICTABLE if you put them in an IT block (Thumb) or use with any condition other than AL (ARM). LLVM didn't know that, and was happy to conditionalise them. In order to force these instructions to count as not predicable, I had to make a small Tablegen change. The code generation back end mostly decides if an instruction was predicable by looking for something it can identify as a predicate operand; there's an isPredicable bit flag that overrides that check in the positive direction, but nothing that overrides it in the negative direction. (I considered the alternative approach of actually removing the predicate operand from those instructions, but thought that it would be more painful overall for instructions differing only in data type to have different shapes of operand list. This way, the only code that has to notice the difference is the if-converter.) So I've added an isUnpredicable bit alongside isPredicable, and set that bit on the right subset of FP16 instructions, and also on the VSEL, VMAXNM/VMINNM and VRINT[ANPM] families which should be unpredicable for all data types. I've included a couple of representative regression tests, both of which previously caused an fp16 instruction to be conditionalised in ARM state and (with -arm-no-restrict-it) to be put in an IT block in Thumb. Reviewers: SjoerdMeijer, t.p.northover, efriedma Reviewed By: efriedma Subscribers: jdoerfert, javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57823 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354768 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Tatham 1 year, 5 months ago
10 changed file(s) with 297 addition(s) and 10 deletion(s). Raw diff Collapse all Expand all
455455 bit isCommutable = 0; // Is this 3 operand instruction commutable?
456456 bit isTerminator = 0; // Is this part of the terminator for a basic block?
457457 bit isReMaterializable = 0; // Is this instruction re-materializable?
458 bit isPredicable = 0; // Is this instruction predicable?
458 bit isPredicable = 0; // 1 means this instruction is predicable
459 // even if it does not have any operand
460 // tablegen can identify as a predicate
461 bit isUnpredicable = 0; // 1 means this instruction is not predicable
462 // even if it _does_ have a predicate operand
459463 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
460464 bit usesCustomInserter = 0; // Pseudo instr needing special help.
461465 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
15541554
15551555 // Loads & stores operate on both NEON and VFP pipelines.
15561556 let D = VFPNeonDomain;
1557
1558 let isUnpredicable = 1; // FP16 instructions cannot in general be conditional
15571559 }
15581560
15591561 // VFP Load / store multiple pseudo instructions.
19011903 let Inst{11-8} = 0b1001; // Half precision
19021904 let Inst{7-6} = opcod4;
19031905 let Inst{4} = opcod5;
1906
1907 let isUnpredicable = 1; // FP16 instructions cannot in general be conditional
19041908 }
19051909
19061910 // Half precision, unary, non-predicated
19291933 let Inst{11-8} = 0b1001; // Half precision
19301934 let Inst{7-6} = opcod4;
19311935 let Inst{4} = opcod5;
1936
1937 let isUnpredicable = 1; // FP16 instructions cannot in general be conditional
19321938 }
19331939
19341940 // Half precision, binary
19551961 let Inst{11-8} = 0b1001; // Half precision
19561962 let Inst{6} = op6;
19571963 let Inst{4} = op4;
1964
1965 let isUnpredicable = 1; // FP16 instructions cannot in general be conditional
19581966 }
19591967
19601968 // Half precision, binary, not predicated
19841992 let Inst{11-8} = 0b1001; // Half precision
19851993 let Inst{6} = opcod3;
19861994 let Inst{4} = 0;
1995
1996 let isUnpredicable = 1; // FP16 instructions cannot in general be conditional
19871997 }
19881998
19891999 // VFP conversion instructions
128128 let D = VFPNeonDomain;
129129 }
130130
131 let isUnpredicable = 1 in
131132 def VLDRH : AHI5<0b1101, 0b01, (outs HPR:$Sd), (ins addrmode5fp16:$addr),
132133 IIC_fpLoad16, "vldr", ".16\t$Sd, $addr",
133134 [(set HPR:$Sd, (alignedload16 addrmode5fp16:$addr))]>,
147148 let D = VFPNeonDomain;
148149 }
149150
151 let isUnpredicable = 1 in
150152 def VSTRH : AHI5<0b1101, 0b00, (outs), (ins HPR:$Sd, addrmode5fp16:$addr),
151153 IIC_fpStore16, "vstr", ".16\t$Sd, $addr",
152154 [(alignedstore16 HPR:$Sd, addrmode5fp16:$addr)]>,
450452
451453 multiclass vsel_inst opc, int CC> {
452454 let DecoderNamespace = "VFPV8", PostEncoderMethod = "",
453 Uses = [CPSR], AddedComplexity = 4 in {
455 Uses = [CPSR], AddedComplexity = 4, isUnpredicable = 1 in {
454456 def H : AHbInp<0b11100, opc, 0,
455457 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
456458 NoItinerary, !strconcat("vsel", op, ".f16\t$Sd, $Sn, $Sm"),
478480 defm VSELVS : vsel_inst<"vs", 0b01, 6>;
479481
480482 multiclass vmaxmin_inst {
481 let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in {
483 let DecoderNamespace = "VFPV8", PostEncoderMethod = "",
484 isUnpredicable = 1 in {
482485 def H : AHbInp<0b11101, 0b00, opc,
483486 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
484487 NoItinerary, !strconcat(op, ".f16\t$Sd, $Sn, $Sm"),
946949
947950 multiclass vrint_inst_anpm rm,
948951 SDPatternOperator node = null_frag> {
949 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
952 let PostEncoderMethod = "", DecoderNamespace = "VFPV8",
953 isUnpredicable = 1 in {
950954 def H : AHuInp<0b11101, 0b11, 0b1000, 0b01, 0,
951955 (outs SPR:$Sd), (ins SPR:$Sm),
952956 NoItinerary, !strconcat("vrint", opc, ".f16\t$Sd, $Sm"),
10111015 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
10121016 } // isMoveReg
10131017
1014 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
1018 let PostEncoderMethod = "", DecoderNamespace = "VFPV8", isUnpredicable = 1 in {
10151019 def VMOVH : ASuInp<0b11101, 0b11, 0b0000, 0b01, 0,
10161020 (outs SPR:$Sd), (ins SPR:$Sm),
10171021 IIC_fpUNA16, "vmovx.f16\t$Sd, $Sm", []>,
12201224
12211225 let Inst{6-5} = 0b00;
12221226 let Inst{3-0} = 0b0000;
1227
1228 let isUnpredicable = 1;
12231229 }
12241230
12251231 // Move R->H, clearing top 16 bits
12401246
12411247 let Inst{6-5} = 0b00;
12421248 let Inst{3-0} = 0b0000;
1249
1250 let isUnpredicable = 1;
12431251 }
12441252
12451253 // FMRDH: SPR -> GPR
13461354 []>,
13471355 Sched<[WriteFPCVT]> {
13481356 let Inst{7} = 1; // s32
1357 let isUnpredicable = 1;
13491358 }
13501359
13511360 def : VFPNoNEONPat<(f16 (sint_to_fp GPR:$a)),
13911400 []>,
13921401 Sched<[WriteFPCVT]> {
13931402 let Inst{7} = 0; // u32
1403 let isUnpredicable = 1;
13941404 }
13951405
13961406 def : VFPNoNEONPat<(f16 (uint_to_fp GPR:$a)),
14951505 []>,
14961506 Sched<[WriteFPCVT]> {
14971507 let Inst{7} = 1; // Z bit
1508 let isUnpredicable = 1;
14981509 }
14991510
15001511 def : VFPNoNEONPat<(i32 (fp_to_sint HPR:$a)),
15411552 []>,
15421553 Sched<[WriteFPCVT]> {
15431554 let Inst{7} = 1; // Z bit
1555 let isUnpredicable = 1;
15441556 }
15451557
15461558 def : VFPNoNEONPat<(i32 (fp_to_uint HPR:$a)),
15701582 []>,
15711583 Sched<[WriteFPCVT]> {
15721584 let Inst{7} = 0; // Z bit
1585 let isUnpredicable = 1;
15731586 }
15741587
15751588 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
15941607 []>,
15951608 Sched<[WriteFPCVT]> {
15961609 let Inst{7} = 0; // Z bit
1610 let isUnpredicable = 1;
15971611 }
15981612 }
15991613
16411655 let Predicates = [HasVFP2, HasDPVFP];
16421656 }
16431657
1658 let isUnpredicable = 1 in {
1659
16441660 def VTOSHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 0,
16451661 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
16461662 IIC_fpCVTHI, "vcvt", ".s16.f16\t$dst, $a, $fbits", []>,
16651681 Requires<[HasFullFP16]>,
16661682 Sched<[WriteFPCVT]>;
16671683
1684 } // End of 'let isUnpredicable = 1 in'
1685
16681686 def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0,
16691687 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
16701688 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []>,
17191737 Sched<[WriteFPCVT]>;
17201738
17211739 // Fixed-Point to FP:
1740
1741 let isUnpredicable = 1 in {
17221742
17231743 def VSHTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1001, 0,
17241744 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
17431763 IIC_fpCVTIH, "vcvt", ".f16.u32\t$dst, $a, $fbits", []>,
17441764 Requires<[HasFullFP16]>,
17451765 Sched<[WriteFPCVT]>;
1766
1767 } // End of 'let isUnpredicable = 1 in'
17461768
17471769 def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0,
17481770 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
23692391 let Inst{11-8} = 0b1001; // Half precision
23702392 let Inst{7-4} = 0b0000;
23712393 let Inst{3-0} = imm{3-0};
2394
2395 let isUnpredicable = 1;
23722396 }
23732397 }
23742398
64776477 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
64786478 ARMCC::AL) {
64796479 return Warning(Loc, "predicated instructions should be in IT block");
6480 } else if (!MCID.isPredicable()) {
6481 // Check the instruction doesn't have a predicate operand anyway
6482 // that it's not allowed to use. Sometimes this happens in order
6483 // to keep instructions the same shape even though one cannot
6484 // legally be predicated, e.g. vmul.f16 vs vmul.f32.
6485 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
6486 if (MCID.OpInfo[i].isPredicate()) {
6487 if (Inst.getOperand(i).getImm() != ARMCC::AL)
6488 return Error(Loc, "instruction is not predicable");
6489 break;
6490 }
6491 }
64806492 }
64816493
64826494 // PC-setting instructions in an IT block, but not the last instruction of
118118 mutable ITStatus ITBlock;
119119
120120 DecodeStatus AddThumbPredicate(MCInst&) const;
121 void UpdateThumbVFPPredicate(MCInst&) const;
121 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const;
122122 };
123123
124124 } // end anonymous namespace
629629 for (unsigned i = 0; i < NumOps; ++i, ++I) {
630630 if (I == MI.end()) break;
631631 if (OpInfo[i].isPredicate()) {
632 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable())
633 Check(S, SoftFail);
632634 I = MI.insert(I, MCOperand::createImm(CC));
633635 ++I;
634636 if (CC == ARMCC::AL)
654656 // mode, the auto-generated decoder will give them an (incorrect)
655657 // predicate operand. We need to rewrite these operands based on the IT
656658 // context as a post-pass.
657 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
659 void ThumbDisassembler::UpdateThumbVFPPredicate(
660 DecodeStatus &S, MCInst &MI) const {
658661 unsigned CC;
659662 CC = ITBlock.getITCC();
660663 if (CC == 0xF)
667670 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
668671 for (unsigned i = 0; i < NumOps; ++i, ++I) {
669672 if (OpInfo[i].isPredicate() ) {
673 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable())
674 Check(S, SoftFail);
670675 I->setImm(CC);
671676 ++I;
672677 if (CC == ARMCC::AL)
772777 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
773778 if (Result != MCDisassembler::Fail) {
774779 Size = 4;
775 UpdateThumbVFPPredicate(MI);
780 UpdateThumbVFPPredicate(Result, MI);
776781 return Result;
777782 }
778783 }
11091114
11101115 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
11111116 uint64_t Address, const void *Decoder) {
1117 DecodeStatus S = MCDisassembler::Success;
11121118 if (Val == 0xF) return MCDisassembler::Fail;
11131119 // AL predicate is not allowed on Thumb1 branches.
11141120 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
11151121 return MCDisassembler::Fail;
1122 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable())
1123 Check(S, MCDisassembler::SoftFail);
11161124 Inst.addOperand(MCOperand::createImm(Val));
11171125 if (Val == ARMCC::AL) {
11181126 Inst.addOperand(MCOperand::createReg(0));
11191127 } else
11201128 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1121 return MCDisassembler::Success;
1129 return S;
11221130 }
11231131
11241132 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
0 ; RUN: llc -O3 -mtriple=armv8a-none-eabi -mattr=+fullfp16 -o - %s | FileCheck %s
1 ; RUN: llc -O3 -mtriple=thumbv8a-none-eabi -mattr=+fullfp16 -arm-no-restrict-it -o - %s | FileCheck %s
2
3 ; Require the vmul.f16 not to be predicated, because it's illegal to
4 ; do so with fp16 instructions
5 define half @conditional_fmul_f16(half* %p) {
6 ; CHECK-LABEL: conditional_fmul_f16:
7 ; CHECK: vmul.f16
8 entry:
9 %p1 = getelementptr half, half* %p, i32 1
10 %a = load half, half* %p, align 2
11 %threshold = load half, half* %p1, align 2
12 %flag = fcmp ogt half %a, %threshold
13 br i1 %flag, label %mul, label %out
14
15 mul:
16 %p2 = getelementptr half, half* %p, i32 2
17 %mult = load half, half* %p2, align 2
18 %b = fmul half %a, %mult
19 br label %out
20
21 out:
22 %sel = phi half [ %a, %entry ], [ %b, %mul ]
23 ret half %sel
24 }
25
26 ; Expect that the corresponding vmul.f32 _will_ be predicated (to make
27 ; sure the previous test is really testing something)
28 define float @conditional_fmul_f32(float* %p) {
29 ; CHECK-LABEL: conditional_fmul_f32:
30 ; CHECK: vmulgt.f32
31 entry:
32 %p1 = getelementptr float, float* %p, i32 1
33 %a = load float, float* %p, align 2
34 %threshold = load float, float* %p1, align 2
35 %flag = fcmp ogt float %a, %threshold
36 br i1 %flag, label %mul, label %out
37
38 mul:
39 %p2 = getelementptr float, float* %p, i32 2
40 %mult = load float, float* %p2, align 2
41 %b = fmul float %a, %mult
42 br label %out
43
44 out:
45 %sel = phi float [ %a, %entry ], [ %b, %mul ]
46 ret float %sel
47 }
48
49 ; Require the two comparisons to be done with unpredicated vcmp.f16
50 ; instructions (again, it is illegal to predicate them)
51 define void @chained_comparisons_f16(half* %p) {
52 ; CHECK-LABEL: chained_comparisons_f16:
53 ; CHECK: vcmp.f16
54 ; CHECK: vcmp.f16
55 entry:
56 %p1 = getelementptr half, half* %p, i32 1
57
58 %a = load half, half* %p, align 2
59 %b = load half, half* %p1, align 2
60
61 %aflag = fcmp oeq half %a, 0xH0000
62 %bflag = fcmp oeq half %b, 0xH0000
63 %flag = or i1 %aflag, %bflag
64 br i1 %flag, label %call, label %out
65
66 call:
67 call void @external_function()
68 br label %out
69
70 out:
71 ret void
72 }
73
74 ; Again, do the corresponding test with 32-bit floats and check that
75 ; the second comparison _is_ predicated on the result of the first.
76 define void @chained_comparisons_f32(float* %p) {
77 ; CHECK-LABEL: chained_comparisons_f32:
78 ; CHECK: vcmp.f32
79 ; CHECK: vcmpne.f32
80 entry:
81 %p1 = getelementptr float, float* %p, i32 1
82
83 %a = load float, float* %p, align 2
84 %b = load float, float* %p1, align 2
85
86 %aflag = fcmp oeq float %a, 0x00000000
87 %bflag = fcmp oeq float %b, 0x00000000
88 %flag = or i1 %aflag, %bflag
89 br i1 %flag, label %call, label %out
90
91 call:
92 call void @external_function()
93 br label %out
94
95 out:
96 ret void
97 }
98
99 declare void @external_function()
0 @ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16 < %s 2>&1 | FileCheck %s
1 @ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16,+thumb-mode -arm-implicit-it always < %s 2>&1 | FileCheck %s
2
3 vaddeq.f16 s0, s1, s0
4 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
5
6 vsubne.f16 s0, s1, s0
7 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
8
9 vdivmi.f16 s0, s1, s0
10 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
11
12 vmulpl.f16 s0, s1, s0
13 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
14
15 vnmulvs.f16 s0, s1, s0
16 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
17
18 vmlavc.f16 s1, s2, s0
19 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
20
21 vmlshs.f16 s1, s2, s0
22 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
23
24 vnmlalo.f16 s1, s2, s0
25 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
26
27 vnmlscs.f16 s1, s2, s0
28 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
29
30 vcmpcc.f16 s0, s1
31 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
32
33 vcmphi.f16 s2, #0
34 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
35
36 vcmpels.f16 s1, s0
37 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
38
39 vcmpege.f16 s0, #0
40 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
41
42 vabslt.f16 s0, s0
43 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
44
45 vneggt.f16 s0, s0
46 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
47
48 vsqrtle.f16 s0, s0
49 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
50
51 vcvteq.f16.s32 s0, s0
52 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
53
54 vcvtne.u32.f16 s0, s0
55 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
56
57 vcvtrmi.s32.f16 s0, s1
58 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
59
60 vrintzhs.f16 s3, s24
61 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
62
63 vrintrlo.f16 s0, s9
64 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
65
66 vrintxcs.f16 s10, s14
67 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
68
69 vfmalt.f16 s2, s7, s4
70 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
71
72 vfmsgt.f16 s2, s7, s4
73 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
74
75 vfnmale.f16 s2, s7, s4
76 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
77
78 vfnmseq.f16 s2, s7, s4
79 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
80
81 vldrpl.16 s1, [pc, #6]
82 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
83
84 vldrvs.16 s2, [pc, #510]
85 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
86
87 vldrvc.16 s3, [pc, #-510]
88 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
89
90 vldrhs.16 s4, [r4, #-18]
91 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
92
93 vstrlo.16 s1, [pc, #6]
94 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
95
96 vstrcs.16 s2, [pc, #510]
97 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
98
99 vstrcc.16 s3, [pc, #-510]
100 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
101
102 vstrhi.16 s4, [r4, #-18]
103 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
104
105 vmovls.f16 s0, #1.0
106 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
107
108 vmovge.f16 s1, r2
109 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
110
111 vmovlt.f16 r3, s4
112 @ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
0 # RUN: llvm-mc -disassemble -triple armv8a-none-eabi -mattr=+fullfp16 -show-encoding < %s 2>&1 | FileCheck %s
1
2 # CHECK: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
3 [0x80,0x09,0x30,0xae]
4 # CHECK-NOT: [[@LINE+1]]:2: warning
5 [0x80,0x0a,0x30,0xae]
0 # RUN: llvm-mc -disassemble -triple thumbv8a-none-eabi -mattr=+fullfp16,+thumb-mode -show-encoding < %s 2>&1 | FileCheck %s
1
2 # CHECK: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
3 [0xc8,0xbf]
4 [0x30,0xee,0x81,0x09]
5
6 # CHECK-NOT: [[@LINE+2]]:2: warning
7 [0xc8,0xbf]
8 [0x30,0xee,0x81,0x0a]
376376 isAdd = R->getValueAsBit("isAdd");
377377 isTrap = R->getValueAsBit("isTrap");
378378 canFoldAsLoad = R->getValueAsBit("canFoldAsLoad");
379 isPredicable = Operands.isPredicable || R->getValueAsBit("isPredicable");
379 isPredicable = !R->getValueAsBit("isUnpredicable") && (
380 Operands.isPredicable || R->getValueAsBit("isPredicable"));
380381 isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress");
381382 isCommutable = R->getValueAsBit("isCommutable");
382383 isTerminator = R->getValueAsBit("isTerminator");