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getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28378 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 13 years ago
18 changed file(s) with 179 addition(s) and 92 deletion(s). Raw diff Collapse all Expand all
3939 //===----------------------------------------------------------------------===//
4040
4141 def ARM : Target {
42 // FIXME: Specify callee-saved registers
43 let CalleeSavedRegisters = [];
44
4542 // Pull in Instruction Info:
4643 let InstructionSet = ARMInstrInfo;
4744 }
5757 return NULL;
5858 }
5959
60 const unsigned* ARMRegisterInfo::getCalleeSaveRegs() const {
61 static const unsigned CalleeSaveRegs[] = { 0 };
62 return CalleeSaveRegs;
63 }
64
65 const TargetRegisterClass* const *
66 ARMRegisterInfo::getCalleeSaveRegClasses() const {
67 static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 0 };
68 return CalleeSaveRegClasses;
69 }
70
6071 void ARMRegisterInfo::
6172 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
6273 MachineBasicBlock::iterator I) const {
4444 unsigned OpNum,
4545 int FrameIndex) const;
4646
47 const unsigned *getCalleeSaveRegs() const;
48
49 const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
50
4751 void eliminateCallFramePseudoInstr(MachineFunction &MF,
4852 MachineBasicBlock &MBB,
4953 MachineBasicBlock::iterator I) const;
6464
6565
6666 def Alpha : Target {
67 let CalleeSavedRegisters =
68 //saved regs
69 [R9, R10, R11, R12, R13, R14,
70 //Frame pointer
71 // R15,
72 //return address
73 // R26,
74 //Stack Pointer
75 // R30,
76 F2, F3, F4, F5, F6, F7, F8, F9];
77
7867 // Pull in Instruction Info:
7968 let InstructionSet = AlphaInstrInfo;
8069 }
144144 }
145145 }
146146
147 const unsigned* AlphaRegisterInfo::getCalleeSaveRegs() const {
148 static const unsigned CalleeSaveRegs[] = {
149 Alpha::R9, Alpha::R10,
150 Alpha::R11, Alpha::R12,
151 Alpha::R13, Alpha::R14,
152 Alpha::F2, Alpha::F3,
153 Alpha::F4, Alpha::F5,
154 Alpha::F6, Alpha::F7,
155 Alpha::F8, Alpha::F9, 0
156 };
157 return CalleeSaveRegs;
158 }
159
160 const TargetRegisterClass* const*
161 AlphaRegisterInfo::getCalleeSaveRegClasses() const {
162 static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
163 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
164 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
165 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
166 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
167 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
168 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
169 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, 0
170 };
171 return CalleeSaveRegClasses;
172 }
173
147174 //===----------------------------------------------------------------------===//
148175 // Stack Frame Processing methods
149176 //===----------------------------------------------------------------------===//
4141 unsigned DestReg, unsigned SrcReg,
4242 const TargetRegisterClass *RC) const;
4343
44 const unsigned *getCalleeSaveRegs() const;
45
46 const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
47
4448 void eliminateCallFramePseudoInstr(MachineFunction &MF,
4549 MachineBasicBlock &MBB,
4650 MachineBasicBlock::iterator I) const;
3030 def IA64InstrInfo : InstrInfo { }
3131
3232 def IA64 : Target {
33 // The following registers are always saved across calls:
34 let CalleeSavedRegisters =
35
36 //'preserved' GRs:
37
38 [
39 r5 // the 'frame pointer' (base pointer) reg
40
41 // We never generate references to these regs, so we don't need to declare
42 // that they are saved. In fact, we could just remove them entirely.
43 //r4, r6, r7,
44
45 //'special' GRs:
46
47 // r1, // global data pointer (GP) - XXX NOT callee saved, we do it ourselves
48 // r12, // memory stack pointer (SP)- XXX NOT callee saved, we do it ourselves
49 // rp, // return branch register (rp/b0) - we do this ourselves
50 // **** r13 (thread pointer) we do not touch, ever. it's not here. ****//
51
52 //'stacked' GRs the RSE takes care of, we don't worry about
53 /* We don't want PEI::calculateCallerSavedRegisters to worry about them,
54 since the RSE takes care of them (and we determinethe appropriate
55 'alloc' instructions and save/restore ar.pfs ourselves, in instruction
56 selection)
57
58 **************************************************************************
59 * r32, r33, r34, r35,
60 * r36, r37, r38, r39, r40, r41, r42, r43, r44, r45, r46, r47,
61 * r48, r49, r50, r51, r52, r53, r54, r55, r56, r57, r58, r59,
62 * r60, r61, r62, r63, r64, r65, r66, r67, r68, r69, r70, r71,
63 * r72, r73, r74, r75, r76, r77, r78, r79, r80, r81, r82, r83,
64 * r84, r85, r86, r87, r88, r89, r90, r91, r92, r93, r94, r95,
65 * r96, r97, r98, r99, r100, r101, r102, r103, r104, r105, r106, r107,
66 * r108, r109, r110, r111, r112, r113, r114, r115, r116, r117, r118, r119,
67 * r120, r121, r122, r123, r124, r125, r126, r127,
68 **************************************************************************
69 */
70 //'preserved' FP regs:
71
72 /* We never generate references to these regs, so we don't need to declare
73 * that they are saved. In fact, we could just remove them entirely.
74 * F2,F3,F4, F5,
75 * F16,F17,F18,F19,F20,F21,F22,F23,
76 * F24,F25,F26,F27,F28,F29,F30,F31,
77 */
78
79 //'preserved' predicate regs:
80
81 /* We never generate references to these regs, so we don't need to declare
82 that they are saved. In fact, we could just remove them entirely.
83 p1, p2, p3, p4, p5,
84 p16, p17, p18, p19, p20, p21, p22, p23,
85 p24, p25, p26, p27, p28, p29, p30, p31,
86 p32, p33, p34, p35, p36, p37, p38, p39,
87 p40, p41, p42, p43, p44, p45, p46, p47,
88 p48, p49, p50, p51, p52, p53, p54, p55,
89 p56, p57, p58, p59, p60, p61, p62, p63
90 */
91 ];
92
9333 // Our instruction set
9434 let InstructionSet = IA64InstrInfo;
9535
8787 BuildMI(MBB, MI, IA64::PCMPEQUNC, 3, DestReg).addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
8888 else // otherwise, MOV works (for both gen. regs and FP regs)
8989 BuildMI(MBB, MI, IA64::MOV, 1, DestReg).addReg(SrcReg);
90 }
91
92 const unsigned* IA64RegisterInfo::getCalleeSaveRegs() const {
93 static const unsigned CalleeSaveRegs[] = {
94 IA64::r5, 0
95 };
96 return CalleeSaveRegs;
97 }
98
99 const TargetRegisterClass* const*
100 IA64RegisterInfo::getCalleeSaveRegClasses() const {
101 static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
102 &IA64::GRRegClass, 0
103 };
104 return CalleeSaveRegClasses;
90105 }
91106
92107 //===----------------------------------------------------------------------===//
3939 unsigned DestReg, unsigned SrcReg,
4040 const TargetRegisterClass *RC) const;
4141
42 const unsigned *getCalleeSaveRegs() const;
43
44 const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
45
4246 void eliminateCallFramePseudoInstr(MachineFunction &MF,
4347 MachineBasicBlock &MBB,
4448 MachineBasicBlock::iterator MI) const;
8282 def PPC : Target {
8383 // Information about the instructions.
8484 let InstructionSet = PPCInstrInfo;
85
86
87 // According to the Mach-O Runtime ABI, these regs are nonvolatile across
88 // calls
89 let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
90 R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
91 F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
92 F30, F31, CR2, CR3, CR4, V20, V21, V22, V23, V24, V25, V26, V27, V28,
93 V29, V30, V31, LR];
9485 }
181181 }
182182 }
183183
184 const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const {
185 static const unsigned CalleeSaveRegs[] = {
186 PPC::R1, PPC::R13,
187 PPC::R14, PPC::R15,
188 PPC::R16, PPC::R17,
189 PPC::R18, PPC::R19,
190 PPC::R20, PPC::R21,
191 PPC::R22, PPC::R23,
192 PPC::R24, PPC::R25,
193 PPC::R26, PPC::R27,
194 PPC::R28, PPC::R29,
195 PPC::R30, PPC::R31,
196 PPC::F14, PPC::F15,
197 PPC::F16, PPC::F17,
198 PPC::F18, PPC::F19,
199 PPC::F20, PPC::F21,
200 PPC::F22, PPC::F23,
201 PPC::F24, PPC::F25,
202 PPC::F26, PPC::F27,
203 PPC::F28, PPC::F29,
204 PPC::F30, PPC::F31,
205 PPC::CR2, PPC::CR3,
206 PPC::CR4, PPC::V20,
207 PPC::V21, PPC::V22,
208 PPC::V23, PPC::V24,
209 PPC::V25, PPC::V26,
210 PPC::V27, PPC::V28,
211 PPC::V29, PPC::V30,
212 PPC::V31, PPC::LR, 0
213 };
214 return CalleeSaveRegs;
215 }
216
217 const TargetRegisterClass* const*
218 PPCRegisterInfo::getCalleeSaveRegClasses() const {
219 static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
220 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
221 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
222 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
223 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
224 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
225 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
226 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
227 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
228 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
229 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
230 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
231 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
232 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
233 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
234 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
235 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
236 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
237 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
238 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
239 &PPC::CRRCRegClass, &PPC::CRRCRegClass,
240 &PPC::CRRCRegClass, &PPC::VRRCRegClass,
241 &PPC::VRRCRegClass, &PPC::VRRCRegClass,
242 &PPC::VRRCRegClass, &PPC::VRRCRegClass,
243 &PPC::VRRCRegClass, &PPC::VRRCRegClass,
244 &PPC::VRRCRegClass, &PPC::VRRCRegClass,
245 &PPC::VRRCRegClass, &PPC::VRRCRegClass,
246 &PPC::VRRCRegClass, &PPC::GPRCRegClass, 0
247 };
248 return CalleeSaveRegClasses;
249 }
250
184251 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
185252 /// copy instructions, turning them into load/store instructions.
186253 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
5050 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
5151 int FrameIndex) const;
5252
53 const unsigned *getCalleeSaveRegs() const;
54
55 const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
56
5357 void eliminateCallFramePseudoInstr(MachineFunction &MF,
5458 MachineBasicBlock &MBB,
5559 MachineBasicBlock::iterator I) const;
7474 //===----------------------------------------------------------------------===//
7575
7676 def Sparc : Target {
77 // FIXME: Specify callee-saved registers
78 let CalleeSavedRegisters = [];
79
8077 // Pull in Instruction Info:
8178 let InstructionSet = SparcInstrInfo;
8279 }
102102 return 0;
103103 }
104104
105 const unsigned* SparcRegisterInfo::getCalleeSaveRegs() const {
106 static const unsigned CalleeSaveRegs[] = { 0 };
107 return CalleeSaveRegs;
108 }
109
110 const TargetRegisterClass* const*
111 SparcRegisterInfo::getCalleeSaveRegClasses() const {
112 static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 0 };
113 return CalleeSaveRegClasses;
114 }
115
116
105117 void SparcRegisterInfo::
106118 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
107119 MachineBasicBlock::iterator I) const {
4545 unsigned OpNum,
4646 int FrameIndex) const;
4747
48 const unsigned *getCalleeSaveRegs() const;
49
50 const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
51
4852 void eliminateCallFramePseudoInstr(MachineFunction &MF,
4953 MachineBasicBlock &MBB,
5054 MachineBasicBlock::iterator I) const;
129129
130130
131131 def X86 : Target {
132 // Specify the callee saved registers.
133 let CalleeSavedRegisters = [ESI, EDI, EBX, EBP];
134
135132 // Information about the instructions...
136133 let InstructionSet = X86InstrInfo;
137134
599599 return NULL;
600600 }
601601
602 const unsigned *X86RegisterInfo::getCalleeSaveRegs() const {
603 static const unsigned CalleeSaveRegs[] = {
604 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
605 };
606 return CalleeSaveRegs;
607 }
608
609 const TargetRegisterClass* const*
610 X86RegisterInfo::getCalleeSaveRegClasses() const {
611 static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
612 &X86::GR32RegClass, &X86::GR32RegClass,
613 &X86::GR32RegClass, &X86::GR32RegClass, 0
614 };
615 return CalleeSaveRegClasses;
616 }
617
602618 //===----------------------------------------------------------------------===//
603619 // Stack Frame Processing methods
604620 //===----------------------------------------------------------------------===//
4646 /// folding and return true, otherwise it should return false. If it folds
4747 /// the instruction, it is likely that the MachineInstruction the iterator
4848 /// references has been changed.
49 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
50 unsigned OpNum,
51 int FrameIndex) const;
49 MachineInstr* foldMemoryOperand(MachineInstr* MI,
50 unsigned OpNum,
51 int FrameIndex) const;
5252
53 /// getCalleeSaveRegs - Return a null-terminated list of all of the
54 /// callee-save registers on this target.
55 const unsigned *getCalleeSaveRegs() const;
56
57 /// getCalleeSaveRegClasses - Return a null-terminated list of the preferred
58 /// register classes to spill each callee-saved register with. The order and
59 /// length of this list match the getCalleeSaveRegs() list.
60 const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
5361
5462 void eliminateCallFramePseudoInstr(MachineFunction &MF,
5563 MachineBasicBlock &MBB,