llvm.org GIT mirror llvm / 0f2e653
R600/SI: Expand all v8[if]32 operations git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201371 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 6 years ago
5 changed file(s) with 95 addition(s) and 17 deletion(s). Raw diff Collapse all Expand all
119119
120120 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
121121 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
122 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
123 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
124 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
122125 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
123 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
126 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
127 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
128 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
129 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
124130
125131 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand);
126132 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
9696 setOperationAction(ISD::LOAD, MVT::i64, Custom);
9797 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
9898 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
99 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
99100
100101 setOperationAction(ISD::STORE, MVT::i32, Custom);
101102 setOperationAction(ISD::STORE, MVT::i64, Custom);
145146 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
146147 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
147148 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
149
150 // We only support LOAD/STORE and vector manipulation ops for vectors
151 // with > 4 elements.
152 MVT VecTypes[] = {
153 MVT::v8i32, MVT::v8f32
154 };
155
156 const size_t NumVecTypes = array_lengthof(VecTypes);
157 for (unsigned Type = 0; Type < NumVecTypes; ++Type) {
158 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
159 switch(Op) {
160 case ISD::LOAD:
161 case ISD::STORE:
162 case ISD::BUILD_VECTOR:
163 case ISD::BITCAST:
164 case ISD::EXTRACT_VECTOR_ELT:
165 case ISD::INSERT_VECTOR_ELT:
166 case ISD::CONCAT_VECTORS:
167 case ISD::INSERT_SUBVECTOR:
168 case ISD::EXTRACT_SUBVECTOR:
169 break;
170 default:
171 setOperationAction(Op, VecTypes[Type], Expand);
172 break;
173 }
174 }
175 }
148176
149177 setTargetDAGCombine(ISD::SELECT_CC);
150178
16671667 def : BitConvert ;
16681668 def : BitConvert ;
16691669
1670 def : BitConvert ;
1671 def : BitConvert ;
16701672 def : BitConvert ;
16711673 def : BitConvert ;
16721674 def : BitConvert ;
None ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
1 ; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
0 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK --check-prefix=FUNC %s
1 ; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=FUNC %s
22
3 ;EG-CHECK-LABEL: @test1:
3 ;FUNC-LABEL: @test1:
44 ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
55
6 ;SI-CHECK-LABEL: @test1:
76 ;SI-CHECK: V_ADD_I32_e32 [[REG:v[0-9]+]], {{v[0-9]+, v[0-9]+}}
87 ;SI-CHECK-NOT: [[REG]]
98 ;SI-CHECK: BUFFER_STORE_DWORD [[REG]],
1615 ret void
1716 }
1817
19 ;EG-CHECK-LABEL: @test2:
18 ;FUNC-LABEL: @test2:
2019 ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
2120 ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
2221
23 ;SI-CHECK-LABEL: @test2:
2422 ;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
2523 ;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
2624
3331 ret void
3432 }
3533
36 ;EG-CHECK-LABEL: @test4:
34 ;FUNC-LABEL: @test4:
3735 ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
3836 ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
3937 ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
4038 ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
4139
42 ;SI-CHECK-LABEL: @test4:
4340 ;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
4441 ;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
4542 ;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
5350 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
5451 ret void
5552 }
53
54 ; FUNC-LABEL: @test8
55 ; EG-CHECK: ADD_INT
56 ; EG-CHECK: ADD_INT
57 ; EG-CHECK: ADD_INT
58 ; EG-CHECK: ADD_INT
59 ; EG-CHECK: ADD_INT
60 ; EG-CHECK: ADD_INT
61 ; EG-CHECK: ADD_INT
62 ; EG-CHECK: ADD_INT
63 ; SI-CHECK: S_ADD_I32
64 ; SI-CHECK: S_ADD_I32
65 ; SI-CHECK: S_ADD_I32
66 ; SI-CHECK: S_ADD_I32
67 ; SI-CHECK: S_ADD_I32
68 ; SI-CHECK: S_ADD_I32
69 ; SI-CHECK: S_ADD_I32
70 ; SI-CHECK: S_ADD_I32
71 define void @test8(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b) {
72 entry:
73 %0 = add <8 x i32> %a, %b
74 store <8 x i32> %0, <8 x i32> addrspace(1)* %out
75 ret void
76 }
None ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
1 ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
0 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK --check-prefix=FUNC
1 ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK --check-prefix=FUNC
22
3 ; R600-CHECK: @fadd_f32
3 ; FUNC-LABEL: @fadd_f32
44 ; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W
5 ; SI-CHECK: @fadd_f32
65 ; SI-CHECK: V_ADD_F32
76 define void @fadd_f32(float addrspace(1)* %out, float %a, float %b) {
87 entry:
1110 ret void
1211 }
1312
14 ; R600-CHECK: @fadd_v2f32
13 ; FUNC-LABEL: @fadd_v2f32
1514 ; R600-CHECK-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
1615 ; R600-CHECK-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
17 ; SI-CHECK: @fadd_v2f32
1816 ; SI-CHECK: V_ADD_F32
1917 ; SI-CHECK: V_ADD_F32
2018 define void @fadd_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
2422 ret void
2523 }
2624
27 ; R600-CHECK: @fadd_v4f32
25 ; FUNC-LABEL: @fadd_v4f32
2826 ; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
2927 ; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
3028 ; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
3129 ; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
32 ; SI-CHECK: @fadd_v4f32
3330 ; SI-CHECK: V_ADD_F32
3431 ; SI-CHECK: V_ADD_F32
3532 ; SI-CHECK: V_ADD_F32
4239 store <4 x float> %result, <4 x float> addrspace(1)* %out
4340 ret void
4441 }
42
43 ; FUNC-LABEL: @fadd_v8f32
44 ; R600-CHECK: ADD
45 ; R600-CHECK: ADD
46 ; R600-CHECK: ADD
47 ; R600-CHECK: ADD
48 ; R600-CHECK: ADD
49 ; R600-CHECK: ADD
50 ; R600-CHECK: ADD
51 ; R600-CHECK: ADD
52 ; SI-CHECK: V_ADD_F32
53 ; SI-CHECK: V_ADD_F32
54 ; SI-CHECK: V_ADD_F32
55 ; SI-CHECK: V_ADD_F32
56 ; SI-CHECK: V_ADD_F32
57 ; SI-CHECK: V_ADD_F32
58 ; SI-CHECK: V_ADD_F32
59 ; SI-CHECK: V_ADD_F32
60 define void @fadd_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) {
61 entry:
62 %0 = fadd <8 x float> %a, %b
63 store <8 x float> %0, <8 x float> addrspace(1)* %out
64 ret void
65 }