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[9.0 branch][ARM] VFPv2 only supports 16 D registers. Summary: Patch for 9.0.1. Simplified version of r372186/r372187: fix the meaning of the "vfpv2" and "vfpv2sp" features, but keep around the useless "vfp2d16" and "vfp2d16sp" features, to reduce the risk on the release branch. Fixes https://bugs.llvm.org/show_bug.cgi?id=43365 Reviewers: t.p.northover, tstellar Reviewed By: t.p.northover Subscribers: kristof.beyls, hiraditya, kristina, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68675 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_90@374433 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 1 year, 1 month ago
3 changed file(s) with 34 addition(s) and 18 deletion(s). Raw diff Collapse all Expand all
175175 // exist).
176176
177177 {"+fpregs", "-fpregs", FPUVersion::VFPV2, FPURestriction::SP_D16},
178 {"+vfp2", "-vfp2", FPUVersion::VFPV2, FPURestriction::None},
178 {"+vfp2", "-vfp2", FPUVersion::VFPV2, FPURestriction::D16},
179179 {"+vfp2d16", "-vfp2d16", FPUVersion::VFPV2, FPURestriction::D16},
180180 {"+vfp2d16sp", "-vfp2d16sp", FPUVersion::VFPV2, FPURestriction::SP_D16},
181 {"+vfp2sp", "-vfp2sp", FPUVersion::VFPV2, FPURestriction::None},
181 {"+vfp2sp", "-vfp2sp", FPUVersion::VFPV2, FPURestriction::SP_D16},
182182 {"+vfp3", "-vfp3", FPUVersion::VFPV3, FPURestriction::None},
183183 {"+vfp3d16", "-vfp3d16", FPUVersion::VFPV3, FPURestriction::D16},
184184 {"+vfp3d16sp", "-vfp3d16sp", FPUVersion::VFPV3, FPURestriction::SP_D16},
194194 {"+fp-armv8sp", "-fp-armv8sp", FPUVersion::VFPV5, FPURestriction::None},
195195 {"+fullfp16", "-fullfp16", FPUVersion::VFPV5_FULLFP16, FPURestriction::SP_D16},
196196 {"+fp64", "-fp64", FPUVersion::VFPV2, FPURestriction::D16},
197 {"+d32", "-d32", FPUVersion::VFPV2, FPURestriction::None},
197 {"+d32", "-d32", FPUVersion::VFPV3, FPURestriction::None},
198198 };
199199
200200 for (const auto &Info: FPUFeatureInfoList) {
5656 "Extend FP to 32 double registers">;
5757
5858 multiclass VFPver
59 list prev = [],
60 list otherimplies = []> {
59 list prev,
60 list otherimplies,
61 list vfp2prev = []> {
6162 def _D16_SP: SubtargetFeature<
6263 name#"d16sp", query#"D16SP", "true",
6364 description#" with only 16 d-registers and no double precision",
64 !foreach(v, prev, !cast(v # "_D16_SP")) # otherimplies>;
65 !foreach(v, prev, !cast(v # "_D16_SP")) #
66 !foreach(v, vfp2prev, !cast(v # "_SP")) #
67 otherimplies>;
6568 def _SP: SubtargetFeature<
6669 name#"sp", query#"SP", "true",
6770 description#" with no double precision",
7174 name#"d16", query#"D16", "true",
7275 description#" with only 16 d-registers",
7376 !foreach(v, prev, !cast(v # "_D16")) #
77 vfp2prev #
7478 otherimplies # [FeatureFP64, !cast(NAME # "_D16_SP")]>;
7579 def "": SubtargetFeature<
7680 name, query, "true", description,
7983 !cast(NAME # "_SP")]>;
8084 }
8185
82 defm FeatureVFP2: VFPver<"vfp2", "HasVFPv2", "Enable VFP2 instructions",
83 [], [FeatureFPRegs]>;
86 def FeatureVFP2_D16_SP : SubtargetFeature<"vfp2d16sp", "HasVFPv2D16SP", "true",
87 "Enable VFP2 instructions with "
88 "no double precision",
89 [FeatureFPRegs]>;
90 def FeatureVFP2_SP : SubtargetFeature<"vfp2sp", "HasVFPv2SP", "true",
91 "Enable VFP2 instructions with "
92 "no double precision",
93 [FeatureVFP2_D16_SP]>;
94 def FeatureVFP2_D16 : SubtargetFeature<"vfp2d16", "HasVFPv2D16", "true",
95 "Enable VFP2 instructions",
96 [FeatureFP64, FeatureVFP2_D16_SP]>;
97 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
98 "Enable VFP2 instructions",
99 [FeatureVFP2_D16, FeatureVFP2_SP]>;
84100
85101 defm FeatureVFP3: VFPver<"vfp3", "HasVFPv3", "Enable VFP3 instructions",
86 [FeatureVFP2]>;
102 [], [], [FeatureVFP2]>;
87103
88104 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
89105 "Enable NEON instructions",
97113 [FeatureVFP3], [FeatureFP16]>;
98114
99115 defm FeatureFPARMv8: VFPver<"fp-armv8", "HasFPARMv8", "Enable ARMv8 FP",
100 [FeatureVFP4]>;
116 [FeatureVFP4], []>;
101117
102118 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
103119 "Enable full half-precision "
1212 fldmeax sp!, {s0}
1313
1414 @ CHECK-LABEL: aliases
15 @ CHECK: error: operand must be a list of registers in range [d0, d31]
15 @ CHECK: error: operand must be a list of registers in range [d0, d15]
1616 @ CHECK: fstmeax sp!, {s0}
1717 @ CHECK: ^
18 @ CHECK: error: operand must be a list of registers in range [d0, d31]
18 @ CHECK: error: operand must be a list of registers in range [d0, d15]
1919 @ CHECK: fldmfdx sp!, {s0}
2020 @ CHECK: ^
2121
22 @ CHECK: error: operand must be a list of registers in range [d0, d31]
22 @ CHECK: error: operand must be a list of registers in range [d0, d15]
2323 @ CHECK: fstmfdx sp!, {s0}
2424 @ CHECK: ^
25 @ CHECK: error: operand must be a list of registers in range [d0, d31]
25 @ CHECK: error: operand must be a list of registers in range [d0, d15]
2626 @ CHECK: fldmeax sp!, {s0}
2727 @ CHECK: ^
2828
3030 fstmiaxhs r0, {s0}
3131 fstmiaxls r0, {s0}
3232 fstmiaxvs r0, {s0}
33 @ CHECK: error: operand must be a list of registers in range [d0, d31]
33 @ CHECK: error: operand must be a list of registers in range [d0, d15]
3434 @ CHECK: fstmiaxcs r0, {s0}
3535 @ CHECK: ^
36 @ CHECK: error: operand must be a list of registers in range [d0, d31]
36 @ CHECK: error: operand must be a list of registers in range [d0, d15]
3737 @ CHECK: fstmiaxhs r0, {s0}
3838 @ CHECK: ^
39 @ CHECK: error: operand must be a list of registers in range [d0, d31]
39 @ CHECK: error: operand must be a list of registers in range [d0, d15]
4040 @ CHECK: fstmiaxls r0, {s0}
4141 @ CHECK: ^
42 @ CHECK: error: operand must be a list of registers in range [d0, d31]
42 @ CHECK: error: operand must be a list of registers in range [d0, d15]
4343 @ CHECK: fstmiaxvs r0, {s0}
4444 @ CHECK: ^
4545