llvm.org GIT mirror llvm / 0eff39f
Enable support for returning i1, i8, and i16. Nothing special todo as it's the callee's responsibility to sign or zero-extend the return value. The additional test case just checks to make sure the calls are selected (i.e., -fast-isel-abort doesn't assert). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144047 91177308-0d34-0410-b5e6-96231b3b80d8 Chad Rosier 8 years ago
3 changed file(s) with 24 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
4242 ]>;
4343
4444 def RetCC_ARM_APCS : CallingConv<[
45 CCIfType<[i1, i8, i16], CCPromoteToType>,
4546 CCIfType<[f32], CCBitConvertToType>,
4647
4748 // Handle all vector types as either f64 or v2f64.
105106 ]>;
106107
107108 def RetCC_ARM_AAPCS_Common : CallingConv<[
109 CCIfType<[i1, i8, i16], CCPromoteToType>,
108110 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
109111 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
110112 ]>;
16961696 } else {
16971697 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
16981698 EVT CopyVT = RVLocs[0].getValVT();
1699
1700 // Special handling for extended integers.
1701 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1702 CopyVT = MVT::i32;
1703
16991704 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
17001705
17011706 unsigned ResultReg = createResultReg(DstRC);
19121917 MVT RetVT;
19131918 if (RetTy->isVoidTy())
19141919 RetVT = MVT::isVoid;
1915 else if (!isTypeLegal(RetTy, RetVT))
1920 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
1921 RetVT != MVT::i8 && RetVT != MVT::i1)
19161922 return false;
19171923
19181924 // TODO: For now if we have long calls specified we don't handle the call.
6464 %7 = call i32 @t4(i16 zeroext 65535)
6565 ret void
6666 }
67
68 define void @foo2() nounwind {
69 %1 = call signext i16 @t5()
70 %2 = call zeroext i16 @t6()
71 %3 = call signext i8 @t7()
72 %4 = call zeroext i8 @t8()
73 %5 = call zeroext i1 @t9()
74 ret void
75 }
76
77 declare signext i16 @t5();
78 declare zeroext i16 @t6();
79 declare signext i8 @t7();
80 declare zeroext i8 @t8();
81 declare zeroext i1 @t9();