llvm.org GIT mirror llvm / 0ef9972
[PowerPC] Remove zexts after byte-swapping loads lhbrx and lwbrx not only load their data with byte swapping, but also clear the upper 32 bits (at least). As a result, they can be added to the PPCISelDAGToDAG peephole optimization as frontier instructions for the removal of unnecessary zero extensions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225189 91177308-0d34-0410-b5e6-96231b3b80d8 Hal Finkel 5 years ago
3 changed file(s) with 46 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
37283728 return true;
37293729 }
37303730
3731 // LHBRX and LWBRX always clear the higher-order bits.
3732 if (Op32.getMachineOpcode() == PPC::LHBRX ||
3733 Op32.getMachineOpcode() == PPC::LWBRX) {
3734 ToPromote.insert(Op32.getNode());
3735 return true;
3736 }
3737
37313738 // Next, check for those instructions we can look through.
37323739
37333740 // Assuming the mask does not wrap around, then the higher-order bits are
39153922 case PPC::SRW: NewOpcode = PPC::SRW8; break;
39163923 case PPC::LI: NewOpcode = PPC::LI8; break;
39173924 case PPC::LIS: NewOpcode = PPC::LIS8; break;
3925 case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break;
3926 case PPC::LWBRX: NewOpcode = PPC::LWBRX8; break;
39183927 case PPC::RLWIMI: NewOpcode = PPC::RLWIMI8; break;
39193928 case PPC::OR: NewOpcode = PPC::OR8; break;
39203929 case PPC::SELECT_I4: NewOpcode = PPC::SELECT_I8; break;
841841 def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src),
842842 "ldbrx $rD, $src", IIC_LdStLoad,
843843 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
844
845 let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in {
846 def LHBRX8 : XForm_1<31, 790, (outs g8rc:$rD), (ins memrr:$src),
847 "lhbrx $rD, $src", IIC_LdStLoad, []>;
848 def LWBRX8 : XForm_1<31, 534, (outs g8rc:$rD), (ins memrr:$src),
849 "lwbrx $rD, $src", IIC_LdStLoad, []>;
850 }
844851
845852 let mayLoad = 1, hasSideEffects = 0 in {
846853 def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
3838 ; CHECK: blr
3939 }
4040
41 ; Function Attrs: nounwind readnone
42 declare i32 @llvm.bswap.i32(i32) #1
43
44 ; Function Attrs: nounwind readonly
45 define zeroext i32 @bs32(i32* nocapture readonly %x) #0 {
46 entry:
47 %0 = load i32* %x, align 4
48 %1 = tail call i32 @llvm.bswap.i32(i32 %0)
49 ret i32 %1
50
51 ; CHECK-LABEL: @bs32
52 ; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32
53 ; CHECK: blr
54 }
55
56 ; Function Attrs: nounwind readonly
57 define zeroext i16 @bs16(i16* nocapture readonly %x) #0 {
58 entry:
59 %0 = load i16* %x, align 2
60 %1 = tail call i16 @llvm.bswap.i16(i16 %0)
61 ret i16 %1
62
63 ; CHECK-LABEL: @bs16
64 ; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32
65 ; CHECK: blr
66 }
67
68 ; Function Attrs: nounwind readnone
69 declare i16 @llvm.bswap.i16(i16) #1
70
4171 attributes #0 = { nounwind readnone }
4272