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The attached patches implement most of the ARM AAPCS-VFP hard float ABI. The missing piece is support for putting "homogeneous aggregates" into registers. Patch by Sandeep Patel! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73095 91177308-0d34-0410-b5e6-96231b3b80d8 Anton Korobeynikov 11 years ago
9 changed file(s) with 128 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
7777 };
7878 }
7979
80 namespace FloatABI {
81 enum ABIType {
82 Default,
83 Soft,
84 Hard
85 };
86 }
87
8088 //===----------------------------------------------------------------------===//
8189 ///
8290 /// TargetMachine - Primary interface to the complete machine description for
8795 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
8896 void operator=(const TargetMachine &); // DO NOT IMPLEMENT
8997 protected: // Can only create subclasses.
90 TargetMachine() : AsmInfo(0) { }
98 TargetMachine();
9199
92100 /// getSubtargetImpl - virtual method implemented by subclasses that returns
93101 /// a reference to that target's TargetSubtarget-derived member variable.
7272 /// target FP instructions.
7373 extern bool UseSoftFloat;
7474
75 /// FloatABIType - This setting is set by -float-abi=xxx option is specfied
76 /// on the command line. This setting may either be Default, Soft, or Hard.
77 /// Default selects the target's default behavior. Soft selects the ABI for
78 /// UseSoftFloat, but does not inidcate that FP hardware may not be used.
79 /// Such a combination is unfortunately popular (e.g. arm-apple-darwin).
80 /// Hard presumes that the normal FP ABI is used.
81 extern FloatABI::ABIType FloatABIType;
82
7583 /// NoZerosInBSS - By default some codegens place zero-initialized data to
7684 /// .bss section. This flag disables such behaviour (necessary, e.g. for
7785 /// crt*.o compiling).
1515 /// CCIfAlign - Match of the original alignment of the arg
1616 class CCIfAlign:
1717 CCIf;
18
19 /// CCIfFloatABI - Match of the float ABI and the arg. ABIType may be "Hard" or
20 /// "Soft".
21 class CCIfFloatABI:
22 CCIf;
1823
1924 //===----------------------------------------------------------------------===//
2025 // ARM APCS Calling Convention
4247 ]>;
4348
4449 //===----------------------------------------------------------------------===//
45 // ARM AAPCS (EABI) Calling Convention
50 // ARM AAPCS (EABI) Calling Convention, common parts
4651 //===----------------------------------------------------------------------===//
47 def CC_ARM_AAPCS : CallingConv<[
52
53 def CC_ARM_AAPCS_Common : CallingConv<[
4854
4955 CCIfType<[i8, i16], CCPromoteToType>,
5056
5258 // i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register
5359 // (and the same is true for f64 if VFP is not enabled)
5460 CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>,
55 CCIfType<[f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>,
56
57 CCIfType<[f32], CCBitConvertToType>,
5861 CCIfType<[i32], CCIf<"State.getNextStackOffset() == 0 &&"
5962 "ArgFlags.getOrigAlign() != 8",
6063 CCAssignToReg<[R0, R1, R2, R3]>>>,
6164
62 CCIfType<[i32], CCAssignToStack<4, 4>>,
65 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
6366 CCIfType<[f64], CCAssignToStack<8, 8>>
6467 ]>;
6568
69 def RetCC_ARM_AAPCS_Common : CallingConv<[
70 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>
71 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
72 ]>;
73
74 //===----------------------------------------------------------------------===//
75 // ARM AAPCS (EABI) Calling Convention
76 //===----------------------------------------------------------------------===//
77
78 def CC_ARM_AAPCS : CallingConv<[
79 CCIfType<[f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>,
80 CCIfType<[f32], CCBitConvertToType>,
81 CCDelegateTo
82 ]>;
83
6684 def RetCC_ARM_AAPCS : CallingConv<[
85 CCIfType<[f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>,
6786 CCIfType<[f32], CCBitConvertToType>,
68 CCIfType<[f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>,
87 CCDelegateTo
88 ]>;
6989
70 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
71 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
90 //===----------------------------------------------------------------------===//
91 // ARM AAPCS-VFP (EABI) Calling Convention
92 //===----------------------------------------------------------------------===//
93
94 def CC_ARM_AAPCS_VFP : CallingConv<[
95 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
96 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
97 S9, S10, S11, S12, S13, S14, S15]>>,
98 CCDelegateTo
99 ]>;
100
101 def RetCC_ARM_AAPCS_VFP : CallingConv<[
102 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
103 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
104 S9, S10, S11, S12, S13, S14, S15]>>,
105 CCDelegateTo
72106 ]>;
73107
74108 //===----------------------------------------------------------------------===//
76110 //===----------------------------------------------------------------------===//
77111
78112 def CC_ARM : CallingConv<[
113 CCIfSubtarget<"isAAPCS_ABI()",
114 CCIfSubtarget<"hasVFP2()",
115 CCIfFloatABI<"Hard",
116 CCDelegateTo>>>,
79117 CCIfSubtarget<"isAAPCS_ABI()", CCDelegateTo>,
80118 CCDelegateTo
81119 ]>;
82120
83121 def RetCC_ARM : CallingConv<[
122 CCIfSubtarget<"isAAPCS_ABI()",
123 CCIfSubtarget<"hasVFP2()",
124 CCIfFloatABI<"Hard",
125 CCDelegateTo>>>,
84126 CCIfSubtarget<"isAAPCS_ABI()", CCDelegateTo>,
85127 CCDelegateTo
86128 ]>;
548548 switch (N->getOpcode()) {
549549 default: break;
550550 case ISD::Constant: {
551 // ARMv6T2 and later should materialize imms via MOV / MOVT pair.
552 if (Subtarget->hasV6T2Ops())
553 break;
554
551555 unsigned Val = cast(N)->getZExtValue();
552556 bool UseCP = true;
553557 if (Subtarget->isThumb())
558562 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
559563 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
560564 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
565
561566 if (UseCP) {
562567 SDValue CPIdx =
563568 CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
569574 CPIdx, CurDAG->getEntryNode());
570575 else {
571576 SDValue Ops[] = {
572 CPIdx,
577 CPIdx,
573578 CurDAG->getRegister(0, MVT::i32),
574579 CurDAG->getTargetConstant(0, MVT::i32),
575580 getAL(CurDAG),
582587 ReplaceUses(Op, SDValue(ResNode, 0));
583588 return NULL;
584589 }
585
590
586591 // Other cases are autogenerated.
587592 break;
588593 }
11001100 else
11011101 RC = ARM::GPRRegisterClass;
11021102
1103 if (RegVT == MVT::f64) {
1103 if (FloatABIType == FloatABI::Hard) {
1104 if (RegVT == MVT::f32)
1105 RC = ARM::SPRRegisterClass;
1106 else if (RegVT == MVT::f64)
1107 RC = ARM::DPRRegisterClass;
1108 } else if (RegVT == MVT::f64) {
11041109 // f64 is passed in pairs of GPRs and must be combined.
11051110 RegVT = MVT::i32;
11061111 } else if (!((RegVT == MVT::i32) || (RegVT == MVT::f32)))
218218
219219 // Condition code registers.
220220 def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;
221
222 //===----------------------------------------------------------------------===//
223 // Subregister Set Definitions... now that we have all of the pieces, define the
224 // sub registers for each register.
225 //
226
227 def : SubRegSet<1, [D0, D1, D2, D3, D4, D5, D6, D7,
228 D8, D9, D10, D11, D12, D13, D14, D15],
229 [S0, S2, S4, S6, S8, S10, S12, S14,
230 S16, S18, S20, S22, S24, S26, S28, S30]>;
231
232 def : SubRegSet<2, [D0, D1, D2, D3, D4, D5, D6, D7,
233 D8, D9, D10, D11, D12, D13, D14, D15],
234 [S1, S3, S5, S7, S9, S11, S13, S15,
235 S17, S19, S21, S23, S25, S27, S29, S31]>;
1313 #include "ARMSubtarget.h"
1414 #include "ARMGenSubtarget.inc"
1515 #include "llvm/Module.h"
16 #include "llvm/Target/TargetMachine.h"
17 #include "llvm/Target/TargetOptions.h"
1618 using namespace llvm;
1719
1820 ARMSubtarget::ARMSubtarget(const Module &M, const std::string &FS,
2729 , CPUString("generic")
2830 , TargetType(isELF) // Default to ELF unless otherwise specified.
2931 , TargetABI(ARM_ABI_APCS) {
32 // default to soft float ABI
33 if (FloatABIType == FloatABI::Default)
34 FloatABIType = FloatABI::Soft;
35
3036 // Determine default and user specified characteristics
3137
3238 // Parse features string.
2929 bool FiniteOnlyFPMathOption;
3030 bool HonorSignDependentRoundingFPMathOption;
3131 bool UseSoftFloat;
32 FloatABI::ABIType FloatABIType;
3233 bool NoImplicitFloat;
3334 bool NoZerosInBSS;
3435 bool ExceptionHandling;
8384 cl::desc("Generate software floating point library calls"),
8485 cl::location(UseSoftFloat),
8586 cl::init(false));
87 static cl::opt
88 FloatABIForCalls("float-abi",
89 cl::desc("Choose float ABI type"),
90 cl::location(FloatABIType),
91 cl::init(FloatABI::Default),
92 cl::values(
93 clEnumValN(FloatABI::Default, "default",
94 "Target default float ABI type"),
95 clEnumValN(FloatABI::Soft, "soft",
96 "Soft float ABI (implied by -soft-float)"),
97 clEnumValN(FloatABI::Hard, "hard",
98 "Hard float ABI (uses FP registers)"),
99 clEnumValEnd));
86100 static cl::opt
87101 DontPlaceZerosInBSS("nozero-initialized-in-bss",
88102 cl::desc("Don't place zero-initialized symbols into bss section"),
161175 // TargetMachine Class
162176 //
163177
178 TargetMachine::TargetMachine()
179 : AsmInfo(0) {
180 // Typically it will be subtargets that will adjust FloatABIType from Default
181 // to Soft or Hard.
182 if (UseSoftFloat)
183 FloatABIType = FloatABI::Soft;
184 }
185
164186 TargetMachine::~TargetMachine() {
165187 delete AsmInfo;
166188 }
349349 , MaxInlineSizeThreshold(128)
350350 , Is64Bit(is64Bit)
351351 , TargetType(isELF) { // Default to ELF unless otherwise specified.
352
353 // default to hard float ABI
354 if (FloatABIType == FloatABI::Default)
355 FloatABIType = FloatABI::Hard;
352356
353357 // Determine default and user specified characteristics
354358 if (!FS.empty()) {