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X86 Peephole: fold loads to the source register operand if possible. Machine CSE and other optimizations can remove instructions so folding is possible at peephole while not possible at ISel. rdar://10554090 and rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160919 91177308-0d34-0410-b5e6-96231b3b80d8 Manman Ren 7 years ago
10 changed file(s) with 167 addition(s) and 50 deletion(s). Raw diff Collapse all Expand all
1313 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
1414 #define LLVM_TARGET_TARGETINSTRINFO_H
1515
16 #include "llvm/ADT/SmallSet.h"
1617 #include "llvm/MC/MCInstrInfo.h"
1718 #include "llvm/CodeGen/DFAPacketizer.h"
1819 #include "llvm/CodeGen/MachineFunction.h"
690691 int Mask, int Value,
691692 const MachineRegisterInfo *MRI) const {
692693 return false;
694 }
695
696 /// optimizeLoadInstr - Try to remove the load by folding it to a register
697 /// operand at the use. We fold the load instructions if and only if the
698 /// def and use are in the same BB.
699 virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI,
700 const MachineRegisterInfo *MRI,
701 SmallSet &FoldAsLoadDefRegs,
702 MachineInstr *&DefMI) const {
703 return 0;
693704 }
694705
695706 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
7777 STATISTIC(NumBitcasts, "Number of bitcasts eliminated");
7878 STATISTIC(NumCmps, "Number of compares eliminated");
7979 STATISTIC(NumImmFold, "Number of move immediate folded");
80 STATISTIC(NumLoadFold, "Number of loads folded");
8081
8182 namespace {
8283 class PeepholeOptimizer : public MachineFunctionPass {
440441 SmallPtrSet LocalMIs;
441442 SmallSet ImmDefRegs;
442443 DenseMap ImmDefMIs;
444 SmallSet FoldAsLoadDefRegs;
443445 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
444446 MachineBasicBlock *MBB = &*I;
445447
447449 LocalMIs.clear();
448450 ImmDefRegs.clear();
449451 ImmDefMIs.clear();
452 FoldAsLoadDefRegs.clear();
450453
451454 bool First = true;
452455 MachineBasicBlock::iterator PMII;
488491 Changed |= foldImmediate(MI, MBB, ImmDefRegs, ImmDefMIs);
489492 }
490493
494 MachineInstr *DefMI = 0;
495 MachineInstr *FoldMI = TII->optimizeLoadInstr(MI, MRI, FoldAsLoadDefRegs,
496 DefMI);
497 if (FoldMI) {
498 // Update LocalMIs since we replaced MI with FoldMI and deleted DefMI.
499 LocalMIs.erase(MI);
500 LocalMIs.erase(DefMI);
501 LocalMIs.insert(FoldMI);
502 MI->eraseFromParent();
503 DefMI->eraseFromParent();
504 ++NumLoadFold;
505
506 // MI is replaced with FoldMI.
507 Changed = true;
508 PMII = FoldMI;
509 MII = llvm::next(PMII);
510 continue;
511 }
512
491513 First = false;
492514 PMII = MII;
493515 ++MII;
33223322 return true;
33233323 }
33243324
3325 /// optimizeLoadInstr - Try to remove the load by folding it to a register
3326 /// operand at the use. We fold the load instructions if and only if the
3327 /// def and use are in the same BB.
3328 MachineInstr* X86InstrInfo::
3329 optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI,
3330 SmallSet &FoldAsLoadDefRegs,
3331 MachineInstr *&DefMI) const {
3332 if (MI->mayStore() || MI->isCall())
3333 // To be conservative, we don't fold the loads if there is a store in
3334 // between.
3335 FoldAsLoadDefRegs.clear();
3336 // We only fold loads to a virtual register.
3337 if (MI->canFoldAsLoad()) {
3338 const MCInstrDesc &MCID = MI->getDesc();
3339 if (MCID.getNumDefs() == 1) {
3340 unsigned Reg = MI->getOperand(0).getReg();
3341 // To reduce compilation time, we check MRI->hasOneUse when inserting
3342 // loads. It should be checked when processing uses of the load, since
3343 // uses can be removed during peephole.
3344 if (TargetRegisterInfo::isVirtualRegister(Reg) && MRI->hasOneUse(Reg)) {
3345 FoldAsLoadDefRegs.insert(Reg);
3346 return 0;
3347 }
3348 }
3349 }
3350
3351 // Collect information about virtual register operands of MI.
3352 DenseMap SrcVirtualRegToOp;
3353 SmallSet DstVirtualRegs;
3354 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
3355 MachineOperand &MO = MI->getOperand(i);
3356 if (!MO.isReg())
3357 continue;
3358 unsigned Reg = MO.getReg();
3359 if (!TargetRegisterInfo::isVirtualRegister(Reg))
3360 continue;
3361 if (MO.isDef())
3362 DstVirtualRegs.insert(Reg);
3363 else if (FoldAsLoadDefRegs.count(Reg)) {
3364 // Only handle the case where Reg is used in a single src operand.
3365 if (SrcVirtualRegToOp.find(Reg) != SrcVirtualRegToOp.end())
3366 SrcVirtualRegToOp.erase(Reg);
3367 else
3368 SrcVirtualRegToOp.insert(std::make_pair(Reg, i));
3369 }
3370 }
3371
3372 for (DenseMap::iterator SI = SrcVirtualRegToOp.begin(),
3373 SE = SrcVirtualRegToOp.end(); SI != SE; SI++) {
3374 // If the virtual register is updated by MI, we can't fold the load.
3375 if (DstVirtualRegs.count(SI->first)) continue;
3376
3377 // Check whether we can fold the def into this operand.
3378 DefMI = MRI->getVRegDef(SI->first);
3379 assert(DefMI);
3380 bool SawStore = false;
3381 if (!DefMI->isSafeToMove(this, 0, SawStore))
3382 continue;
3383
3384 SmallVector Ops;
3385 Ops.push_back(SI->second);
3386 MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI);
3387 if (!FoldMI) continue;
3388 FoldAsLoadDefRegs.erase(SI->first);
3389 return FoldMI;
3390 }
3391 return 0;
3392 }
3393
33253394 /// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
33263395 /// instruction with two undef reads of the register being defined. This is
33273396 /// used for mapping:
386386 unsigned SrcReg2, int CmpMask, int CmpValue,
387387 const MachineRegisterInfo *MRI) const;
388388
389 /// optimizeLoadInstr - Try to remove the load by folding it to a register
390 /// operand at the use. We fold the load instructions if and only if the
391 /// def and use are in the same BB.
392 virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI,
393 const MachineRegisterInfo *MRI,
394 SmallSet &FoldAsLoadDefRegs,
395 MachineInstr *&DefMI) const;
396
389397 private:
390398 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
391399 MachineFunction::iterator &MFI,
22 define void @double_save(<4 x i32>* %Ap, <4 x i32>* %Bp, <8 x i32>* %P) nounwind ssp {
33 entry:
44 ; CHECK: vmovaps
5 ; CHECK: vmovaps
6 ; CHECK: vinsertf128
5 ; CHECK: vinsertf128 $1, ([[A0:%rdi|%rsi]]),
76 ; CHECK: vmovups
87 %A = load <4 x i32>* %Ap
98 %B = load <4 x i32>* %Bp
3333 define double @squirt(double* %x) nounwind {
3434 entry:
3535 ; CHECK: squirt:
36 ; CHECK: movsd ([[A0]]), %xmm0
37 ; CHECK: sqrtsd %xmm0, %xmm0
36 ; CHECK: sqrtsd ([[A0]]), %xmm0
3837 %z = load double* %x
3938 %t = call double @llvm.sqrt.f64(double %z)
4039 ret double %t
4444
4545 }
4646
47 ; rdar://10554090
48 ; xor in exit block will be CSE'ed and load will be folded to xor in entry.
49 define i1 @test3(i32* %P, i32* %Q) nounwind {
50 ; CHECK: test3:
51 ; CHECK: movl 8(%esp), %eax
52 ; CHECK: xorl (%eax),
53 ; CHECK: j
54 ; CHECK-NOT: xor
55 entry:
56 %0 = load i32* %P, align 4
57 %1 = load i32* %Q, align 4
58 %2 = xor i32 %0, %1
59 %3 = and i32 %2, 65535
60 %4 = icmp eq i32 %3, 0
61 br i1 %4, label %exit, label %land.end
62
63 exit:
64 %shr.i.i19 = xor i32 %1, %0
65 %5 = and i32 %shr.i.i19, 2147418112
66 %6 = icmp eq i32 %5, 0
67 br label %land.end
68
69 land.end:
70 %7 = phi i1 [ %6, %exit ], [ false, %entry ]
71 ret i1 %7
72 }
None ; RUN: llc < %s -march=x86 -mattr=+sse2 > %t
1 ; RUN: grep pcmpeqd %t | count 1
2 ; RUN: grep xor %t | count 1
3 ; RUN: not grep LCP %t
0 ; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
41
52 define <2 x double> @foo() nounwind {
63 ret <2 x double> bitcast (<2 x i64> to <2 x double>)
4 ; CHECK: foo:
5 ; CHECK: pcmpeqd %xmm{{[0-9]+}}, %xmm{{[0-9]+}}
6 ; CHECK-NEXT: ret
77 }
88 define <2 x double> @bar() nounwind {
99 ret <2 x double> bitcast (<2 x i64> to <2 x double>)
10 ; CHECK: bar:
11 ; CHECK: xorps %xmm{{[0-9]+}}, %xmm{{[0-9]+}}
12 ; CHECK-NEXT: ret
1013 }
136136 }
137137
138138 ; CHECK: ogt_x:
139 ; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1
140 ; CHECK-NEXT: maxsd %xmm1, %xmm0
139 ; CHECK-NEXT: maxsd LCP{{.*}}(%rip), %xmm0
141140 ; CHECK-NEXT: ret
142141 ; UNSAFE: ogt_x:
143 ; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
144 ; UNSAFE-NEXT: maxsd %xmm1, %xmm0
142 ; UNSAFE-NEXT: maxsd LCP{{.*}}(%rip), %xmm0
145143 ; UNSAFE-NEXT: ret
146144 ; FINITE: ogt_x:
147 ; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
148 ; FINITE-NEXT: maxsd %xmm1, %xmm0
145 ; FINITE-NEXT: maxsd LCP{{.*}}(%rip), %xmm0
149146 ; FINITE-NEXT: ret
150147 define double @ogt_x(double %x) nounwind {
151148 %c = fcmp ogt double %x, 0.000000e+00
154151 }
155152
156153 ; CHECK: olt_x:
157 ; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1
158 ; CHECK-NEXT: minsd %xmm1, %xmm0
154 ; CHECK-NEXT: minsd LCP{{.*}}(%rip), %xmm0
159155 ; CHECK-NEXT: ret
160156 ; UNSAFE: olt_x:
161 ; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
162 ; UNSAFE-NEXT: minsd %xmm1, %xmm0
157 ; UNSAFE-NEXT: minsd LCP{{.*}}(%rip), %xmm0
163158 ; UNSAFE-NEXT: ret
164159 ; FINITE: olt_x:
165 ; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
166 ; FINITE-NEXT: minsd %xmm1, %xmm0
160 ; FINITE-NEXT: minsd LCP{{.*}}(%rip), %xmm0
167161 ; FINITE-NEXT: ret
168162 define double @olt_x(double %x) nounwind {
169163 %c = fcmp olt double %x, 0.000000e+00
216210 ; CHECK: oge_x:
217211 ; CHECK: ucomisd %xmm1, %xmm0
218212 ; UNSAFE: oge_x:
219 ; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
220 ; UNSAFE-NEXT: maxsd %xmm1, %xmm0
213 ; UNSAFE-NEXT: maxsd LCP{{.*}}(%rip), %xmm0
221214 ; UNSAFE-NEXT: ret
222215 ; FINITE: oge_x:
223 ; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
224 ; FINITE-NEXT: maxsd %xmm1, %xmm0
216 ; FINITE-NEXT: maxsd LCP{{.*}}(%rip), %xmm0
225217 ; FINITE-NEXT: ret
226218 define double @oge_x(double %x) nounwind {
227219 %c = fcmp oge double %x, 0.000000e+00
232224 ; CHECK: ole_x:
233225 ; CHECK: ucomisd %xmm0, %xmm1
234226 ; UNSAFE: ole_x:
235 ; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
236 ; UNSAFE-NEXT: minsd %xmm1, %xmm0
227 ; UNSAFE-NEXT: minsd LCP{{.*}}(%rip), %xmm0
237228 ; UNSAFE-NEXT: ret
238229 ; FINITE: ole_x:
239 ; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
240 ; FINITE-NEXT: minsd %xmm1, %xmm0
230 ; FINITE-NEXT: minsd LCP{{.*}}(%rip), %xmm0
241231 ; FINITE-NEXT: ret
242232 define double @ole_x(double %x) nounwind {
243233 %c = fcmp ole double %x, 0.000000e+00
410400 ; CHECK: ugt_x:
411401 ; CHECK: ucomisd %xmm0, %xmm1
412402 ; UNSAFE: ugt_x:
413 ; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
414 ; UNSAFE-NEXT: maxsd %xmm1, %xmm0
403 ; UNSAFE-NEXT: maxsd LCP{{.*}}(%rip), %xmm0
415404 ; UNSAFE-NEXT: ret
416405 ; FINITE: ugt_x:
417 ; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
418 ; FINITE-NEXT: maxsd %xmm1, %xmm0
406 ; FINITE-NEXT: maxsd LCP{{.*}}(%rip), %xmm0
419407 ; FINITE-NEXT: ret
420408 define double @ugt_x(double %x) nounwind {
421409 %c = fcmp ugt double %x, 0.000000e+00
426414 ; CHECK: ult_x:
427415 ; CHECK: ucomisd %xmm1, %xmm0
428416 ; UNSAFE: ult_x:
429 ; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
430 ; UNSAFE-NEXT: minsd %xmm1, %xmm0
417 ; UNSAFE-NEXT: minsd LCP{{.*}}(%rip), %xmm0
431418 ; UNSAFE-NEXT: ret
432419 ; FINITE: ult_x:
433 ; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
434 ; FINITE-NEXT: minsd %xmm1, %xmm0
420 ; FINITE-NEXT: minsd LCP{{.*}}(%rip), %xmm0
435421 ; FINITE-NEXT: ret
436422 define double @ult_x(double %x) nounwind {
437423 %c = fcmp ult double %x, 0.000000e+00
481467 ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
482468 ; CHECK-NEXT: ret
483469 ; UNSAFE: uge_x:
484 ; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
485 ; UNSAFE-NEXT: maxsd %xmm1, %xmm0
470 ; UNSAFE-NEXT: maxsd LCP{{.*}}(%rip), %xmm0
486471 ; UNSAFE-NEXT: ret
487472 ; FINITE: uge_x:
488 ; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
489 ; FINITE-NEXT: maxsd %xmm1, %xmm0
473 ; FINITE-NEXT: maxsd LCP{{.*}}(%rip), %xmm0
490474 ; FINITE-NEXT: ret
491475 define double @uge_x(double %x) nounwind {
492476 %c = fcmp uge double %x, 0.000000e+00
500484 ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
501485 ; CHECK-NEXT: ret
502486 ; UNSAFE: ule_x:
503 ; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
504 ; UNSAFE-NEXT: minsd %xmm1, %xmm0
487 ; UNSAFE-NEXT: minsd LCP{{.*}}(%rip), %xmm0
505488 ; UNSAFE-NEXT: ret
506489 ; FINITE: ule_x:
507 ; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
508 ; FINITE-NEXT: minsd %xmm1, %xmm0
490 ; FINITE-NEXT: minsd LCP{{.*}}(%rip), %xmm0
509491 ; FINITE-NEXT: ret
510492 define double @ule_x(double %x) nounwind {
511493 %c = fcmp ule double %x, 0.000000e+00
514496 }
515497
516498 ; CHECK: uge_inverse_x:
517 ; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1
518 ; CHECK-NEXT: minsd %xmm1, %xmm0
499 ; CHECK-NEXT: minsd LCP{{.*}}(%rip), %xmm0
519500 ; CHECK-NEXT: ret
520501 ; UNSAFE: uge_inverse_x:
521502 ; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
534515 }
535516
536517 ; CHECK: ule_inverse_x:
537 ; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1
538 ; CHECK-NEXT: maxsd %xmm1, %xmm0
518 ; CHECK-NEXT: maxsd LCP{{.*}}(%rip), %xmm0
539519 ; CHECK-NEXT: ret
540520 ; UNSAFE: ule_inverse_x:
541521 ; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
1313 define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind {
1414 ; CHECK: test2:
1515 ; CHECK: pcmp
16 ; CHECK: pcmp
17 ; CHECK: pxor
16 ; CHECK: pxor LCP
17 ; CHECK: movdqa
1818 ; CHECK: ret
1919 %C = icmp sge <4 x i32> %A, %B
2020 %D = sext <4 x i1> %C to <4 x i32>