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[ARM] Thumb1 3 to 2 operand convertion for commutative operations Differential Revision: http://reviews.llvm.org/D11057 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241802 91177308-0d34-0410-b5e6-96231b3b80d8 Scott Douglass 5 years ago
3 changed file(s) with 40 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
55035503 // then transform to 2 operand version of the same instruction
55045504 // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1'
55055505 bool Transform = Op3.getReg() == Op4.getReg();
5506
5507 // For communtative operations, we might be able to transform if we swap
5508 // Op4 and Op5. The 'ADD Rdm, SP, Rdm' form is already handled specially
5509 // as tADDrsp.
5510 const ARMOperand *LastOp = &Op5;
5511 bool Swap = false;
5512 if (!Transform && Op5.isReg() && Op3.getReg() == Op5.getReg() &&
5513 ((Mnemonic == "add" && Op4.getReg() != ARM::SP) ||
5514 Mnemonic == "and" || Mnemonic == "eor" ||
5515 Mnemonic == "adc" || Mnemonic == "orr")) {
5516 Swap = true;
5517 LastOp = &Op4;
5518 Transform = true;
5519 }
5520
55065521 // If both registers are the same then remove one of them from
55075522 // the operand list, with certain exceptions.
55085523 if (Transform) {
55095524 // Don't transform 'adds Rd, Rd, Rm' or 'sub{s} Rd, Rd, Rm' because the
55105525 // 2 operand forms don't exist.
55115526 if (((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub") &&
5512 Op5.isReg())
5527 LastOp->isReg())
55135528 Transform = false;
55145529
55155530 // Don't transform 'add/sub{s} Rd, Rd, #imm' if the immediate fits into
55165531 // 3-bits because the ARMARM says not to.
5517 if ((Mnemonic == "add" || Mnemonic == "sub") && Op5.isImm0_7())
5532 if ((Mnemonic == "add" || Mnemonic == "sub") && LastOp->isImm0_7())
55185533 Transform = false;
55195534 }
55205535
5521 if (Transform)
5536 if (Transform) {
5537 if (Swap)
5538 std::swap(Op4, Op5);
55225539 Operands.erase(Operands.begin() + 3);
5540 }
55235541 }
55245542
55255543 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
6666 // CHECK: add r3, r1 @ encoding: [0x0b,0x44]
6767 ADD r4, r4, pc // T2
6868 // CHECK: add r4, pc @ encoding: [0x7c,0x44]
69 ADD r4, pc, r4 // T2
70 // CHECK: add r4, pc @ encoding: [0x7c,0x44]
6971 ADD pc, pc, r2 // T2
72 // CHECK: add pc, r2 @ encoding: [0x97,0x44]
73 ADD pc, r2, pc // T2
7074 // CHECK: add pc, r2 @ encoding: [0x97,0x44]
7175
7276 // ADD (SP plus immediate) A8.8.9
1313
1414 add r0, r0, r8
1515 @ CHECK: add r0, r8 @ encoding: [0x40,0x44]
16
17 add r1, r8, r1
18 @ CHECK: add r1, r8 @ encoding: [0x41,0x44]
1619
1720 add sp, sp, r0
1821 @ CHECK: add sp, r0 @ encoding: [0x85,0x44]
5154 sub sp, sp, #16
5255 @ CHECK: sub sp, #16 @ encoding: [0x84,0xb0]
5356
57 ands r0, r1, r0
58 @ CHECK: ands r0, r1 @ encoding: [0x08,0x40]
59
5460 ands r0, r0, r1
5561 @ CHECK: ands r0, r1 @ encoding: [0x08,0x40]
5662
5763 eors r0, r0, r1
64 @ CHECK: eors r0, r1 @ encoding: [0x48,0x40]
65
66 eors r0, r1, r0
5867 @ CHECK: eors r0, r1 @ encoding: [0x48,0x40]
5968
6069 lsls r0, r0, r1
6978 adcs r0, r0, r1
7079 @ CHECK: adcs r0, r1 @ encoding: [0x48,0x41]
7180
81 adcs r0, r1, r0
82 @ CHECK: adcs r0, r1 @ encoding: [0x48,0x41]
83
7284 sbcs r0, r0, r1
7385 @ CHECK: sbcs r0, r1 @ encoding: [0x88,0x41]
7486
7890 orrs r0, r0, r1
7991 @ CHECK: orrs r0, r1 @ encoding: [0x08,0x43]
8092
93 orrs r0, r1, r0
94 @ CHECK: orrs r0, r1 @ encoding: [0x08,0x43]
95
8196 bics r0, r0, r1
8297 @ CHECK: bics r0, r1 @ encoding: [0x88,0x43]