llvm.org GIT mirror llvm / 0e6a052
Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 8 years ago
70 changed file(s) with 650 addition(s) and 609 deletion(s). Raw diff Collapse all Expand all
169169
170170 MachineModuleInfo(); // DUMMY CONSTRUCTOR, DO NOT CALL.
171171 // Real constructor.
172 MachineModuleInfo(const MCAsmInfo &MAI, const TargetAsmInfo *TAI);
172 MachineModuleInfo(const MCAsmInfo &MAI, const MCRegisterInfo &MRI,
173 const TargetAsmInfo *TAI);
173174 ~MachineModuleInfo();
174175
175176 bool doInitialization();
2525 class MCLabel;
2626 class MCDwarfFile;
2727 class MCDwarfLoc;
28 class MCRegisterInfo;
2829 class MCLineSection;
2930 class StringRef;
3031 class Twine;
4445
4546 /// The MCAsmInfo for this target.
4647 const MCAsmInfo &MAI;
48
49 /// The MCRegisterInfo for this target.
50 const MCRegisterInfo &MRI;
4751
4852 const TargetAsmInfo *TAI;
4953
109113 MCSymbol *CreateSymbol(StringRef Name);
110114
111115 public:
112 explicit MCContext(const MCAsmInfo &MAI, const TargetAsmInfo *TAI);
116 explicit MCContext(const MCAsmInfo &MAI, const MCRegisterInfo &MRI,
117 const TargetAsmInfo *TAI);
113118 ~MCContext();
114119
115120 const MCAsmInfo &getAsmInfo() const { return MAI; }
121
122 const MCRegisterInfo &getRegisterInfo() const { return MRI; }
116123
117124 const TargetAsmInfo &getTargetAsmInfo() const { return *TAI; }
118125
1515 #ifndef LLVM_MC_MCREGISTERINFO_H
1616 #define LLVM_MC_MCREGISTERINFO_H
1717
18 #include "llvm/ADT/DenseMap.h"
1819 #include
1920
2021 namespace llvm {
5051 ///
5152 class MCRegisterInfo {
5253 private:
53 const MCRegisterDesc *Desc; // Pointer to the descriptor array
54 unsigned NumRegs; // Number of entries in the array
54 const MCRegisterDesc *Desc; // Pointer to the descriptor array
55 unsigned NumRegs; // Number of entries in the array
56 unsigned RAReg; // Return address register
57 DenseMap L2DwarfRegs; // LLVM to Dwarf regs mapping
58 DenseMap EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
59 DenseMap Dwarf2LRegs; // Dwarf to LLVM regs mapping
60 DenseMap EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
61 DenseMap L2SEHRegs; // LLVM to SEH regs mapping
5562
5663 public:
5764 /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
5865 /// auto-generated routines. *DO NOT USE*.
59 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR) {
66 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA) {
6067 Desc = D;
6168 NumRegs = NR;
69 RAReg = RA;
70 }
71
72 /// mapLLVMRegToDwarfReg - Used to initialize LLVM register to Dwarf
73 /// register number mapping. Called by TableGen auto-generated routines.
74 /// *DO NOT USE*.
75 void mapLLVMRegToDwarfReg(unsigned LLVMReg, int DwarfReg, bool isEH) {
76 if (isEH)
77 EHL2DwarfRegs[LLVMReg] = DwarfReg;
78 else
79 L2DwarfRegs[LLVMReg] = DwarfReg;
6280 }
6381
82 /// mapDwarfRegToLLVMReg - Used to initialize Dwarf register to LLVM
83 /// register number mapping. Called by TableGen auto-generated routines.
84 /// *DO NOT USE*.
85 void mapDwarfRegToLLVMReg(unsigned DwarfReg, unsigned LLVMReg, bool isEH) {
86 if (isEH)
87 EHDwarf2LRegs[DwarfReg] = LLVMReg;
88 else
89 Dwarf2LRegs[DwarfReg] = LLVMReg;
90 }
91
92 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
93 /// number mapping. By default the SEH register number is just the same
94 /// as the LLVM register number.
95 /// FIXME: TableGen these numbers. Currently this requires target specific
96 /// initialization code.
97 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
98 L2SEHRegs[LLVMReg] = SEHReg;
99 }
100
101 /// getRARegister - This method should return the register where the return
102 /// address can be found.
103 unsigned getRARegister() const {
104 return RAReg;
105 }
106
64107 const MCRegisterDesc &operator[](unsigned RegNo) const {
65108 assert(RegNo < NumRegs &&
66109 "Attempting to access record for invalid register number!");
121164 unsigned getNumRegs() const {
122165 return NumRegs;
123166 }
167
168 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
169 /// number. Returns -1 if there is no equivalent value. The second
170 /// parameter allows targets to use different numberings for EH info and
171 /// debugging info.
172 int getDwarfRegNum(unsigned RegNum, bool isEH) const {
173 const DenseMap &M = isEH ? EHL2DwarfRegs : L2DwarfRegs;
174 const DenseMap::const_iterator I = M.find(RegNum);
175 if (I == M.end()) return -1;
176 return I->second;
177 }
178
179 /// getLLVMRegNum - Map a dwarf register back to a target register.
180 ///
181 int getLLVMRegNum(unsigned RegNum, bool isEH) const {
182 const DenseMap &M = isEH ? EHDwarf2LRegs : Dwarf2LRegs;
183 const DenseMap::const_iterator I = M.find(RegNum);
184 if (I == M.end()) {
185 assert(0 && "Invalid RegNum");
186 return -1;
187 }
188 return I->second;
189 }
190
191 /// getSEHRegNum - Map a target register to an equivalent SEH register
192 /// number. Returns LLVM register number if there is no equivalent value.
193 int getSEHRegNum(unsigned RegNum) const {
194 const DenseMap::const_iterator I = L2SEHRegs.find(RegNum);
195 if (I == L2SEHRegs.end()) return (int)RegNum;
196 return I->second;
197 }
124198 };
125199
126200 } // End llvm namespace
2828
2929 class TargetAsmInfo {
3030 std::vector InitialFrameState;
31 const TargetRegisterInfo *TRI;
3231 const TargetFrameLowering *TFI;
3332 const TargetLoweringObjectFile *TLOF;
3433
7372 return TFI->getCompactUnwindEncoding(Instrs, DataAlignmentFactor, IsEH);
7473 }
7574
76 const unsigned *getCalleeSavedRegs(MachineFunction *MF = 0) const {
77 return TRI->getCalleeSavedRegs(MF);
78 }
79
80 unsigned getDwarfRARegNum(bool isEH) const {
81 return TRI->getDwarfRegNum(TRI->getRARegister(), isEH);
82 }
83
8475 const std::vector &getInitialFrameState() const {
8576 return InitialFrameState;
86 }
87
88 int getDwarfRegNum(unsigned RegNum, bool isEH) const {
89 return TRI->getDwarfRegNum(RegNum, isEH);
90 }
91
92 int getLLVMRegNum(unsigned DwarfRegNum, bool isEH) const {
93 return TRI->getLLVMRegNum(DwarfRegNum, isEH);
94 }
95
96 int getSEHRegNum(unsigned RegNum) const {
97 return TRI->getSEHRegNum(RegNum);
9877 }
9978 };
10079
698698 //===--------------------------------------------------------------------===//
699699 /// Debug information queries.
700700
701 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
702 /// number. Returns -1 if there is no equivalent value. The second
703 /// parameter allows targets to use different numberings for EH info and
704 /// debugging info.
705 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
706
707 virtual int getLLVMRegNum(unsigned RegNum, bool isEH) const = 0;
708
709701 /// getFrameRegister - This method should return the register used as a base
710702 /// for values allocated in the current stack frame.
711703 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
712
713 /// getRARegister - This method should return the register where the return
714 /// address can be found.
715 virtual unsigned getRARegister() const = 0;
716
717 /// getSEHRegNum - Map a target register to an equivalent SEH register
718 /// number. Returns -1 if there is no equivalent value.
719 virtual int getSEHRegNum(unsigned i) const {
720 return i;
721 }
722704
723705 /// getCompactUnwindRegNum - This function maps the register to the number for
724706 /// compact unwind encoding. Return -1 if the register isn't valid.
6868 typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const Target &T,
6969 StringRef TT);
7070 typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
71 typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(void);
71 typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT);
7272 typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT,
7373 StringRef CPU,
7474 StringRef Features);
262262
263263 /// createMCRegInfo - Create a MCRegisterInfo implementation.
264264 ///
265 MCRegisterInfo *createMCRegInfo() const {
265 MCRegisterInfo *createMCRegInfo(StringRef Triple) const {
266266 if (!MCRegInfoCtorFn)
267267 return 0;
268 return MCRegInfoCtorFn();
268 return MCRegInfoCtorFn(Triple);
269269 }
270270
271271 /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
802802 TargetRegistry::RegisterMCRegInfo(T, &Allocator);
803803 }
804804 private:
805 static MCRegisterInfo *Allocator() {
805 static MCRegisterInfo *Allocator(StringRef TT) {
806806 return new MCRegisterInfoImpl();
807807 }
808808 };
3131
3232 #define LLVM_TARGET(TargetName) \
3333 void LLVMInitialize##TargetName##MCInstrInfo();
34 #include "llvm/Config/Targets.def"
35
36 #define LLVM_TARGET(TargetName) \
37 void LLVMInitialize##TargetName##MCRegisterInfo();
3438 #include "llvm/Config/Targets.def"
3539
3640 #define LLVM_TARGET(TargetName) \
9498 /// It is legal for a client to make multiple calls to this function.
9599 inline void InitializeAllMCInstrInfos() {
96100 #define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##MCInstrInfo();
101 #include "llvm/Config/Targets.def"
102 }
103
104 /// InitializeAllMCRegisterInfos - The main program should call this function
105 /// if it wants access to all available register infos for targets that
106 /// LLVM is configured to support, to make them available via the
107 /// TargetRegistry.
108 ///
109 /// It is legal for a client to make multiple calls to this function.
110 inline void InitializeAllMCRegisterInfos() {
111 #define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##MCRegisterInfo();
97112 #include "llvm/Config/Targets.def"
98113 }
99114
5050 #include "llvm/Target/TargetLowering.h"
5151 #include "llvm/Target/TargetLoweringObjectFile.h"
5252 #include "llvm/Target/TargetMachine.h"
53 #include "llvm/Target/TargetRegisterInfo.h"
5354 #include "llvm/Support/Debug.h"
5455 #include "llvm/Support/ErrorHandling.h"
5556 #include "llvm/Support/raw_ostream.h"
6465
6566 ELFWriter::ELFWriter(raw_ostream &o, TargetMachine &tm)
6667 : MachineFunctionPass(ID), O(o), TM(tm),
67 OutContext(*new MCContext(*TM.getMCAsmInfo(), new TargetAsmInfo(tm))),
68 OutContext(*new MCContext(*TM.getMCAsmInfo(), *TM.getRegisterInfo(),
69 new TargetAsmInfo(tm))),
6870 TLOF(TM.getTargetLowering()->getObjFileLowering()),
6971 is64Bit(TM.getTargetData()->getPointerSizeInBits() == 64),
7072 isLittleEndian(TM.getTargetData()->isLittleEndian()),
369369 // Install a MachineModuleInfo class, which is an immutable pass that holds
370370 // all the per-module stuff we're generating, including MCContext.
371371 TargetAsmInfo *TAI = new TargetAsmInfo(*this);
372 MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo(), TAI);
372 MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo(),
373 *getRegisterInfo(), TAI);
373374 PM.add(MMI);
374375 OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
375376
253253 //===----------------------------------------------------------------------===//
254254
255255 MachineModuleInfo::MachineModuleInfo(const MCAsmInfo &MAI,
256 const MCRegisterInfo &MRI,
256257 const TargetAsmInfo *TAI)
257 : ImmutablePass(ID), Context(MAI, TAI),
258 : ImmutablePass(ID), Context(MAI, MRI, TAI),
258259 ObjFileMMI(0),
259260 CurCallSite(0), CallsEHReturn(0), CallsUnwindInit(0), DbgInfoAvailable(false),
260261 CallsExternalVAFunctionWithFloatingPointArguments(false) {
266267 }
267268
268269 MachineModuleInfo::MachineModuleInfo()
269 : ImmutablePass(ID), Context(*(MCAsmInfo*)0, NULL) {
270 : ImmutablePass(ID), Context(*(MCAsmInfo*)0, *(MCRegisterInfo*)0, NULL) {
270271 assert(0 && "This MachineModuleInfo constructor should never be called, MMI "
271272 "should always be explicitly constructed by LLVMTargetMachine");
272273 abort();
1414 #include "llvm/MC/MCFixupKindInfo.h"
1515 #include "llvm/MC/MCInst.h"
1616 #include "llvm/MC/MCInstPrinter.h"
17 #include "llvm/MC/MCRegisterInfo.h"
1718 #include "llvm/MC/MCSectionMachO.h"
1819 #include "llvm/MC/MCSymbol.h"
1920 #include "llvm/ADT/OwningPtr.h"
826827
827828 void MCAsmStreamer::EmitRegisterName(int64_t Register) {
828829 if (InstPrinter && !MAI.useDwarfRegNumForCFI()) {
829 const TargetAsmInfo &TAI = getContext().getTargetAsmInfo();
830 unsigned LLVMRegister = TAI.getLLVMRegNum(Register, true);
830 const MCRegisterInfo &MRI = getContext().getRegisterInfo();
831 unsigned LLVMRegister = MRI.getLLVMRegNum(Register, true);
831832 InstPrinter->printRegName(OS, LLVMRegister);
832833 } else {
833834 OS << Register;
88
99 #include "llvm/MC/MCContext.h"
1010 #include "llvm/MC/MCAsmInfo.h"
11 #include "llvm/MC/MCRegisterInfo.h"
1112 #include "llvm/MC/MCSectionMachO.h"
1213 #include "llvm/MC/MCSectionELF.h"
1314 #include "llvm/MC/MCSectionCOFF.h"
2526 typedef StringMap COFFUniqueMapTy;
2627
2728
28 MCContext::MCContext(const MCAsmInfo &mai, const TargetAsmInfo *tai) :
29 MAI(mai), TAI(tai),
29 MCContext::MCContext(const MCAsmInfo &mai, const MCRegisterInfo &mri,
30 const TargetAsmInfo *tai) :
31 MAI(mai), MRI(mri), TAI(tai),
3032 Allocator(), Symbols(Allocator), UsedNames(Allocator),
3133 NextUniqueID(0),
3234 CurrentDwarfLoc(0,0,0,DWARF2_FLAG_IS_STMT,0,0),
4040 // FIXME: We shouldn't need to initialize the Target(Machine)s.
4141 llvm::InitializeAllTargets();
4242 llvm::InitializeAllMCAsmInfos();
43 llvm::InitializeAllMCRegisterInfos();
4344 llvm::InitializeAllAsmPrinters();
4445 llvm::InitializeAllAsmParsers();
4546 llvm::InitializeAllDisassemblers();
5253 // Get the assembler info needed to setup the MCContext.
5354 const MCAsmInfo *MAI = TheTarget->createMCAsmInfo(TripleName);
5455 assert(MAI && "Unable to create target asm info!");
56
57 const MCRegisterInfo *MRI = TheTarget->createMCRegInfo(TripleName);
58 assert(MRI && "Unable to create target register info!");
5559
5660 // Package up features to be passed to target/subtarget
5761 std::string FeaturesStr;
6973 assert(tai && "Unable to create target assembler!");
7074
7175 // Set up the MCContext for creating symbols and MCExpr's.
72 MCContext *Ctx = new MCContext(*MAI, tai);
76 MCContext *Ctx = new MCContext(*MAI, *MRI, tai);
7377 assert(Ctx && "Unable to create MCContext!");
7478
7579 // Set up disassembler.
8589
8690 LLVMDisasmContext *DC = new LLVMDisasmContext(TripleName, DisInfo, TagType,
8791 GetOpInfo, SymbolLookUp,
88 TheTarget, MAI, TM, tai, Ctx,
89 DisAsm, IP);
92 TheTarget, MAI, MRI, TM, tai,
93 Ctx, DisAsm, IP);
9094 assert(DC && "Allocation failure!");
9195 return DC;
9296 }
2626 class MCAsmInfo;
2727 class MCDisassembler;
2828 class MCInstPrinter;
29 class MCRegisterInfo;
2930 class Target;
3031 class TargetMachine;
3132
5758 const Target *TheTarget;
5859 // The assembly information for the target architecture.
5960 llvm::OwningPtr MAI;
61 // The register information for the target architecture.
62 llvm::OwningPtr MRI;
6063 // The target machine instance.
6164 llvm::OwningPtr TM;
6265 // The disassembler for the target architecture.
7578 LLVMOpInfoCallback getOpInfo,
7679 LLVMSymbolLookupCallback symbolLookUp,
7780 const Target *theTarget, const MCAsmInfo *mAI,
81 const MCRegisterInfo *mRI,
7882 llvm::TargetMachine *tM, const TargetAsmInfo *tai,
7983 llvm::MCContext *ctx, const MCDisassembler *disAsm,
8084 MCInstPrinter *iP) : TripleName(tripleName),
8286 SymbolLookUp(symbolLookUp), TheTarget(theTarget), Tai(tai) {
8387 TM.reset(tM);
8488 MAI.reset(mAI);
89 MRI.reset(mRI);
8590 Ctx.reset(ctx);
8691 DisAsm.reset(disAsm);
8792 IP.reset(iP);
2121 #include "llvm/MC/MCExpr.h"
2222 #include "llvm/MC/MCInst.h"
2323 #include "llvm/MC/MCInstPrinter.h"
24 #include "llvm/MC/MCRegisterInfo.h"
2425 #include "llvm/MC/MCStreamer.h"
2526 #include "llvm/MC/MCSubtargetInfo.h"
2627 #include "llvm/MC/MCParser/AsmLexer.h"
107108 InitializeAllTargetInfos();
108109 InitializeAllTargets();
109110 InitializeAllMCAsmInfos();
111 InitializeAllMCRegisterInfos();
110112 InitializeAllAsmPrinters();
111113 InitializeAllAsmParsers();
112114 InitializeAllDisassemblers();
183185 AsmInfo.reset(Tgt->createMCAsmInfo(tripleString));
184186
185187 if (!AsmInfo)
188 return;
189
190 MRI.reset(Tgt->createMCRegInfo(tripleString));
191
192 if (!MRI)
186193 return;
187194
188195 Disassembler.reset(Tgt->createMCDisassembler());
367374 SourceMgr sourceMgr;
368375 sourceMgr.setDiagHandler(diag_handler, static_cast(this));
369376 sourceMgr.AddNewSourceBuffer(buf, SMLoc()); // ownership of buf handed over
370 MCContext context(*AsmInfo, NULL);
377 MCContext context(*AsmInfo, *MRI, NULL);
371378 OwningPtr streamer(createNullStreamer(context));
372379 OwningPtr genericParser(createMCAsmParser(*Tgt, sourceMgr,
373380 context, *streamer,
2828
2929 namespace llvm {
3030 class AsmLexer;
31 class AsmParser;
3132 class AsmToken;
3233 class MCContext;
3334 class MCAsmInfo;
3435 class MCAsmLexer;
35 class AsmParser;
36 class TargetAsmLexer;
37 class TargetAsmParser;
3836 class MCDisassembler;
3937 class MCInstPrinter;
4038 class MCInst;
4139 class MCParsedAsmOperand;
40 class MCRegisterInfo;
4241 class MCStreamer;
4342 class MCSubtargetInfo;
4443 template class SmallVectorImpl;
4544 class SourceMgr;
4645 class Target;
46 class TargetAsmLexer;
47 class TargetAsmParser;
4748 class TargetMachine;
4849 class TargetRegisterInfo;
4950
139140 llvm::OwningPtr TargetMachine;
140141 /// The assembly information for the target architecture
141142 llvm::OwningPtr AsmInfo;
143 // The register information for the target architecture.
144 llvm::OwningPtr MRI;
142145 /// The disassembler for the target architecture
143146 llvm::OwningPtr Disassembler;
144147 /// The output string for the instruction printer; must be guarded with
484484 }
485485
486486 static const MachineLocation TranslateMachineLocation(
487 const TargetAsmInfo &TAI,
487 const MCRegisterInfo &MRI,
488488 const MachineLocation &Loc) {
489489 unsigned Reg = Loc.getReg() == MachineLocation::VirtualFP ?
490490 MachineLocation::VirtualFP :
491 unsigned(TAI.getDwarfRegNum(Loc.getReg(), true));
491 unsigned(MRI.getDwarfRegNum(Loc.getReg(), true));
492492 const MachineLocation &NewLoc = Loc.isReg() ?
493493 MachineLocation(Reg) : MachineLocation(Reg, Loc.getOffset());
494494 return NewLoc;
770770 const MCSymbol *lsda,
771771 unsigned lsdaEncoding) {
772772 MCContext &context = streamer.getContext();
773 const MCRegisterInfo &MRI = context.getRegisterInfo();
773774 const TargetAsmInfo &TAI = context.getTargetAsmInfo();
774775 bool verboseAsm = streamer.isVerboseAsm();
775776
823824
824825 // Return Address Register
825826 if (verboseAsm) streamer.AddComment("CIE Return Address Column");
826 streamer.EmitULEB128IntValue(TAI.getDwarfRARegNum(true));
827 streamer.EmitULEB128IntValue(MRI.getDwarfRegNum(MRI.getRARegister(), true));
827828
828829 // Augmentation Data Length (optional)
829830
869870 for (int i = 0, n = Moves.size(); i != n; ++i) {
870871 MCSymbol *Label = Moves[i].getLabel();
871872 const MachineLocation &Dst =
872 TranslateMachineLocation(TAI, Moves[i].getDestination());
873 TranslateMachineLocation(MRI, Moves[i].getDestination());
873874 const MachineLocation &Src =
874 TranslateMachineLocation(TAI, Moves[i].getSource());
875 TranslateMachineLocation(MRI, Moves[i].getSource());
875876 MCCFIInstruction Inst(Label, Dst, Src);
876877 Instructions.push_back(Inst);
877878 }
24152415 if (getParser().getTargetParser().ParseRegister(RegNo, DirectiveLoc,
24162416 DirectiveLoc))
24172417 return true;
2418 Register = getContext().getTargetAsmInfo().getDwarfRegNum(RegNo, true);
2418 Register = getContext().getRegisterInfo().getDwarfRegNum(RegNo, true);
24192419 } else
24202420 return getParser().ParseAbsoluteExpression(Register);
24212421
1111 #include "llvm/MC/MCAsmInfo.h"
1212 #include "llvm/MC/MCContext.h"
1313 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCRegisterInfo.h"
1415 #include "llvm/MC/MCSectionCOFF.h"
1516 #include "llvm/MC/MCStreamer.h"
1617 #include "llvm/MC/MCExpr.h"
17 #include "llvm/Target/TargetAsmInfo.h"
1818 #include "llvm/Target/TargetAsmParser.h"
1919 #include "llvm/Support/COFF.h"
2020 using namespace llvm;
400400 bool COFFAsmParser::ParseSEHRegisterNumber(unsigned &RegNo) {
401401 SMLoc startLoc = getLexer().getLoc();
402402 if (getLexer().is(AsmToken::Percent)) {
403 const TargetAsmInfo &TAI = getContext().getTargetAsmInfo();
403 const MCRegisterInfo &MRI = getContext().getRegisterInfo();
404404 SMLoc endLoc;
405405 unsigned LLVMRegNo;
406406 if (getParser().getTargetParser().ParseRegister(LLVMRegNo,startLoc,endLoc))
407407 return true;
408
409 #if 0
410 // FIXME: TargetAsmInfo::getCalleeSavedRegs() commits a serious layering
411 // violation so this validation code is disabled.
408412
409413 // Check that this is a non-volatile register.
410414 const unsigned *NVRegs = TAI.getCalleeSavedRegs();
414418 break;
415419 if (NVRegs[i] == 0)
416420 return Error(startLoc, "expected non-volatile register");
417
418 int SEHRegNo = TAI.getSEHRegNum(LLVMRegNo);
421 #endif
422
423 int SEHRegNo = MRI.getSEHRegNum(LLVMRegNo);
419424 if (SEHRegNo < 0)
420425 return Error(startLoc,"register can't be represented in SEH unwind info");
421426 RegNo = SEHRegNo;
5656
5757 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
5858 const ARMSubtarget &sti)
59 : ARMGenRegisterInfo(), TII(tii), STI(sti),
59 : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti),
6060 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
6161 BasePtr(ARM::R6) {
6262 }
648648 || needsStackRealignment(MF);
649649 }
650650
651 unsigned ARMBaseRegisterInfo::getRARegister() const {
652 return ARM::LR;
653 }
654
655651 unsigned
656652 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
657653 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
669665 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
670666 llvm_unreachable("What is the exception handler register");
671667 return 0;
672 }
673
674 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
675 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
676 }
677
678 int ARMBaseRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
679 return ARMGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
680668 }
681669
682670 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
163163 bool cannotEliminateFrame(const MachineFunction &MF) const;
164164
165165 // Debug information queries.
166 unsigned getRARegister() const;
167166 unsigned getFrameRegister(const MachineFunction &MF) const;
168167 unsigned getBaseRegister() const { return BasePtr; }
169168
170169 // Exception handling queries.
171170 unsigned getEHExceptionRegister() const;
172171 unsigned getEHHandlerRegister() const;
173
174 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
175 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
176172
177173 bool isLowRegister(unsigned Reg) const;
178174
116116 TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
117117 }
118118
119 static MCRegisterInfo *createARMMCRegisterInfo() {
119 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
120120 MCRegisterInfo *X = new MCRegisterInfo();
121 InitARMMCRegisterInfo(X);
121 InitARMMCRegisterInfo(X, ARM::LR);
122122 return X;
123123 }
124124
125 extern "C" void LLVMInitializeARMMCRegInfo() {
125 extern "C" void LLVMInitializeARMMCRegisterInfo() {
126126 TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
127127 TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
128128 }
3939 using namespace llvm;
4040
4141 AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
42 : AlphaGenRegisterInfo(),
43 TII(tii) {
42 : AlphaGenRegisterInfo(Alpha::R26), TII(tii) {
4443 }
4544
4645 static long getUpper16(long l) {
177176 }
178177 }
179178
180 unsigned AlphaRegisterInfo::getRARegister() const {
181 return Alpha::R26;
182 }
183
184179 unsigned AlphaRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
185180 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
186181
195190 unsigned AlphaRegisterInfo::getEHHandlerRegister() const {
196191 llvm_unreachable("What is the exception handler register");
197192 return 0;
198 }
199
200 int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
201 llvm_unreachable("What is the dwarf register number");
202 return -1;
203 }
204
205 int AlphaRegisterInfo::getLLVMRegNum(unsigned DwarfRegNum, bool isEH) const {
206 llvm_unreachable("What is the dwarf register number");
207 return -1;
208193 }
209194
210195 std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
4141 int SPAdj, RegScavenger *RS = NULL) const;
4242
4343 // Debug information queries.
44 unsigned getRARegister() const;
4544 unsigned getFrameRegister(const MachineFunction &MF) const;
4645
4746 // Exception handling queries.
4847 unsigned getEHExceptionRegister() const;
4948 unsigned getEHHandlerRegister() const;
50
51 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
52 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
5349
5450 static std::string getPrettyName(unsigned reg);
5551 };
3939 TargetRegistry::RegisterMCInstrInfo(TheAlphaTarget, createAlphaMCInstrInfo);
4040 }
4141
42 static MCRegisterInfo *createAlphaMCRegisterInfo(StringRef TT) {
43 MCRegisterInfo *X = new MCRegisterInfo();
44 InitAlphaMCRegisterInfo(X, Alpha::R26);
45 return X;
46 }
47
48 extern "C" void LLVMInitializeAlphaMCRegisterInfo() {
49 TargetRegistry::RegisterMCRegInfo(TheAlphaTarget, createAlphaMCRegisterInfo);
50 }
51
4252 static MCSubtargetInfo *createAlphaMCSubtargetInfo(StringRef TT, StringRef CPU,
4353 StringRef FS) {
4454 MCSubtargetInfo *X = new MCSubtargetInfo();
3636
3737 BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st,
3838 const TargetInstrInfo &tii)
39 : BlackfinGenRegisterInfo(), Subtarget(st), TII(tii) {}
39 : BlackfinGenRegisterInfo(BF::RETS), Subtarget(st), TII(tii) {}
4040
4141 const unsigned*
4242 BlackfinRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
326326 }
327327 }
328328
329 unsigned BlackfinRegisterInfo::getRARegister() const {
330 return BF::RETS;
331 }
332
333329 unsigned
334330 BlackfinRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
335331 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
346342 llvm_unreachable("What is the exception handler register");
347343 return 0;
348344 }
349
350 int BlackfinRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
351 llvm_unreachable("What is the dwarf register number");
352 return -1;
353 }
354
355 int BlackfinRegisterInfo::getLLVMRegNum(unsigned DwarfRegNum,
356 bool isEH) const {
357 llvm_unreachable("What is the dwarf register number");
358 return -1;
359 }
5252 int SPAdj, RegScavenger *RS = NULL) const;
5353
5454 unsigned getFrameRegister(const MachineFunction &MF) const;
55 unsigned getRARegister() const;
5655
5756 // Exception handling queries.
5857 unsigned getEHExceptionRegister() const;
5958 unsigned getEHHandlerRegister() const;
60
61 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
62 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
6359
6460 // Utility functions
6561 void adjustRegister(MachineBasicBlock &MBB,
4040 createBlackfinMCInstrInfo);
4141 }
4242
43 static MCRegisterInfo *createBlackfinMCRegisterInfo(StringRef TT) {
44 MCRegisterInfo *X = new MCRegisterInfo();
45 InitBlackfinMCRegisterInfo(X, BF::RETS);
46 return X;
47 }
48
49 extern "C" void LLVMInitializeBlackfinMCRegisterInfo() {
50 TargetRegistry::RegisterMCRegInfo(TheBlackfinTarget,
51 createBlackfinMCRegisterInfo);
52 }
4353
4454 static MCSubtargetInfo *createBlackfinMCSubtargetInfo(StringRef TT,
4555 StringRef CPU,
3636 #include "llvm/MC/MCAsmInfo.h"
3737 #include "llvm/MC/MCContext.h"
3838 #include "llvm/MC/MCInstrInfo.h"
39 #include "llvm/MC/MCRegisterInfo.h"
3940 #include "llvm/MC/MCSubtargetInfo.h"
4041 #include "llvm/MC/MCSymbol.h"
4142 #include "llvm/Target/TargetData.h"
6364
6465 extern "C" void LLVMInitializeCBackendMCAsmInfo() {}
6566
67 extern "C" void LLVMInitializeCBackendMCRegisterInfo() {}
68
6669 extern "C" void LLVMInitializeCBackendMCInstrInfo() {}
6770
6871 extern "C" void LLVMInitializeCBackendMCSubtargetInfo() {}
8588 LoopInfo *LI;
8689 const Module *TheModule;
8790 const MCAsmInfo* TAsm;
91 const MCRegisterInfo *MRI;
8892 MCContext *TCtx;
8993 const TargetData* TD;
9094
104108 static char ID;
105109 explicit CWriter(formatted_raw_ostream &o)
106110 : FunctionPass(ID), Out(o), IL(0), Mang(0), LI(0),
107 TheModule(0), TAsm(0), TCtx(0), TD(0), OpaqueCounter(0),
111 TheModule(0), TAsm(0), MRI(0), TCtx(0), TD(0), OpaqueCounter(0),
108112 NextAnonValueNumber(0) {
109113 initializeLoopInfoPass(*PassRegistry::getPassRegistry());
110114 FPCounter = 0;
144148 delete Mang;
145149 delete TCtx;
146150 delete TAsm;
151 delete MRI;
147152 FPConstantMap.clear();
148153 ByValParams.clear();
149154 intrinsicPrototypesAlreadyGenerated.clear();
16641669 TAsm = Match->createMCAsmInfo(Triple);
16651670 #endif
16661671 TAsm = new CBEMCAsmInfo();
1667 TCtx = new MCContext(*TAsm, NULL);
1672 MRI = new MCRegisterInfo();
1673 TCtx = new MCContext(*TAsm, *MRI, NULL);
16681674 Mang = new Mangler(*TCtx, *TD);
16691675
16701676 // Keep track of which functions are static ctors/dtors so they can have
3838 TargetRegistry::RegisterMCInstrInfo(TheCellSPUTarget, createSPUMCInstrInfo);
3939 }
4040
41 static MCRegisterInfo *createCellSPUMCRegisterInfo(StringRef TT) {
42 MCRegisterInfo *X = new MCRegisterInfo();
43 InitSPUMCRegisterInfo(X, SPU::R0);
44 return X;
45 }
46
47 extern "C" void LLVMInitializeCellSPUMCRegisterInfo() {
48 TargetRegistry::RegisterMCRegInfo(TheCellSPUTarget,
49 createCellSPUMCRegisterInfo);
50 }
51
4152 static MCSubtargetInfo *createSPUMCSubtargetInfo(StringRef TT, StringRef CPU,
4253 StringRef FS) {
4354 MCSubtargetInfo *X = new MCSubtargetInfo();
186186
187187 SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
188188 const TargetInstrInfo &tii) :
189 SPUGenRegisterInfo(), Subtarget(subtarget), TII(tii)
189 SPUGenRegisterInfo(SPU::R0), Subtarget(subtarget), TII(tii)
190190 {
191191 }
192192
310310 }
311311
312312 unsigned
313 SPURegisterInfo::getRARegister() const
314 {
315 return SPU::R0;
316 }
317
318 unsigned
319313 SPURegisterInfo::getFrameRegister(const MachineFunction &MF) const
320314 {
321315 return SPU::R1;
322 }
323
324 int
325 SPURegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
326 // FIXME: Most probably dwarf numbers differs for Linux and Darwin
327 return SPUGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
328 }
329
330 int SPURegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
331 return SPUGenRegisterInfo::getLLVMRegNumFull(RegNum, 0);
332316 }
333317
334318 int
7373 void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
7474 RegScavenger *RS = NULL) const;
7575
76 //! Get return address register (LR, aka R0)
77 unsigned getRARegister() const;
7876 //! Get the stack frame register (SP, aka R1)
7977 unsigned getFrameRegister(const MachineFunction &MF) const;
8078
8179 //------------------------------------------------------------------------
8280 // New methods added:
8381 //------------------------------------------------------------------------
84
85 //! Get DWARF debugging register number
86 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
87 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
8882
8983 //! Convert D-form load/store to X-form load/store
9084 /*!
7878
7979 extern "C" void LLVMInitializeCppBackendMCAsmInfo() {}
8080
81 extern "C" void LLVMInitializeCppBackendMCInstrInfo() {
82 RegisterMCInstrInfo X(TheCppBackendTarget);
83 }
84
85 extern "C" void LLVMInitializeCppBackendMCSubtargetInfo() {
86 RegisterMCSubtargetInfo X(TheCppBackendTarget);
87 }
81 extern "C" void LLVMInitializeCppBackendMCRegisterInfo() {}
82
83 extern "C" void LLVMInitializeCppBackendMCInstrInfo() {}
84
85 extern "C" void LLVMInitializeCppBackendMCSubtargetInfo() {}
8886
8987 namespace {
9088 typedef std::vector TypeList;
4343
4444 MBlazeRegisterInfo::
4545 MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii)
46 : MBlazeGenRegisterInfo(), Subtarget(ST), TII(tii) {}
46 : MBlazeGenRegisterInfo(MBlaze::R15), Subtarget(ST), TII(tii) {}
4747
4848 /// getRegisterNumbering - Given the enum value for some register, e.g.
4949 /// MBlaze::R0, return the number that it corresponds to (e.g. 0).
333333 MFI->setObjectOffset(MBlazeFI->getGPFI(), MBlazeFI->getGPStackOffset());
334334 }
335335
336 unsigned MBlazeRegisterInfo::getRARegister() const {
337 return MBlaze::R15;
338 }
339
340336 unsigned MBlazeRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
341337 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
342338
352348 llvm_unreachable("What is the exception handler register");
353349 return 0;
354350 }
355
356 int MBlazeRegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
357 return MBlazeGenRegisterInfo::getDwarfRegNumFull(RegNo,0);
358 }
359
360 int MBlazeRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
361 return MBlazeGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
362 }
6868 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
6969
7070 /// Debug information queries.
71 unsigned getRARegister() const;
7271 unsigned getFrameRegister(const MachineFunction &MF) const;
7372
7473 /// Exception handling queries.
7574 unsigned getEHExceptionRegister() const;
7675 unsigned getEHHandlerRegister() const;
77
78 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
79 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
8076 };
8177
8278 } // end namespace llvm
3939 TargetRegistry::RegisterMCInstrInfo(TheMBlazeTarget, createMBlazeMCInstrInfo);
4040 }
4141
42 static MCRegisterInfo *createMBlazeMCRegisterInfo(StringRef TT) {
43 MCRegisterInfo *X = new MCRegisterInfo();
44 InitMBlazeMCRegisterInfo(X, MBlaze::R15);
45 return X;
46 }
47
48 extern "C" void LLVMInitializeMBlazeMCRegisterInfo() {
49 TargetRegistry::RegisterMCRegInfo(TheMBlazeTarget,
50 createMBlazeMCRegisterInfo);
51 }
52
4253 static MCSubtargetInfo *createMBlazeMCSubtargetInfo(StringRef TT, StringRef CPU,
4354 StringRef FS) {
4455 MCSubtargetInfo *X = new MCSubtargetInfo();
2828
2929 using namespace llvm;
3030
31
3231 static MCInstrInfo *createMSP430MCInstrInfo() {
3332 MCInstrInfo *X = new MCInstrInfo();
3433 InitMSP430MCInstrInfo(X);
3938 TargetRegistry::RegisterMCInstrInfo(TheMSP430Target, createMSP430MCInstrInfo);
4039 }
4140
41
42 static MCRegisterInfo *createMSP430MCRegisterInfo(StringRef TT) {
43 MCRegisterInfo *X = new MCRegisterInfo();
44 InitMSP430MCRegisterInfo(X, MSP430::PCW);
45 return X;
46 }
47
48 extern "C" void LLVMInitializeMSP430MCRegisterInfo() {
49 TargetRegistry::RegisterMCRegInfo(TheMSP430Target,
50 createMSP430MCRegisterInfo);
51 }
4252
4353 static MCSubtargetInfo *createMSP430MCSubtargetInfo(StringRef TT, StringRef CPU,
4454 StringRef FS) {
3333 // FIXME: Provide proper call frame setup / destroy opcodes.
3434 MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
3535 const TargetInstrInfo &tii)
36 : MSP430GenRegisterInfo(), TM(tm), TII(tii) {
36 : MSP430GenRegisterInfo(MSP430::PCW), TM(tm), TII(tii) {
3737 StackAlign = TM.getFrameLowering()->getStackAlignment();
3838 }
3939
232232 }
233233 }
234234
235 unsigned MSP430RegisterInfo::getRARegister() const {
236 return MSP430::PCW;
237 }
238
239235 unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
240236 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
241237
242238 return TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW;
243239 }
244
245 int MSP430RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
246 llvm_unreachable("Not implemented yet!");
247 return 0;
248 }
249
250 int MSP430RegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
251 llvm_unreachable("Not implemented yet!");
252 return 0;
253 }
5757 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
5858
5959 // Debug information queries.
60 unsigned getRARegister() const;
6160 unsigned getFrameRegister(const MachineFunction &MF) const;
62
63 //! Get DWARF debugging register number
64 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
65 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
6661 };
6762
6863 } // end namespace llvm
3838 TargetRegistry::RegisterMCInstrInfo(TheMipsTarget, createMipsMCInstrInfo);
3939 }
4040
41 static MCRegisterInfo *createMipsMCRegisterInfo(StringRef TT) {
42 MCRegisterInfo *X = new MCRegisterInfo();
43 InitMipsMCRegisterInfo(X, Mips::RA);
44 return X;
45 }
46
47 extern "C" void LLVMInitializeMipsMCRegisterInfo() {
48 TargetRegistry::RegisterMCRegInfo(TheMipsTarget, createMipsMCRegisterInfo);
49 TargetRegistry::RegisterMCRegInfo(TheMipselTarget, createMipsMCRegisterInfo);
50 }
4151
4252 static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU,
4353 StringRef FS) {
4343
4444 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
4545 const TargetInstrInfo &tii)
46 : MipsGenRegisterInfo(), Subtarget(ST), TII(tii) {}
46 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {}
4747
4848 /// getRegisterNumbering - Given the enum value for some register, e.g.
4949 /// Mips::RA, return the number that it corresponds to (e.g. 31).
244244 }
245245
246246 unsigned MipsRegisterInfo::
247 getRARegister() const {
248 return Mips::RA;
249 }
250
251 unsigned MipsRegisterInfo::
252247 getFrameRegister(const MachineFunction &MF) const {
253248 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
254249
266261 llvm_unreachable("What is the exception handler register");
267262 return 0;
268263 }
269
270 int MipsRegisterInfo::
271 getDwarfRegNum(unsigned RegNum, bool isEH) const {
272 return MipsGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
273 }
274
275 int MipsRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
276 return MipsGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
277 }
5656 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
5757
5858 /// Debug information queries.
59 unsigned getRARegister() const;
6059 unsigned getFrameRegister(const MachineFunction &MF) const;
6160
6261 /// Exception handling queries.
6362 unsigned getEHExceptionRegister() const;
6463 unsigned getEHHandlerRegister() const;
65
66 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
67 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
6864 };
6965
7066 } // end namespace llvm
3939 TargetRegistry::RegisterMCInstrInfo(ThePTX64Target, createPTXMCInstrInfo);
4040 }
4141
42 static MCRegisterInfo *createPTXMCRegisterInfo(StringRef TT) {
43 MCRegisterInfo *X = new MCRegisterInfo();
44 // PTX does not have a return address register.
45 InitPTXMCRegisterInfo(X, 0);
46 return X;
47 }
48
49 extern "C" void LLVMInitializePTXMCRegisterInfo() {
50 TargetRegistry::RegisterMCRegInfo(ThePTX32Target, createPTXMCRegisterInfo);
51 TargetRegistry::RegisterMCRegInfo(ThePTX64Target, createPTXMCRegisterInfo);
52 }
53
4254 static MCSubtargetInfo *createPTXMCSubtargetInfo(StringRef TT, StringRef CPU,
4355 StringRef FS) {
4456 MCSubtargetInfo *X = new MCSubtargetInfo();
2323
2424 PTXRegisterInfo::PTXRegisterInfo(PTXTargetMachine &TM,
2525 const TargetInstrInfo &TII)
26 : PTXGenRegisterInfo() {
26 // PTX does not have a return address register.
27 : PTXGenRegisterInfo(0) {
2728 }
2829
2930 void PTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
4646 llvm_unreachable("PTX does not have a frame register");
4747 return 0;
4848 }
49
50 virtual unsigned getRARegister() const {
51 llvm_unreachable("PTX does not have a return address register");
52 return 0;
53 }
54
55 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const {
56 return PTXGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
57 }
58 virtual int getLLVMRegNum(unsigned RegNum, bool isEH) const {
59 return PTXGenRegisterInfo::getLLVMRegNumFull(RegNum, 0);
60 }
6149 }; // struct PTXRegisterInfo
6250 } // namespace llvm
6351
3939 TargetRegistry::RegisterMCInstrInfo(ThePPC64Target, createPPCMCInstrInfo);
4040 }
4141
42 static MCRegisterInfo *createPPCMCRegisterInfo(StringRef TT) {
43 Triple TheTriple(TT);
44 bool isPPC64 = (TheTriple.getArch() == Triple::ppc64);
45 unsigned Flavour = isPPC64 ? 0 : 1;
46 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR;
47
48 MCRegisterInfo *X = new MCRegisterInfo();
49 InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
50 return X;
51 }
52
53 extern "C" void LLVMInitializePowerPCMCRegisterInfo() {
54 TargetRegistry::RegisterMCRegInfo(ThePPC32Target, createPPCMCRegisterInfo);
55 TargetRegistry::RegisterMCRegInfo(ThePPC64Target, createPPCMCRegisterInfo);
56 }
4257
4358 static MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU,
4459 StringRef FS) {
112112
113113 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
114114 const TargetInstrInfo &tii)
115 : PPCGenRegisterInfo(), Subtarget(ST), TII(tii) {
115 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
116 ST.isPPC64() ? 0 : 1,
117 ST.isPPC64() ? 0 : 1),
118 Subtarget(ST), TII(tii) {
116119 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
117120 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
118121 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
667670 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
668671 }
669672
670 unsigned PPCRegisterInfo::getRARegister() const {
671 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
672 }
673
674673 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
675674 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
676675
687686 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
688687 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
689688 }
690
691 /// DWARFFlavour - Flavour of dwarf regnumbers
692 ///
693 namespace DWARFFlavour {
694 enum {
695 PPC64 = 0, PPC32 = 1
696 };
697 }
698
699 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
700 // FIXME: Most probably dwarf numbers differs for Linux and Darwin
701 unsigned Flavour = Subtarget.isPPC64() ?
702 DWARFFlavour::PPC64 : DWARFFlavour::PPC32;
703
704 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, Flavour);
705 }
706
707 int PPCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
708 // FIXME: Most probably dwarf numbers differs for Linux and Darwin
709 unsigned Flavour = Subtarget.isPPC64() ?
710 DWARFFlavour::PPC64 : DWARFFlavour::PPC32;
711
712 return PPCGenRegisterInfo::getLLVMRegNumFull(RegNum, Flavour);
713 }
6161 int SPAdj, RegScavenger *RS = NULL) const;
6262
6363 // Debug information queries.
64 unsigned getRARegister() const;
6564 unsigned getFrameRegister(const MachineFunction &MF) const;
6665
6766 // Exception handling queries.
6867 unsigned getEHExceptionRegister() const;
6968 unsigned getEHHandlerRegister() const;
70
71 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
72 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
7369 };
7470
7571 } // end namespace llvm
3838 TargetRegistry::RegisterMCInstrInfo(TheSparcTarget, createSparcMCInstrInfo);
3939 }
4040
41 static MCRegisterInfo *createSparcMCRegisterInfo(StringRef TT) {
42 MCRegisterInfo *X = new MCRegisterInfo();
43 InitSparcMCRegisterInfo(X, SP::I7);
44 return X;
45 }
46
47 extern "C" void LLVMInitializeSparcMCRegisterInfo() {
48 TargetRegistry::RegisterMCRegInfo(TheSparcTarget, createSparcMCRegisterInfo);
49 }
50
4151 static MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU,
4252 StringRef FS) {
4353 MCSubtargetInfo *X = new MCSubtargetInfo();
3030
3131 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
3232 const TargetInstrInfo &tii)
33 : SparcGenRegisterInfo(), Subtarget(st), TII(tii) {
33 : SparcGenRegisterInfo(SP::I7), Subtarget(st), TII(tii) {
3434 }
3535
3636 const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
112112 void SparcRegisterInfo::
113113 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
114114
115 unsigned SparcRegisterInfo::getRARegister() const {
116 return SP::I7;
117 }
118
119115 unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
120116 return SP::I6;
121117 }
129125 llvm_unreachable("What is the exception handler register");
130126 return 0;
131127 }
132
133 int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
134 return SparcGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
135 }
136
137 int SparcRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
138 return SparcGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
139 }
4545 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
4646
4747 // Debug information queries.
48 unsigned getRARegister() const;
4948 unsigned getFrameRegister(const MachineFunction &MF) const;
5049
5150 // Exception handling queries.
5251 unsigned getEHExceptionRegister() const;
5352 unsigned getEHHandlerRegister() const;
54
55 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
56 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
5753 };
5854
5955 } // end namespace llvm
3939 createSystemZMCInstrInfo);
4040 }
4141
42 static MCRegisterInfo *createSystemZMCRegisterInfo(StringRef TT) {
43 MCRegisterInfo *X = new MCRegisterInfo();
44 InitSystemZMCRegisterInfo(X, 0);
45 return X;
46 }
47
48 extern "C" void LLVMInitializeSystemZMCRegisterInfo() {
49 TargetRegistry::RegisterMCRegInfo(TheSystemZTarget,
50 createSystemZMCRegisterInfo);
51 }
52
4253 static MCSubtargetInfo *createSystemZMCSubtargetInfo(StringRef TT,
4354 StringRef CPU,
4455 StringRef FS) {
3232
3333 SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm,
3434 const SystemZInstrInfo &tii)
35 : SystemZGenRegisterInfo(), TM(tm), TII(tii) {
35 : SystemZGenRegisterInfo(0), TM(tm), TII(tii) {
3636 }
3737
3838 const unsigned*
125125 MI.getOperand(i+1).ChangeToImmediate(Offset);
126126 }
127127
128 unsigned SystemZRegisterInfo::getRARegister() const {
129 assert(0 && "What is the return address register");
130 return 0;
131 }
132
133128 unsigned
134129 SystemZRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
135130 assert(0 && "What is the frame register");
145140 assert(0 && "What is the exception handler register");
146141 return 0;
147142 }
148
149 int SystemZRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
150 assert(0 && "What is the dwarf register number");
151 return -1;
152 }
153
154 int SystemZRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
155 assert(0 && "What is the dwarf register number");
156 return -1;
157 }
4747 int SPAdj, RegScavenger *RS = NULL) const;
4848
4949 // Debug information queries.
50 unsigned getRARegister() const;
5150 unsigned getFrameRegister(const MachineFunction &MF) const;
5251
5352 // Exception handling queries.
5453 unsigned getEHExceptionRegister() const;
5554 unsigned getEHHandlerRegister() const;
56
57 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
58 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
5955 };
6056
6157 } // end namespace llvm
1717 TargetAsmInfo::TargetAsmInfo(const TargetMachine &TM) {
1818 TLOF = &TM.getTargetLowering()->getObjFileLowering();
1919 TFI = TM.getFrameLowering();
20 TRI = TM.getRegisterInfo();
2120 TFI->getInitialFrameState(InitialFrameState);
2221 }
106106 }
107107 }
108108
109 unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) {
110 Triple TheTriple(TT);
111 if (TheTriple.getArch() == Triple::x86_64)
112 return DWARFFlavour::X86_64;
113
114 if (TheTriple.isOSDarwin())
115 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
116 if (TheTriple.getOS() == Triple::MinGW32 ||
117 TheTriple.getOS() == Triple::Cygwin)
118 // Unsupported by now, just quick fallback
119 return DWARFFlavour::X86_32_Generic;
120 return DWARFFlavour::X86_32_Generic;
121 }
122
123 /// getX86RegNum - This function maps LLVM register identifiers to their X86
124 /// specific numbering, which is used in various places encoding instructions.
125 unsigned X86_MC::getX86RegNum(unsigned RegNo) {
126 switch(RegNo) {
127 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
128 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
129 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
130 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
131 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
132 return N86::ESP;
133 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
134 return N86::EBP;
135 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
136 return N86::ESI;
137 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
138 return N86::EDI;
139
140 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
141 return N86::EAX;
142 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
143 return N86::ECX;
144 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
145 return N86::EDX;
146 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
147 return N86::EBX;
148 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
149 return N86::ESP;
150 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
151 return N86::EBP;
152 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
153 return N86::ESI;
154 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
155 return N86::EDI;
156
157 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
158 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
159 return RegNo-X86::ST0;
160
161 case X86::XMM0: case X86::XMM8:
162 case X86::YMM0: case X86::YMM8: case X86::MM0:
163 return 0;
164 case X86::XMM1: case X86::XMM9:
165 case X86::YMM1: case X86::YMM9: case X86::MM1:
166 return 1;
167 case X86::XMM2: case X86::XMM10:
168 case X86::YMM2: case X86::YMM10: case X86::MM2:
169 return 2;
170 case X86::XMM3: case X86::XMM11:
171 case X86::YMM3: case X86::YMM11: case X86::MM3:
172 return 3;
173 case X86::XMM4: case X86::XMM12:
174 case X86::YMM4: case X86::YMM12: case X86::MM4:
175 return 4;
176 case X86::XMM5: case X86::XMM13:
177 case X86::YMM5: case X86::YMM13: case X86::MM5:
178 return 5;
179 case X86::XMM6: case X86::XMM14:
180 case X86::YMM6: case X86::YMM14: case X86::MM6:
181 return 6;
182 case X86::XMM7: case X86::XMM15:
183 case X86::YMM7: case X86::YMM15: case X86::MM7:
184 return 7;
185
186 case X86::ES: return 0;
187 case X86::CS: return 1;
188 case X86::SS: return 2;
189 case X86::DS: return 3;
190 case X86::FS: return 4;
191 case X86::GS: return 5;
192
193 case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
194 case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
195 case X86::CR2: case X86::CR10: case X86::DR2: return 2;
196 case X86::CR3: case X86::CR11: case X86::DR3: return 3;
197 case X86::CR4: case X86::CR12: case X86::DR4: return 4;
198 case X86::CR5: case X86::CR13: case X86::DR5: return 5;
199 case X86::CR6: case X86::CR14: case X86::DR6: return 6;
200 case X86::CR7: case X86::CR15: case X86::DR7: return 7;
201
202 // Pseudo index registers are equivalent to a "none"
203 // scaled index (See Intel Manual 2A, table 2-3)
204 case X86::EIZ:
205 case X86::RIZ:
206 return 4;
207
208 default:
209 assert((int(RegNo) > 0) && "Unknown physical register!");
210 return 0;
211 }
212 }
213
214 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
215 // FIXME: TableGen these.
216 for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
217 int SEH = X86_MC::getX86RegNum(Reg);
218 switch (Reg) {
219 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
220 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
221 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
222 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
223 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
224 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
225 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
226 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
227 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
228 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
229 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
230 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
231 SEH += 8;
232 break;
233 }
234 MRI->mapLLVMRegToSEHReg(Reg, SEH);
235 }
236 }
237
109238 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
110239 StringRef FS) {
111240 std::string ArchFS = X86_MC::ParseX86Triple(TT);
149278 TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo);
150279 }
151280
152 static MCRegisterInfo *createX86MCRegisterInfo() {
281 static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) {
282 Triple TheTriple(TT);
283 unsigned RA = (TheTriple.getArch() == Triple::x86_64)
284 ? X86::RIP // Should have dwarf #16.
285 : X86::EIP; // Should have dwarf #8.
286
153287 MCRegisterInfo *X = new MCRegisterInfo();
154 InitX86MCRegisterInfo(X);
288 InitX86MCRegisterInfo(X, RA,
289 X86_MC::getDwarfRegFlavour(TT, false),
290 X86_MC::getDwarfRegFlavour(TT, true));
291 X86_MC::InitLLVM2SEHRegisterMapping(X);
155292 return X;
156293 }
157294
158 extern "C" void LLVMInitializeX86MCRegInfo() {
295 extern "C" void LLVMInitializeX86MCRegisterInfo() {
159296 TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
160297 TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
161298 }
1616 #include
1717
1818 namespace llvm {
19 class MCRegisterInfo;
1920 class MCSubtargetInfo;
2021 class Target;
2122 class StringRef;
2223
2324 extern Target TheX86_32Target, TheX86_64Target;
25
26 /// DWARFFlavour - Flavour of dwarf regnumbers
27 ///
28 namespace DWARFFlavour {
29 enum {
30 X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2
31 };
32 }
33
34 /// N86 namespace - Native X86 register numbers
35 ///
36 namespace N86 {
37 enum {
38 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
39 };
40 }
2441
2542 namespace X86_MC {
2643 std::string ParseX86Triple(StringRef TT);
3249
3350 void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model);
3451
35 /// createARMMCSubtargetInfo - Create a X86 MCSubtargetInfo instance.
52 unsigned getDwarfRegFlavour(StringRef TT, bool isEH);
53
54 unsigned getX86RegNum(unsigned RegNo);
55
56 void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI);
57
58 /// createX86MCSubtargetInfo - Create a X86 MCSubtargetInfo instance.
3659 /// This is exposed so Asm parser, etc. do not need to go through
3760 /// TargetRegistry.
3861 MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
9797 void emitMemModRMByte(const MachineInstr &MI,
9898 unsigned Op, unsigned RegOpcodeField,
9999 intptr_t PCAdj = 0);
100
101 unsigned getX86RegNum(unsigned RegNo) const;
102100 };
103101
104102 template
345343 MCE.emitWordLE(0);
346344 }
347345
348 template
349 unsigned Emitter::getX86RegNum(unsigned RegNo) const {
350 return X86RegisterInfo::getX86RegNum(RegNo);
351 }
352
353346 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
354347 unsigned RM) {
355348 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
359352 template
360353 void Emitter::emitRegModRMByte(unsigned ModRMReg,
361354 unsigned RegOpcodeFld){
362 MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
355 MCE.emitByte(ModRMByte(3, RegOpcodeFld, X86_MC::getX86RegNum(ModRMReg)));
363356 }
364357
365358 template
497490 // 2-7) and absolute references.
498491 unsigned BaseRegNo = -1U;
499492 if (BaseReg != 0 && BaseReg != X86::RIP)
500 BaseRegNo = getX86RegNum(BaseReg);
493 BaseRegNo = X86_MC::getX86RegNum(BaseReg);
501494
502495 if (// The SIB byte must be used if there is an index register.
503496 IndexReg.getReg() == 0 &&
573566 // Manual 2A, table 2-7. The displacement has already been output.
574567 unsigned IndexRegNo;
575568 if (IndexReg.getReg())
576 IndexRegNo = getX86RegNum(IndexReg.getReg());
569 IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg());
577570 else // Examples: [ESP+1*+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
578571 IndexRegNo = 4;
579572 emitSIBByte(SS, IndexRegNo, 5);
580573 } else {
581 unsigned BaseRegNo = getX86RegNum(BaseReg);
574 unsigned BaseRegNo = X86_MC::getX86RegNum(BaseReg);
582575 unsigned IndexRegNo;
583576 if (IndexReg.getReg())
584 IndexRegNo = getX86RegNum(IndexReg.getReg());
577 IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg());
585578 else
586579 IndexRegNo = 4; // For example [ESP+1*+4]
587580 emitSIBByte(SS, IndexRegNo, BaseRegNo);
808801 }
809802
810803 case X86II::AddRegFrm: {
811 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
804 MCE.emitByte(BaseOpcode +
805 X86_MC::getX86RegNum(MI.getOperand(CurOp++).getReg()));
812806
813807 if (CurOp == NumOps)
814808 break;
843837 case X86II::MRMDestReg: {
844838 MCE.emitByte(BaseOpcode);
845839 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
846 getX86RegNum(MI.getOperand(CurOp+1).getReg()));
840 X86_MC::getX86RegNum(MI.getOperand(CurOp+1).getReg()));
847841 CurOp += 2;
848842 if (CurOp != NumOps)
849843 emitConstant(MI.getOperand(CurOp++).getImm(),
853847 case X86II::MRMDestMem: {
854848 MCE.emitByte(BaseOpcode);
855849 emitMemModRMByte(MI, CurOp,
856 getX86RegNum(MI.getOperand(CurOp + X86::AddrNumOperands)
850 X86_MC::getX86RegNum(MI.getOperand(CurOp + X86::AddrNumOperands)
857851 .getReg()));
858852 CurOp += X86::AddrNumOperands + 1;
859853 if (CurOp != NumOps)
865859 case X86II::MRMSrcReg:
866860 MCE.emitByte(BaseOpcode);
867861 emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
868 getX86RegNum(MI.getOperand(CurOp).getReg()));
862 X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()));
869863 CurOp += 2;
870864 if (CurOp != NumOps)
871865 emitConstant(MI.getOperand(CurOp++).getImm(),
879873 X86II::getSizeOfImm(Desc->TSFlags) : 0;
880874
881875 MCE.emitByte(BaseOpcode);
882 emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
883 PCAdj);
876 emitMemModRMByte(MI, CurOp+1,
877 X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()),PCAdj);
884878 CurOp += AddrOperands + 1;
885879 if (CurOp != NumOps)
886880 emitConstant(MI.getOperand(CurOp++).getImm(),
967961 MCE.emitByte(BaseOpcode);
968962 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
969963 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
970 getX86RegNum(MI.getOperand(CurOp).getReg()));
964 X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()));
971965 ++CurOp;
972966 break;
973967
85518551 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
85528552 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
85538553
8554 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
8555 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
8554 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
8555 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
85568556
85578557 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
85588558
86568656
86578657 // This is storing the opcode for MOV32ri.
86588658 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
8659 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
8659 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
86608660 OutChains[0] = DAG.getStore(Root, dl,
86618661 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
86628662 Trmp, MachinePointerInfo(TrmpAddr),
4444 }
4545
4646 static unsigned GetX86RegNum(const MCOperand &MO) {
47 return X86RegisterInfo::getX86RegNum(MO.getReg());
47 return X86_MC::getX86RegNum(MO.getReg());
4848 }
4949
5050 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
5252
5353 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
5454 const TargetInstrInfo &tii)
55 : X86GenRegisterInfo(), TM(tm), TII(tii) {
55 : X86GenRegisterInfo(tm.getSubtarget().is64Bit()
56 ? X86::RIP : X86::EIP,
57 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false),
58 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true)),
59 TM(tm), TII(tii) {
60 X86_MC::InitLLVM2SEHRegisterMapping(this);
61
5662 // Cache some information.
5763 const X86Subtarget *Subtarget = &TM.getSubtarget();
5864 Is64Bit = Subtarget->is64Bit();
6773 StackPtr = X86::ESP;
6874 FramePtr = X86::EBP;
6975 }
70 }
71
72 static unsigned getFlavour(const X86Subtarget *Subtarget, bool isEH) {
73 if (!Subtarget->is64Bit()) {
74 if (Subtarget->isTargetDarwin()) {
75 if (isEH)
76 return DWARFFlavour::X86_32_DarwinEH;
77 else
78 return DWARFFlavour::X86_32_Generic;
79 } else if (Subtarget->isTargetCygMing()) {
80 // Unsupported by now, just quick fallback
81 return DWARFFlavour::X86_32_Generic;
82 } else {
83 return DWARFFlavour::X86_32_Generic;
84 }
85 }
86 return DWARFFlavour::X86_64;
87 }
88
89 /// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
90 /// specific numbering, used in debug info and exception tables.
91 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
92 const X86Subtarget *Subtarget = &TM.getSubtarget();
93 unsigned Flavour = getFlavour(Subtarget, isEH);
94
95 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
96 }
97
98 /// getLLVMRegNum - This function maps DWARF register numbers to LLVM register.
99 int X86RegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
100 const X86Subtarget *Subtarget = &TM.getSubtarget();
101 unsigned Flavour = getFlavour(Subtarget, isEH);
102
103 return X86GenRegisterInfo::getLLVMRegNumFull(DwarfRegNo, Flavour);
10476 }
10577
10678 /// getCompactUnwindRegNum - This function maps the register to the number for
12092
12193 int
12294 X86RegisterInfo::getSEHRegNum(unsigned i) const {
123 int reg = getX86RegNum(i);
95 int reg = X86_MC::getX86RegNum(i);
12496 switch (i) {
12597 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
12698 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
137109 reg += 8;
138110 }
139111 return reg;
140 }
141
142 /// getX86RegNum - This function maps LLVM register identifiers to their X86
143 /// specific numbering, which is used in various places encoding instructions.
144 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
145 switch(RegNo) {
146 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
147 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
148 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
149 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
150 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
151 return N86::ESP;
152 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
153 return N86::EBP;
154 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
155 return N86::ESI;
156 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
157 return N86::EDI;
158
159 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
160 return N86::EAX;
161 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
162 return N86::ECX;
163 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
164 return N86::EDX;
165 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
166 return N86::EBX;
167 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
168 return N86::ESP;
169 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
170 return N86::EBP;
171 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
172 return N86::ESI;
173 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
174 return N86::EDI;
175
176 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
177 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
178 return RegNo-X86::ST0;
179
180 case X86::XMM0: case X86::XMM8:
181 case X86::YMM0: case X86::YMM8: case X86::MM0:
182 return 0;
183 case X86::XMM1: case X86::XMM9:
184 case X86::YMM1: case X86::YMM9: case X86::MM1:
185 return 1;
186 case X86::XMM2: case X86::XMM10:
187 case X86::YMM2: case X86::YMM10: case X86::MM2:
188 return 2;
189 case X86::XMM3: case X86::XMM11:
190 case X86::YMM3: case X86::YMM11: case X86::MM3:
191 return 3;
192 case X86::XMM4: case X86::XMM12:
193 case X86::YMM4: case X86::YMM12: case X86::MM4:
194 return 4;
195 case X86::XMM5: case X86::XMM13:
196 case X86::YMM5: case X86::YMM13: case X86::MM5:
197 return 5;
198 case X86::XMM6: case X86::XMM14:
199 case X86::YMM6: case X86::YMM14: case X86::MM6:
200 return 6;
201 case X86::XMM7: case X86::XMM15:
202 case X86::YMM7: case X86::YMM15: case X86::MM7:
203 return 7;
204
205 case X86::ES: return 0;
206 case X86::CS: return 1;
207 case X86::SS: return 2;
208 case X86::DS: return 3;
209 case X86::FS: return 4;
210 case X86::GS: return 5;
211
212 case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
213 case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
214 case X86::CR2: case X86::CR10: case X86::DR2: return 2;
215 case X86::CR3: case X86::CR11: case X86::DR3: return 3;
216 case X86::CR4: case X86::CR12: case X86::DR4: return 4;
217 case X86::CR5: case X86::CR13: case X86::DR5: return 5;
218 case X86::CR6: case X86::CR14: case X86::DR6: return 6;
219 case X86::CR7: case X86::CR15: case X86::DR7: return 7;
220
221 // Pseudo index registers are equivalent to a "none"
222 // scaled index (See Intel Manual 2A, table 2-3)
223 case X86::EIZ:
224 case X86::RIZ:
225 return 4;
226
227 default:
228 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
229 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
230 return 0;
231 }
232112 }
233113
234114 const TargetRegisterClass *
738618 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
739619 MI.getOperand(i+3).setOffset(Offset);
740620 }
741 }
742
743 unsigned X86RegisterInfo::getRARegister() const {
744 return Is64Bit ? X86::RIP // Should have dwarf #16.
745 : X86::EIP; // Should have dwarf #8.
746621 }
747622
748623 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
2323 class TargetInstrInfo;
2424 class X86TargetMachine;
2525
26 /// N86 namespace - Native X86 register numbers
27 ///
28 namespace N86 {
29 enum {
30 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
31 };
32 }
33
34 /// DWARFFlavour - Flavour of dwarf regnumbers
35 ///
36 namespace DWARFFlavour {
37 enum {
38 X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2
39 };
40 }
41
4226 class X86RegisterInfo : public X86GenRegisterInfo {
4327 public:
4428 X86TargetMachine &TM;
7155 /// getX86RegNum - Returns the native X86 register number for the given LLVM
7256 /// register identifier.
7357 static unsigned getX86RegNum(unsigned RegNo);
74
75 /// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum
76 /// (created by TableGen) for target dependencies.
77 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
78 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
7958
8059 // FIXME: This should be tablegen'd like getDwarfRegNum is
8160 int getSEHRegNum(unsigned i) const;
135114 int SPAdj, RegScavenger *RS = NULL) const;
136115
137116 // Debug information queries.
138 unsigned getRARegister() const;
139117 unsigned getFrameRegister(const MachineFunction &MF) const;
140118 unsigned getStackRegister() const { return StackPtr; }
141119 // FIXME: Move to FrameInfok
3838 TargetRegistry::RegisterMCInstrInfo(TheXCoreTarget, createXCoreMCInstrInfo);
3939 }
4040
41 static MCRegisterInfo *createXCoreMCRegisterInfo(StringRef TT) {
42 MCRegisterInfo *X = new MCRegisterInfo();
43 InitXCoreMCRegisterInfo(X, XCore::LR);
44 return X;
45 }
46
47 extern "C" void LLVMInitializeXCoreMCRegisterInfo() {
48 TargetRegistry::RegisterMCRegInfo(TheXCoreTarget, createXCoreMCRegisterInfo);
49 }
50
4151 static MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU,
4252 StringRef FS) {
4353 MCSubtargetInfo *X = new MCSubtargetInfo();
3838 using namespace llvm;
3939
4040 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
41 : XCoreGenRegisterInfo(), TII(tii) {
41 : XCoreGenRegisterInfo(XCore::LR), TII(tii) {
4242 }
4343
4444 // helper functions
320320 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
321321 }
322322
323 int XCoreRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
324 return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
325 }
326
327 int XCoreRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
328 return XCoreGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
329 }
330
331323 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
332324 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
333325
334326 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
335327 }
336
337 unsigned XCoreRegisterInfo::getRARegister() const {
338 return XCore::LR;
339 }
5959 int SPAdj, RegScavenger *RS = NULL) const;
6060
6161 // Debug information queries.
62 unsigned getRARegister() const;
6362 unsigned getFrameRegister(const MachineFunction &MF) const;
6463
6564 //! Return the array of argument passing registers
7372
7473 //! Return whether to emit frame moves
7574 static bool needsFrameMoves(const MachineFunction &MF);
76
77 //! Get DWARF debugging register number
78 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
79 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
8075 };
8176
8277 } // end namespace llvm
308308 llvm::OwningPtr MAI(TheTarget->createMCAsmInfo(TripleName));
309309 assert(MAI && "Unable to create target asm info!");
310310
311 llvm::OwningPtr MRI(TheTarget->createMCRegInfo(TripleName));
312 assert(MRI && "Unable to create target register info!");
313
311314 // Package up features to be passed to target/subtarget
312315 std::string FeaturesStr;
313316
326329 }
327330
328331 const TargetAsmInfo *tai = new TargetAsmInfo(*TM);
329 MCContext Ctx(*MAI, tai);
332 MCContext Ctx(*MAI, *MRI, tai);
330333 if (SaveTempLabels)
331334 Ctx.setAllowTemporaryLabels(false);
332335
437440 llvm::InitializeAllTargets();
438441 llvm::InitializeAllMCAsmInfos();
439442 llvm::InitializeAllMCInstrInfos();
443 llvm::InitializeAllMCRegisterInfos();
440444 llvm::InitializeAllMCSubtargetInfos();
441445 llvm::InitializeAllAsmPrinters();
442446 llvm::InitializeAllAsmParsers();
3030 #include "llvm/Target/TargetOptions.h"
3131 #include "llvm/Target/TargetData.h"
3232 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
3334 #include "llvm/Target/TargetRegistry.h"
3435 #include "llvm/Target/TargetSelect.h"
3536 #include "llvm/Support/CommandLine.h"
7374 {
7475 InitializeAllTargets();
7576 InitializeAllMCAsmInfos();
77 InitializeAllMCRegisterInfos();
7678 InitializeAllMCSubtargetInfos();
7779 InitializeAllAsmPrinters();
7880 }
307309 passes.add(createVerifierPass());
308310
309311 // mark which symbols can not be internalized
310 MCContext Context(*_target->getMCAsmInfo(), NULL);
312 MCContext Context(*_target->getMCAsmInfo(), *_target->getRegisterInfo(),
313 NULL);
311314 Mangler mangler(Context, *_target->getTargetData());
312315 std::vector mustPreserveList;
313316 SmallPtrSet asmUsed;
3939 #include "llvm/MC/SubtargetFeature.h"
4040 #include "llvm/Target/TargetAsmParser.h"
4141 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetRegisterInfo.h"
4243 #include "llvm/Target/TargetRegistry.h"
4344 #include "llvm/Target/TargetSelect.h"
4445
661662
662663 bool LTOModule::ParseSymbols() {
663664 // Use mangler to add GlobalPrefix to names to match linker names.
664 MCContext Context(*_target->getMCAsmInfo(), NULL);
665 MCContext Context(*_target->getMCAsmInfo(), *_target->getRegisterInfo(),
666 NULL);
665667 Mangler mangler(Context, *_target->getTargetData());
666668
667669 // add functions
8888
8989 OS << "} // End llvm namespace \n";
9090 OS << "#endif // GET_REGINFO_ENUM\n\n";
91 }
92
93 void
94 RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
95 const std::vector &Regs,
96 bool isCtor) {
97
98 // Collect all information about dwarf register numbers
99 typedef std::map, LessRecord> DwarfRegNumsMapTy;
100 DwarfRegNumsMapTy DwarfRegNums;
101
102 // First, just pull all provided information to the map
103 unsigned maxLength = 0;
104 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
105 Record *Reg = Regs[i]->TheDef;
106 std::vector RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
107 maxLength = std::max((size_t)maxLength, RegNums.size());
108 if (DwarfRegNums.count(Reg))
109 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
110 << "specified multiple times\n";
111 DwarfRegNums[Reg] = RegNums;
112 }
113
114 if (!maxLength)
115 return;
116
117 // Now we know maximal length of number list. Append -1's, where needed
118 for (DwarfRegNumsMapTy::iterator
119 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
120 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
121 I->second.push_back(-1);
122
123 // Emit reverse information about the dwarf register numbers.
124 for (unsigned j = 0; j < 2; ++j) {
125 OS << " switch (";
126 if (j == 0)
127 OS << "DwarfFlavour";
128 else
129 OS << "EHFlavour";
130 OS << ") {\n"
131 << " default:\n"
132 << " assert(0 && \"Unknown DWARF flavour\");\n"
133 << " break;\n";
134
135 for (unsigned i = 0, e = maxLength; i != e; ++i) {
136 OS << " case " << i << ":\n";
137 for (DwarfRegNumsMapTy::iterator
138 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
139 int DwarfRegNo = I->second[i];
140 if (DwarfRegNo < 0)
141 continue;
142 OS << " ";
143 if (!isCtor)
144 OS << "RI->";
145 OS << "mapDwarfRegToLLVMReg(" << DwarfRegNo << ", "
146 << getQualifiedName(I->first) << ", ";
147 if (j == 0)
148 OS << "false";
149 else
150 OS << "true";
151 OS << " );\n";
152 }
153 OS << " break;\n";
154 }
155 OS << " }\n";
156 }
157
158 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
159 Record *Reg = Regs[i]->TheDef;
160 const RecordVal *V = Reg->getValue("DwarfAlias");
161 if (!V || !V->getValue())
162 continue;
163
164 DefInit *DI = dynamic_cast(V->getValue());
165 Record *Alias = DI->getDef();
166 DwarfRegNums[Reg] = DwarfRegNums[Alias];
167 }
168
169 // Emit information about the dwarf register numbers.
170 for (unsigned j = 0; j < 2; ++j) {
171 OS << " switch (";
172 if (j == 0)
173 OS << "DwarfFlavour";
174 else
175 OS << "EHFlavour";
176 OS << ") {\n"
177 << " default:\n"
178 << " assert(0 && \"Unknown DWARF flavour\");\n"
179 << " break;\n";
180
181 for (unsigned i = 0, e = maxLength; i != e; ++i) {
182 OS << " case " << i << ":\n";
183 // Sort by name to get a stable order.
184 for (DwarfRegNumsMapTy::iterator
185 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
186 int RegNo = I->second[i];
187 OS << " ";
188 if (!isCtor)
189 OS << "RI->";
190 OS << "mapLLVMRegToDwarfReg(" << getQualifiedName(I->first) << ", "
191 << RegNo << ", ";
192 if (j == 0)
193 OS << "false";
194 else
195 OS << "true";
196 OS << " );\n";
197 }
198 OS << " break;\n";
199 }
200 OS << " }\n";
201 }
91202 }
92203
93204 //
187298
188299 // MCRegisterInfo initialization routine.
189300 OS << "static inline void Init" << TargetName
190 << "MCRegisterInfo(MCRegisterInfo *RI) {\n";
301 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
302 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
191303 OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
192 << Regs.size()+1 << ");\n}\n\n";
304 << Regs.size()+1 << ", RA);\n\n";
305
306 EmitRegMapping(OS, Regs, false);
307
308 OS << "}\n\n";
309
193310
194311 OS << "} // End llvm namespace \n";
195312 OS << "#endif // GET_REGINFO_MC_DESC\n\n";
212329 OS << "namespace llvm {\n\n";
213330
214331 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
215 << " explicit " << ClassName << "();\n"
216 << " virtual int getDwarfRegNumFull(unsigned RegNum, "
217 << "unsigned Flavour) const;\n"
218 << " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, "
219 << "unsigned Flavour) const;\n"
220 << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
332 << " explicit " << ClassName
333 << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
221334 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
222335 << " { return false; }\n"
223336 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
661774 OS << "extern MCRegisterDesc " << TargetName << "RegDesc[];\n";
662775
663776 OS << ClassName << "::" << ClassName
664 << "()\n"
777 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
665778 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
666779 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
667780 << " " << TargetName << "SubRegIndexTable) {\n"
668781 << " InitMCRegisterInfo(" << TargetName << "RegDesc, "
669 << Regs.size()+1 << ");\n"
670 << "}\n\n";
671
672 // Collect all information about dwarf register numbers
673 typedef std::map, LessRecord> DwarfRegNumsMapTy;
674 DwarfRegNumsMapTy DwarfRegNums;
675
676 // First, just pull all provided information to the map
677 unsigned maxLength = 0;
678 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
679 Record *Reg = Regs[i]->TheDef;
680 std::vector RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
681 maxLength = std::max((size_t)maxLength, RegNums.size());
682 if (DwarfRegNums.count(Reg))
683 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
684 << "specified multiple times\n";
685 DwarfRegNums[Reg] = RegNums;
686 }
687
688 // Now we know maximal length of number list. Append -1's, where needed
689 for (DwarfRegNumsMapTy::iterator
690 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
691 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
692 I->second.push_back(-1);
693
694 // Emit reverse information about the dwarf register numbers.
695 OS << "int " << ClassName << "::getLLVMRegNumFull(unsigned DwarfRegNum, "
696 << "unsigned Flavour) const {\n"
697 << " switch (Flavour) {\n"
698 << " default:\n"
699 << " assert(0 && \"Unknown DWARF flavour\");\n"
700 << " return -1;\n";
701
702 for (unsigned i = 0, e = maxLength; i != e; ++i) {
703 OS << " case " << i << ":\n"
704 << " switch (DwarfRegNum) {\n"
705 << " default:\n"
706 << " assert(0 && \"Invalid DwarfRegNum\");\n"
707 << " return -1;\n";
708
709 for (DwarfRegNumsMapTy::iterator
710 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
711 int DwarfRegNo = I->second[i];
712 if (DwarfRegNo >= 0)
713 OS << " case " << DwarfRegNo << ":\n"
714 << " return " << getQualifiedName(I->first) << ";\n";
715 }
716 OS << " };\n";
717 }
718
719 OS << " };\n}\n\n";
720
721 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
722 Record *Reg = Regs[i]->TheDef;
723 const RecordVal *V = Reg->getValue("DwarfAlias");
724 if (!V || !V->getValue())
725 continue;
726
727 DefInit *DI = dynamic_cast(V->getValue());
728 Record *Alias = DI->getDef();
729 DwarfRegNums[Reg] = DwarfRegNums[Alias];
730 }
731
732 // Emit information about the dwarf register numbers.
733 OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
734 << "unsigned Flavour) const {\n"
735 << " switch (Flavour) {\n"
736 << " default:\n"
737 << " assert(0 && \"Unknown DWARF flavour\");\n"
738 << " return -1;\n";
739
740 for (unsigned i = 0, e = maxLength; i != e; ++i) {
741 OS << " case " << i << ":\n"
742 << " switch (RegNum) {\n"
743 << " default:\n"
744 << " assert(0 && \"Invalid RegNum\");\n"
745 << " return -1;\n";
746
747 // Sort by name to get a stable order.
748
749
750 for (DwarfRegNumsMapTy::iterator
751 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
752 int RegNo = I->second[i];
753 OS << " case " << getQualifiedName(I->first) << ":\n"
754 << " return " << RegNo << ";\n";
755 }
756 OS << " };\n";
757 }
758
759 OS << " };\n}\n\n";
782 << Regs.size()+1 << ", RA);\n\n";
783
784 EmitRegMapping(OS, Regs, true);
785
786 OS << "}\n\n";
760787
761788 OS << "} // End llvm namespace \n";
762789 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
1616 #define REGISTER_INFO_EMITTER_H
1717
1818 #include "TableGenBackend.h"
19 #include
1920
2021 namespace llvm {
2122
2223 class CodeGenRegBank;
24 struct CodeGenRegister;
2325 class CodeGenTarget;
2426
2527 class RegisterInfoEmitter : public TableGenBackend {
4345
4446 // run - Output the register file description.
4547 void run(raw_ostream &o);
48
49 private:
50 void EmitRegMapping(raw_ostream &o,
51 const std::vector &Regs, bool isCtor);
4652 };
4753
4854 } // End llvm namespace