llvm.org GIT mirror llvm / 0de8d78
Do not ASSERTZEXT for i16 result of bitcast from f16 operand Summary: During legalization if i16, do not ASSERTZEXT the result of FP_TO_FP16. Directly return an FP_TO_FP16 node with return type as the promote-to-type of i16. This patch also removes extraneous length check. This legalization should be valid even if integer and float types are of different lengths. This patch breaks a hard-float test for fp16 args. The test is changed to allow a vmov to zero-out the top bits, and also ensure that the return value is in an FP register. Reviewers: ab, jmolloy Subscribers: srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D15438 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@257184 91177308-0d34-0410-b5e6-96231b3b80d8 Pirama Arumuga Nainar 4 years ago
3 changed file(s) with 34 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
261261 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
262262 case TargetLowering::TypePromoteFloat: {
263263 // Convert the promoted float by hand.
264 if (NOutVT.bitsEq(NInVT)) {
265 SDValue PromotedOp = GetPromotedFloat(InOp);
266 SDValue Trunc = DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp);
267 return DAG.getNode(ISD::AssertZext, dl, NOutVT, Trunc,
268 DAG.getValueType(OutVT));
269 }
264 SDValue PromotedOp = GetPromotedFloat(InOp);
265 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp);
270266 break;
271267 }
272268 case TargetLowering::TypeExpandInteger:
3131 ; HARD: vcvtb.f32.f16 {{s[0-9]+}}, s1
3232 ; HARD: vcvtb.f32.f16 {{s[0-9]+}}, s0
3333 ; HARD: vadd.f32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
34 ; HARD: vcvtb.f16.f32 s0, {{s[0-9]+}}
35 ; HARD-NOT: vmov
36 ; HARD-NOT: uxth
34 ; HARD: vcvtb.f16.f32 [[SREG:s[0-9]+]], {{s[0-9]+}}
35 ; HARD-NEXT: vmov [[REG0:r[0-9]+]], [[SREG]]
36 ; HARD-NEXT: uxth [[REG1:r[0-9]+]], [[REG0]]
37 ; HARD-NEXT: vmov s0, [[REG1]]
3738
3839 ; CHECK: bx lr
3940 }
0 ; RUN: llc -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK
1
2 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3 target triple = "armv7a--none-eabi"
4
5 ; CHECK-LABEL: test_vec3:
6 ; CHECK: vcvtb.f32.f16
7 ; CHECK: vcvt.f32.s32
8 ; CHECK: vadd.f32
9 ; CHECK-NEXT: vcvtb.f16.f32 [[SREG:s[0-9]+]], {{.*}}
10 ; CHECK-NEXT: vmov [[RREG1:r[0-9]+]], [[SREG]]
11 ; CHECK-NEXT: uxth [[RREG2:r[0-9]+]], [[RREG1]]
12 ; CHECK-NEXT: pkhbt [[RREG3:r[0-9]+]], [[RREG1]], [[RREG1]], lsl #16
13 ; CHECK-DAG: strh [[RREG1]], [r0, #4]
14 ; CHECK-DAG: vmov [[DREG:d[0-9]+]], [[RREG3]], [[RREG2]]
15 ; CHECK-DAG: vst1.32 {[[DREG]][0]}, [r0:32]
16 ; CHECK-NEXT: bx lr
17 define void @test_vec3(<3 x half>* %arr, i32 %i) #0 {
18 %H = sitofp i32 %i to half
19 %S = fadd half %H, 0xH4A00
20 %1 = insertelement <3 x half> undef, half %S, i32 0
21 %2 = insertelement <3 x half> %1, half %S, i32 1
22 %3 = insertelement <3 x half> %2, half %S, i32 2
23 store <3 x half> %3, <3 x half>* %arr, align 8
24 ret void
25 }
26
27 attributes #0 = { nounwind }