llvm.org GIT mirror llvm / 0d80090
Merge 98212 from mainline. add support, testcases, and dox for the new GHC calling convention. Patch by David Terei! git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_27@98307 91177308-0d34-0410-b5e6-96231b3b80d8 Tanya Lattner 10 years ago
9 changed file(s) with 220 addition(s) and 18 deletion(s). Raw diff Collapse all Expand all
16771677 supported on x86/x86-64 and PowerPC. It is performed if:

16781678
16791679
1680
  • Caller and callee have the calling convention fastcc.
  • 1680
  • Caller and callee have the calling convention fastcc or
  • 1681 cc 10 (GHC call convention).
    16811682
    16821683
  • The call is a tail call - in tail position (ret immediately follows call
  • 16831684 and ret uses value of call or is void).
    690690 target, without having to conform to an externally specified ABI
    691691 (Application Binary Interface).
    692692 Tail calls can only be optimized
    693 when this convention is used. This calling convention does not
    694 support varargs and requires the prototype of all callees to exactly match
    695 the prototype of the function definition.
    693 when this or the GHC convention is used. This calling convention
    694 does not support varargs and requires the prototype of all callees to
    695 exactly match the prototype of the function definition.
    696696
    697697
    "coldcc" - The cold calling convention:
    698698
    This calling convention attempts to make code in the caller as efficient
    701701 not break any live ranges in the caller side. This calling convention
    702702 does not support varargs and requires the prototype of all callees to
    703703 exactly match the prototype of the function definition.
    704
    705
    "cc 10" - GHC convention:
    706
    This calling convention has been implemented specifically for use by the
    707 Glasgow Haskell Compiler (GHC).
    708 It passes everything in registers, going to extremes to achieve this by
    709 disabling callee save registers. This calling convention should not be
    710 used lightly but only for specific situations such as an alternative to
    711 the register pinning performance technique often used when
    712 implementing functional programming languages.At the moment only X86
    713 supports this convention and it has the following limitations:
    714
    715
  • On X86-32 only supports up to 4 bit type parameters. No
  • 716 floating point types are supported.
    717
  • On X86-64 only supports up to 10 bit type parameters and
  • 718 6 floating point parameters.
    719
    720 This calling convention supports
    721 tail call optimization but
    722 requires both the caller and callee are using it.
    723
    704724
    705725
    "cc <n>" - Numbered convention:
    706726
    Any calling convention may be specified by number, allowing
    4343 // call does not break any live ranges in the caller side.
    4444 Cold = 9,
    4545
    46 // GHC - Calling convention used by the Glasgow Haskell Compiler (GHC).
    47 GHC = 10,
    48
    4649 // Target - This is the start of the target-specific calling conventions,
    4750 // e.g. fastcall and thiscall on X86.
    4851 FirstTargetCC = 64,
    220220 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 8>>
    221221 ]>;
    222222
    223 def CC_X86_64_GHC : CallingConv<[
    224 // Promote i8/i16/i32 arguments to i64.
    225 CCIfType<[i8, i16, i32], CCPromoteToType>,
    226
    227 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
    228 CCIfType<[i64],
    229 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
    230
    231 // Pass in STG registers: F1, F2, F3, F4, D1, D2
    232 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
    233 CCIfSubtarget<"hasSSE1()",
    234 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>
    235 ]>;
    236
    223237 //===----------------------------------------------------------------------===//
    224238 // X86 C Calling Convention
    225239 //===----------------------------------------------------------------------===//
    319333 // Otherwise, same as everything else.
    320334 CCDelegateTo
    321335 ]>;
    336
    337 def CC_X86_32_GHC : CallingConv<[
    338 // Promote i8/i16 arguments to i32.
    339 CCIfType<[i8, i16], CCPromoteToType>,
    340
    341 // Pass in STG registers: Base, Sp, Hp, R1
    342 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>>
    343 ]>;
    171171 CCAssignFn *X86FastISel::CCAssignFnForCall(CallingConv::ID CC,
    172172 bool isTaillCall) {
    173173 if (Subtarget->is64Bit()) {
    174 if (Subtarget->isTargetWin64())
    174 if (CC == CallingConv::GHC)
    175 return CC_X86_64_GHC;
    176 else if (Subtarget->isTargetWin64())
    175177 return CC_X86_Win64_C;
    176178 else
    177179 return CC_X86_64_C;
    181183 return CC_X86_32_FastCall;
    182184 else if (CC == CallingConv::Fast)
    183185 return CC_X86_32_FastCC;
    186 else if (CC == CallingConv::GHC)
    187 return CC_X86_32_GHC;
    184188 else
    185189 return CC_X86_32_C;
    186190 }
    13771377 return !Subtarget->is64Bit();
    13781378 case CallingConv::Fast:
    13791379 return GuaranteedTailCallOpt;
    1380 case CallingConv::GHC:
    1381 return GuaranteedTailCallOpt;
    13801382 }
    13811383 }
    13821384
    13841386 /// given CallingConvention value.
    13851387 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
    13861388 if (Subtarget->is64Bit()) {
    1387 if (Subtarget->isTargetWin64())
    1389 if (CC == CallingConv::GHC)
    1390 return CC_X86_64_GHC;
    1391 else if (Subtarget->isTargetWin64())
    13881392 return CC_X86_Win64_C;
    13891393 else
    13901394 return CC_X86_64_C;
    13941398 return CC_X86_32_FastCall;
    13951399 else if (CC == CallingConv::Fast)
    13961400 return CC_X86_32_FastCC;
    1401 else if (CC == CallingConv::GHC)
    1402 return CC_X86_32_GHC;
    13971403 else
    13981404 return CC_X86_32_C;
    13991405 }
    14111417 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
    14121418 }
    14131419
    1420 /// IsTailCallConvention - Return true if the calling convention is one that
    1421 /// supports tail call optimization.
    1422 static bool IsTailCallConvention(CallingConv::ID CC) {
    1423 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
    1424 }
    1425
    14141426 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
    14151427 /// a tailcall target by changing its ABI.
    14161428 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
    1417 return GuaranteedTailCallOpt && CC == CallingConv::Fast;
    1429 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
    14181430 }
    14191431
    14201432 SDValue
    14781490 bool Is64Bit = Subtarget->is64Bit();
    14791491 bool IsWin64 = Subtarget->isTargetWin64();
    14801492
    1481 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
    1482 "Var args not supported with calling convention fastcc");
    1493 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
    1494 "Var args not supported with calling convention fastcc or ghc");
    14831495
    14841496 // Assign locations to all of the incoming arguments.
    14851497 SmallVector ArgLocs;
    16821694 } else {
    16831695 BytesToPopOnReturn = 0; // Callee pops nothing.
    16841696 // If this is an sret function, the return should pop the hidden pointer.
    1685 if (!Is64Bit && CallConv != CallingConv::Fast && ArgsAreStructReturn(Ins))
    1697 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
    16861698 BytesToPopOnReturn = 4;
    16871699 }
    16881700
    17781790 ++NumTailCalls;
    17791791 }
    17801792
    1781 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
    1782 "Var args not supported with calling convention fastcc");
    1793 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
    1794 "Var args not supported with calling convention fastcc or ghc");
    17831795
    17841796 // Analyze operands of the call, assigning locations to each operand.
    17851797 SmallVector ArgLocs;
    17931805 // This is a sibcall. The memory operands are available in caller's
    17941806 // own caller's stack.
    17951807 NumBytes = 0;
    1796 else if (GuaranteedTailCallOpt && CallConv == CallingConv::Fast)
    1808 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
    17971809 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
    17981810
    17991811 int FPDiff = 0;
    21492161 unsigned NumBytesForCalleeToPush;
    21502162 if (IsCalleePop(isVarArg, CallConv))
    21512163 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
    2152 else if (!Is64Bit && CallConv != CallingConv::Fast && IsStructRet)
    2164 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
    21532165 // If this is a call to a struct-return function, the callee
    21542166 // pops the hidden struct pointer, so we have to push it back.
    21552167 // This is common for Darwin/X86, Linux & Mingw32 targets.
    22872299 const SmallVectorImpl &Outs,
    22882300 const SmallVectorImpl &Ins,
    22892301 SelectionDAG& DAG) const {
    2290 if (CalleeCC != CallingConv::Fast &&
    2302 if (!IsTailCallConvention(CalleeCC) &&
    22912303 CalleeCC != CallingConv::C)
    22922304 return false;
    22932305
    22942306 // If -tailcallopt is specified, make fastcc functions tail-callable.
    22952307 const Function *CallerF = DAG.getMachineFunction().getFunction();
    22962308 if (GuaranteedTailCallOpt) {
    2297 if (CalleeCC == CallingConv::Fast &&
    2309 if (IsTailCallConvention(CalleeCC) &&
    22982310 CallerF->getCallingConv() == CalleeCC)
    22992311 return true;
    23002312 return false;
    293293 const unsigned *
    294294 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
    295295 bool callsEHReturn = false;
    296 bool ghcCall = false;
    296297
    297298 if (MF) {
    298299 const MachineFrameInfo *MFI = MF->getFrameInfo();
    299300 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
    300301 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
    301 }
    302 const Function *F = MF->getFunction();
    303 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
    304 }
    305
    306 static const unsigned GhcCalleeSavedRegs[] = {
    307 0
    308 };
    302309
    303310 static const unsigned CalleeSavedRegs32Bit[] = {
    304311 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
    325332 X86::XMM14, X86::XMM15, 0
    326333 };
    327334
    328 if (Is64Bit) {
    335 if (ghcCall) {
    336 return GhcCalleeSavedRegs;
    337 } else if (Is64Bit) {
    329338 if (IsWin64)
    330339 return CalleeSavedRegsWin64;
    331340 else
    0 ; RUN: llc < %s -tailcallopt -mtriple=i686-linux-gnu | FileCheck %s
    1
    2 ; Test the GHC call convention works (x86-32)
    3
    4 @base = external global i32 ; assigned to register: EBX
    5 @sp = external global i32 ; assigned to register: EBP
    6 @hp = external global i32 ; assigned to register: EDI
    7 @r1 = external global i32 ; assigned to register: ESI
    8
    9 define void @zap(i32 %a, i32 %b) nounwind {
    10 entry:
    11 ; CHECK: movl {{[0-9]*}}(%esp), %ebx
    12 ; CHECK-NEXT: movl {{[0-9]*}}(%esp), %ebp
    13 ; CHECK-NEXT: call addtwo
    14 %0 = call cc 10 i32 @addtwo(i32 %a, i32 %b)
    15 ; CHECK: call foo
    16 call void @foo() nounwind
    17 ret void
    18 }
    19
    20 define cc 10 i32 @addtwo(i32 %x, i32 %y) nounwind {
    21 entry:
    22 ; CHECK: leal (%ebx,%ebp), %eax
    23 %0 = add i32 %x, %y
    24 ; CHECK-NEXT: ret
    25 ret i32 %0
    26 }
    27
    28 define cc 10 void @foo() nounwind {
    29 entry:
    30 ; CHECK: movl base, %ebx
    31 ; CHECK-NEXT: movl sp, %ebp
    32 ; CHECK-NEXT: movl hp, %edi
    33 ; CHECK-NEXT: movl r1, %esi
    34 %0 = load i32* @r1
    35 %1 = load i32* @hp
    36 %2 = load i32* @sp
    37 %3 = load i32* @base
    38 ; CHECK: jmp bar
    39 tail call cc 10 void @bar( i32 %3, i32 %2, i32 %1, i32 %0 ) nounwind
    40 ret void
    41 }
    42
    43 declare cc 10 void @bar(i32, i32, i32, i32)
    44
    0 ; RUN: llc < %s -tailcallopt -mtriple=x86_64-linux-gnu | FileCheck %s
    1
    2 ; Check the GHC call convention works (x86-64)
    3
    4 @base = external global i64 ; assigned to register: R13
    5 @sp = external global i64 ; assigned to register: RBP
    6 @hp = external global i64 ; assigned to register: R12
    7 @r1 = external global i64 ; assigned to register: RBX
    8 @r2 = external global i64 ; assigned to register: R14
    9 @r3 = external global i64 ; assigned to register: RSI
    10 @r4 = external global i64 ; assigned to register: RDI
    11 @r5 = external global i64 ; assigned to register: R8
    12 @r6 = external global i64 ; assigned to register: R9
    13 @splim = external global i64 ; assigned to register: R15
    14
    15 @f1 = external global float ; assigned to register: XMM1
    16 @f2 = external global float ; assigned to register: XMM2
    17 @f3 = external global float ; assigned to register: XMM3
    18 @f4 = external global float ; assigned to register: XMM4
    19 @d1 = external global double ; assigned to register: XMM5
    20 @d2 = external global double ; assigned to register: XMM6
    21
    22 define void @zap(i64 %a, i64 %b) nounwind {
    23 entry:
    24 ; CHECK: movq %rdi, %r13
    25 ; CHECK-NEXT: movq %rsi, %rbp
    26 ; CHECK-NEXT: callq addtwo
    27 %0 = call cc 10 i64 @addtwo(i64 %a, i64 %b)
    28 ; CHECK: callq foo
    29 call void @foo() nounwind
    30 ret void
    31 }
    32
    33 define cc 10 i64 @addtwo(i64 %x, i64 %y) nounwind {
    34 entry:
    35 ; CHECK: leaq (%r13,%rbp), %rax
    36 %0 = add i64 %x, %y
    37 ; CHECK-NEXT: ret
    38 ret i64 %0
    39 }
    40
    41 define cc 10 void @foo() nounwind {
    42 entry:
    43 ; CHECK: movq base(%rip), %r13
    44 ; CHECK-NEXT: movq sp(%rip), %rbp
    45 ; CHECK-NEXT: movq hp(%rip), %r12
    46 ; CHECK-NEXT: movq r1(%rip), %rbx
    47 ; CHECK-NEXT: movq r2(%rip), %r14
    48 ; CHECK-NEXT: movq r3(%rip), %rsi
    49 ; CHECK-NEXT: movq r4(%rip), %rdi
    50 ; CHECK-NEXT: movq r5(%rip), %r8
    51 ; CHECK-NEXT: movq r6(%rip), %r9
    52 ; CHECK-NEXT: movq splim(%rip), %r15
    53 ; CHECK-NEXT: movss f1(%rip), %xmm1
    54 ; CHECK-NEXT: movss f2(%rip), %xmm2
    55 ; CHECK-NEXT: movss f3(%rip), %xmm3
    56 ; CHECK-NEXT: movss f4(%rip), %xmm4
    57 ; CHECK-NEXT: movsd d1(%rip), %xmm5
    58 ; CHECK-NEXT: movsd d2(%rip), %xmm6
    59 %0 = load double* @d2
    60 %1 = load double* @d1
    61 %2 = load float* @f4
    62 %3 = load float* @f3
    63 %4 = load float* @f2
    64 %5 = load float* @f1
    65 %6 = load i64* @splim
    66 %7 = load i64* @r6
    67 %8 = load i64* @r5
    68 %9 = load i64* @r4
    69 %10 = load i64* @r3
    70 %11 = load i64* @r2
    71 %12 = load i64* @r1
    72 %13 = load i64* @hp
    73 %14 = load i64* @sp
    74 %15 = load i64* @base
    75 ; CHECK: jmp bar
    76 tail call cc 10 void @bar( i64 %15, i64 %14, i64 %13, i64 %12, i64 %11,
    77 i64 %10, i64 %9, i64 %8, i64 %7, i64 %6,
    78 float %5, float %4, float %3, float %2, double %1,
    79 double %0 ) nounwind
    80 ret void
    81 }
    82
    83 declare cc 10 void @bar(i64, i64, i64, i64, i64, i64, i64, i64, i64, i64,
    84 float, float, float, float, double, double)
    85