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[ARM] Add support for unpredictable MVN instructions. This fixes bugzilla 33011 https://bugs.llvm.org/show_bug.cgi?id=33011 Defines bits {19-16} as zero or unpredictable as specified by the ARM ARM in sections A8.8.116 and A8.8.117. It fixes also the usage of PC register as destination register for MVN register-shifted register version as specified in A8.8.117. Differential Revision: https://reviews.llvm.org/D41905 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323954 91177308-0d34-0410-b5e6-96231b3b80d8 Yvan Roux 2 years ago
3 changed file(s) with 54 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
39113911 let Inst{11-4} = 0b00000000;
39123912 let Inst{15-12} = Rd;
39133913 let Inst{3-0} = Rm;
3914
3915 let Unpredictable{19-16} = 0b1111;
39143916 }
39153917 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
39163918 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
39243926 let Inst{11-5} = shift{11-5};
39253927 let Inst{4} = 0;
39263928 let Inst{3-0} = shift{3-0};
3927 }
3928 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3929
3930 let Unpredictable{19-16} = 0b1111;
3931 }
3932 def MVNsr : AsI1<0b1111, (outs GPRnopc:$Rd), (ins so_reg_reg:$shift),
39293933 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3930 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3934 [(set GPRnopc:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
39313935 Sched<[WriteALU]> {
39323936 bits<4> Rd;
39333937 bits<12> shift;
39393943 let Inst{6-5} = shift{6-5};
39403944 let Inst{4} = 1;
39413945 let Inst{3-0} = shift{3-0};
3946
3947 let Unpredictable{19-16} = 0b1111;
39423948 }
39433949 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
39443950 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
741741 adds r0
742742 @ CHECK-ERRORS: error: too few operands for instruction
743743 @ CHECK-ERRORS: error: too few operands for instruction
744
745 @ Using pc for MVN
746 mvn pc, r6, lsl r7
747 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
748 @ CHECK-ERRORS: note: operand must be a register in range [r0, r14]
749 @ CHECK-ERRORS: mvn pc, r6, lsl r7
750 @ CHECK-ERRORS: ^
0 # RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s
1
2 # A8.8.116 MVN (register)
3 # MVN(S) , {, }
4 #
5 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
6 # -------------------------------------------------------------------------------------------------
7 # | cond | 0 0| 0| 1 1 1 1| S|(0)(0)(0)(0)| Rd | imm5 |type | 0| Rm |
8 # -------------------------------------------------------------------------------------------------
9
10 # MVN r2, r3 ; with bit 16 == 1 => Unpredictable
11 # CHECK: potentially undefined
12 # CHECK: 0x03 0x20 0xe1 0xe1
13 0x03 0x20 0xe1 0xe1
14
15 # A8.8.117 MVN (register-shifted register)
16 # MVN(S) , ,
17 #
18 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 # -------------------------------------------------------------------------------------------------
20 # | cond | 0 0| 0| 1 1 1 1| S|(0)(0)(0)(0)| Rd | Rs | 0|type | 1| Rm |
21 # -------------------------------------------------------------------------------------------------
22 # if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
23
24 # MVN r5, pc, lsl r7
25 # CHECK: potentially undefined
26 # CHECK: 0x1f 0x57 0xe0 0xe1
27 0x1f 0x57 0xe0 0xe1
28
29 # MVN pc, r6, lsl r7
30 # CHECK: potentially undefined
31 # CHECK: 0x16 0xf7 0xe0 0xe1
32 0x16 0xf7 0xe0 0xe1
33
34 # MVN r5, r6, lsl pc
35 # CHECK: potentially undefined
36 # CHECK: 0x16 0x5f 0xe0 0xe1
37 0x16 0x5f 0xe0 0xe1