llvm.org GIT mirror llvm / 0cf7d29
[ARM]Decoding MSR with unpredictable destination register causes an assert This patch handling: Enable parsing of raw encodings of system registers . Allows UNPREDICTABLE sysregs to be decoded to a raw number in the same way that disasslib does, rather than llvm crashing. Disassemble msr/mrs with unpredictable sysregs as SoftFail. Fix regression due to SoftFailing some encodings. Patch by Chris Ryder Differential revision:https://reviews.llvm.org/D43374 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326803 91177308-0d34-0410-b5e6-96231b3b80d8 Simi Pallipurath 2 years ago
5 changed file(s) with 27 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
42374237 MCAsmParser &Parser = getParser();
42384238 SMLoc S = Parser.getTok().getLoc();
42394239 const AsmToken &Tok = Parser.getTok();
4240
4241 if (Tok.is(AsmToken::Integer)) {
4242 int64_t Val = Tok.getIntVal();
4243 if (Val > 255 || Val < 0) {
4244 return MatchOperand_NoMatch;
4245 }
4246 unsigned SYSmvalue = Val & 0xFF;
4247 Parser.Lex();
4248 Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
4249 return MatchOperand_Success;
4250 }
4251
42404252 if (!Tok.is(AsmToken::Identifier))
42414253 return MatchOperand_NoMatch;
42424254 StringRef Mask = Tok.getString();
41484148 case 0x8a: // msplim_ns
41494149 case 0x8b: // psplim_ns
41504150 case 0x91: // basepri_ns
4151 case 0x92: // basepri_max_ns
41524151 case 0x93: // faultmask_ns
41534152 if (!(FeatureBits[ARM::HasV8MMainlineOps]))
41544153 return MCDisassembler::Fail;
41644163 return MCDisassembler::Fail;
41654164 break;
41664165 default:
4167 return MCDisassembler::Fail;
4166 // Architecturally defined as unpredictable
4167 S = MCDisassembler::SoftFail;
4168 break;
41684169 }
41694170
41704171 if (Inst.getOpcode() == ARM::t2MSR_M) {
824824 return;
825825 }
826826
827 llvm_unreachable("Unexpected mask value!");
827 O << SYSm;
828
828829 return;
829830 }
830831
224224 // CHECK-MAINLINE: msr faultmask_ns, lr @ encoding: [0x8e,0xf3,0x93,0x88]
225225 // UNDEF-BASELINE: error: invalid operand for instruction
226226
227 // Unpredictable SYSm's
228 MRS r8, 146
229 // CHECK: mrs r8, 146 @ encoding: [0xef,0xf3,0x92,0x88]
230 MSR 146, r8
231 // CHECK: msr 146, r8 @ encoding: [0x88,0xf3,0x92,0x80]
232
227233 // Invalid operand tests
228234 // UNDEF: error: too many operands for instruction
229235 // UNDEF: sg #0
None # RUN: not llvm-mc -disassemble %s -triple=thumbv7em 2>&1 | FileCheck %s
1 # RUN: not llvm-mc -disassemble %s -triple=thumbv7m 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7M %s
0 # RUN: llvm-mc -disassemble %s -triple=thumbv7em 2>&1 | FileCheck %s
1 # RUN: llvm-mc -disassemble %s -triple=thumbv7m 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7M %s
22
33 #------------------------------------------------------------------------------
44 # Undefined encodings for mrs
55 #------------------------------------------------------------------------------
66
77 # invalid SYSm
8 # CHECK: warning: invalid instruction encoding
8 # CHECK: warning: potentially undefined instruction encoding
99 # CHECK-NEXT: [0xef 0xf3 0x80 0x80]
1010 [0xef 0xf3 0x80 0x80]
1111
2929 [0x80 0xf3 0x00 0x84]
3030
3131 # invalid SYSm
32 # CHECK: warning: invalid instruction encoding
32 # CHECK: warning: potentially undefined instruction encoding
3333 # CHECK-NEXT: [0x80 0xf3 0x80 0x88]
3434 [0x80 0xf3 0x80 0x88]