llvm.org GIT mirror llvm / 0cb25a2
MIParser/MIRPrinter: Compute block successors if not explicitely specified - MIParser: If the successor list is not specified successors will be added based on basic block operands in the block and possible fallthrough. - MIRPrinter: Adds a new `simplify-mir` option, with that option set: Skip printing of block successor lists in cases where the parser is guaranteed to reconstruct it. This means we still print the list if some successor cannot be determined (happens for example for jump tables), if the successor order changes or branch probabilities being unequal. Differential Revision: https://reviews.llvm.org/D31262 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302289 91177308-0d34-0410-b5e6-96231b3b80d8 Matthias Braun 2 years ago
34 changed file(s) with 264 addition(s) and 316 deletion(s). Raw diff Collapse all Expand all
7676
7777 The MIR code coming out of ``-stop-after``/``-stop-before`` is very verbose;
7878 Tests are more accessible and future proof when simplified:
79
80 - Use the ``-simplify-mir`` option with llc.
7981
8082 - Machine function attributes often have default values or the test works just
8183 as well with default values. Typical candidates for this are: `alignment:`,
0 //===- MIRPrinter.h - MIR serialization format printer --------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the functions that print out the LLVM IR and the machine
10 // functions using the MIR serialization format.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef LLVM_LIB_CODEGEN_MIRPRINTER_H
15 #define LLVM_LIB_CODEGEN_MIRPRINTER_H
16
17 namespace llvm {
18
19 class MachineBasicBlock;
20 class MachineFunction;
21 class Module;
22 class raw_ostream;
23 template class SmallVectorImpl;
24
25 /// Print LLVM IR using the MIR serialization format to the given output stream.
26 void printMIR(raw_ostream &OS, const Module &M);
27
28 /// Print a machine function using the MIR serialization format to the given
29 /// output stream.
30 void printMIR(raw_ostream &OS, const MachineFunction &MF);
31
32 /// Determine a possible list of successors of a basic block based on the
33 /// basic block machine operand being used inside the block. This should give
34 /// you the correct list of successor blocks in most cases except for things
35 /// like jump tables where the basic block references can't easily be found.
36 /// The MIRPRinter will skip printing successors if they match the result of
37 /// this funciton and the parser will use this function to construct a list if
38 /// it is missing.
39 void guessSuccessors(const MachineBasicBlock &MBB,
40 SmallVectorImpl &Successors,
41 bool &IsFallthrough);
42
43 } // end namespace llvm
44
45 #endif
1111 //===----------------------------------------------------------------------===//
1212
1313 #include "MIParser.h"
14
1415 #include "MILexer.h"
1516 #include "llvm/ADT/StringMap.h"
1617 #include "llvm/ADT/StringSwitch.h"
1718 #include "llvm/AsmParser/Parser.h"
1819 #include "llvm/AsmParser/SlotMapping.h"
20 #include "llvm/CodeGen/MIRPrinter.h"
1921 #include "llvm/CodeGen/MachineBasicBlock.h"
2022 #include "llvm/CodeGen/MachineFrameInfo.h"
2123 #include "llvm/CodeGen/MachineFunction.h"
133135
134136 bool
135137 parseBasicBlockDefinition(DenseMap &MBBSlots);
136 bool parseBasicBlock(MachineBasicBlock &MBB);
138 bool parseBasicBlock(MachineBasicBlock &MBB,
139 MachineBasicBlock *&AddFalthroughFrom);
137140 bool parseBasicBlockLiveins(MachineBasicBlock &MBB);
138141 bool parseBasicBlockSuccessors(MachineBasicBlock &MBB);
139142
517520 return false;
518521 }
519522
520 bool MIParser::parseBasicBlock(MachineBasicBlock &MBB) {
523 bool MIParser::parseBasicBlock(MachineBasicBlock &MBB,
524 MachineBasicBlock *&AddFalthroughFrom) {
521525 // Skip the definition.
522526 assert(Token.is(MIToken::MachineBasicBlockLabel));
523527 lex();
537541 //
538542 // is equivalent to
539543 // liveins: %edi, %esi
544 bool ExplicitSuccesors = false;
540545 while (true) {
541546 if (Token.is(MIToken::kw_successors)) {
542547 if (parseBasicBlockSuccessors(MBB))
543548 return true;
549 ExplicitSuccesors = true;
544550 } else if (Token.is(MIToken::kw_liveins)) {
545551 if (parseBasicBlockLiveins(MBB))
546552 return true;
556562 // Parse the instructions.
557563 bool IsInBundle = false;
558564 MachineInstr *PrevMI = nullptr;
559 while (true) {
560 if (Token.is(MIToken::MachineBasicBlockLabel) || Token.is(MIToken::Eof))
561 return false;
562 else if (consumeIfPresent(MIToken::Newline))
565 while (!Token.is(MIToken::MachineBasicBlockLabel) &&
566 !Token.is(MIToken::Eof)) {
567 if (consumeIfPresent(MIToken::Newline))
563568 continue;
564569 if (consumeIfPresent(MIToken::rbrace)) {
565570 // The first parsing pass should verify that all closing '}' have an
591596 assert(Token.isNewlineOrEOF() && "MI is not fully parsed");
592597 lex();
593598 }
599
600 // Construct successor list by searching for basic block machine operands.
601 if (!ExplicitSuccesors) {
602 SmallVector Successors;
603 bool IsFallthrough;
604 guessSuccessors(MBB, Successors, IsFallthrough);
605 for (MachineBasicBlock *Succ : Successors)
606 MBB.addSuccessor(Succ);
607
608 if (IsFallthrough) {
609 AddFalthroughFrom = &MBB;
610 } else {
611 MBB.normalizeSuccProbs();
612 }
613 }
614
594615 return false;
595616 }
596617
604625 // The first parsing pass should have verified that this token is a MBB label
605626 // in the 'parseBasicBlockDefinitions' method.
606627 assert(Token.is(MIToken::MachineBasicBlockLabel));
628 MachineBasicBlock *AddFalthroughFrom = nullptr;
607629 do {
608630 MachineBasicBlock *MBB = nullptr;
609631 if (parseMBBReference(MBB))
610632 return true;
611 if (parseBasicBlock(*MBB))
633 if (AddFalthroughFrom) {
634 if (!AddFalthroughFrom->isSuccessor(MBB))
635 AddFalthroughFrom->addSuccessor(MBB);
636 AddFalthroughFrom->normalizeSuccProbs();
637 AddFalthroughFrom = nullptr;
638 }
639 if (parseBasicBlock(*MBB, AddFalthroughFrom))
612640 return true;
613641 // The method 'parseBasicBlock' should parse the whole block until the next
614642 // block or the end of file.
1111 //
1212 //===----------------------------------------------------------------------===//
1313
14 #include "MIRPrinter.h"
14 #include "llvm/CodeGen/MIRPrinter.h"
15
1516 #include "llvm/ADT/STLExtras.h"
1617 #include "llvm/ADT/SmallBitVector.h"
1718 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
3334 #include "llvm/MC/MCSymbol.h"
3435 #include "llvm/Support/Format.h"
3536 #include "llvm/Support/MemoryBuffer.h"
37 #include "llvm/Support/Options.h"
3638 #include "llvm/Support/YAMLTraits.h"
3739 #include "llvm/Support/raw_ostream.h"
3840 #include "llvm/Target/TargetInstrInfo.h"
4042 #include "llvm/Target/TargetSubtargetInfo.h"
4143
4244 using namespace llvm;
45
46 static cl::opt SimplifyMIR("simplify-mir",
47 cl::desc("Leave out unnecessary information when printing MIR"));
4348
4449 namespace {
4550
103108 ModuleSlotTracker &MST;
104109 const DenseMap &RegisterMaskIds;
105110 const DenseMap &StackObjectOperandMapping;
111
112 bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
113 bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
106114
107115 public:
108116 MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
453461 RegisterMaskIds.insert(std::make_pair(Mask, I++));
454462 }
455463
464 void llvm::guessSuccessors(const MachineBasicBlock &MBB,
465 SmallVectorImpl &Result,
466 bool &IsFallthrough) {
467 SmallPtrSet Seen;
468
469 for (const MachineInstr &MI : MBB) {
470 if (MI.isPHI())
471 continue;
472 for (const MachineOperand &MO : MI.operands()) {
473 if (!MO.isMBB())
474 continue;
475 MachineBasicBlock *Succ = MO.getMBB();
476 auto RP = Seen.insert(Succ);
477 if (RP.second)
478 Result.push_back(Succ);
479 }
480 }
481 MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
482 IsFallthrough = I == MBB.end() || !I->isBarrier();
483 }
484
485 bool
486 MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const {
487 if (MBB.succ_size() <= 1)
488 return true;
489 if (!MBB.hasSuccessorProbabilities())
490 return true;
491
492 SmallVector Normalized(MBB.Probs.begin(),
493 MBB.Probs.end());
494 BranchProbability::normalizeProbabilities(Normalized.begin(),
495 Normalized.end());
496 SmallVector Equal(Normalized.size());
497 BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end());
498
499 return std::equal(Normalized.begin(), Normalized.end(), Equal.begin());
500 }
501
502 bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const {
503 SmallVector GuessedSuccs;
504 bool GuessedFallthrough;
505 guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough);
506 if (GuessedFallthrough) {
507 const MachineFunction &MF = *MBB.getParent();
508 MachineFunction::const_iterator NextI = std::next(MBB.getIterator());
509 if (NextI != MF.end()) {
510 MachineBasicBlock *Next = const_cast(&*NextI);
511 if (!is_contained(GuessedSuccs, Next))
512 GuessedSuccs.push_back(Next);
513 }
514 }
515 if (GuessedSuccs.size() != MBB.succ_size())
516 return false;
517 return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin());
518 }
519
520
456521 void MIPrinter::print(const MachineBasicBlock &MBB) {
457522 assert(MBB.getNumber() >= 0 && "Invalid MBB number");
458523 OS << "bb." << MBB.getNumber();
491556
492557 bool HasLineAttributes = false;
493558 // Print the successors
494 if (!MBB.succ_empty()) {
559 bool canPredictProbs = canPredictBranchProbabilities(MBB);
560 if (!MBB.succ_empty() && (!SimplifyMIR || !canPredictProbs ||
561 !canPredictSuccessors(MBB))) {
495562 OS.indent(2) << "successors: ";
496563 for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
497564 if (I != MBB.succ_begin())
498565 OS << ", ";
499566 printMBBReference(**I);
500 if (MBB.hasSuccessorProbabilities())
567 if (!SimplifyMIR || !canPredictProbs)
501568 OS << '('
502569 << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
503570 << ')';
+0
-33
lib/CodeGen/MIRPrinter.h less more
None //===- MIRPrinter.h - MIR serialization format printer --------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the functions that print out the LLVM IR and the machine
10 // functions using the MIR serialization format.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef LLVM_LIB_CODEGEN_MIRPRINTER_H
15 #define LLVM_LIB_CODEGEN_MIRPRINTER_H
16
17 namespace llvm {
18
19 class MachineFunction;
20 class Module;
21 class raw_ostream;
22
23 /// Print LLVM IR using the MIR serialization format to the given output stream.
24 void printMIR(raw_ostream &OS, const Module &M);
25
26 /// Print a machine function using the MIR serialization format to the given
27 /// output stream.
28 void printMIR(raw_ostream &OS, const MachineFunction &MF);
29
30 } // end namespace llvm
31
32 #endif
1111 //
1212 //===----------------------------------------------------------------------===//
1313
14 #include "MIRPrinter.h"
14 #include "llvm/CodeGen/MIRPrinter.h"
15
1516 #include "llvm/CodeGen/Passes.h"
1617 #include "llvm/CodeGen/MachineFunctionPass.h"
1718 #include "llvm/CodeGen/MIRYamlMapping.h"
179179 %x9 = ADRP target-flags(aarch64-page, aarch64-got) @g5
180180
181181 bb.13:
182 successors: %bb.14
183182 ; Cannot produce a LOH for multiple users
184183 ; CHECK-NOT: MCLOH_AdrpAdd
185184 %x10 = ADRP target-flags(aarch64-page) @g0
66 tracksRegLiveness: true
77 body: |
88 bb.0:
9 successors: %bb.1, %bb.2
109 liveins: %x0, %x1
1110
1211 %x0 = COPY %x1
1312 CBNZX %x1, %bb.2
1413
1514 bb.1:
16 successors: %bb.3
17
18 %x0 = COPY %xzr
19 B %bb.3
20
21 bb.2:
22 successors: %bb.3
15 %x0 = COPY %xzr
16 B %bb.3
17
18 bb.2:
2319 liveins: %x1
2420
2521 %x0 = LDRXui %x1, 0
3733 tracksRegLiveness: true
3834 body: |
3935 bb.0:
40 successors: %bb.1, %bb.2
4136 liveins: %x0, %x1
4237
4338 %x1 = COPY %x0
4439 CBNZX %x1, %bb.2
4540
4641 bb.1:
47 successors: %bb.3
48
49 %x0 = COPY %xzr
50 B %bb.3
51
52 bb.2:
53 successors: %bb.3
42 %x0 = COPY %xzr
43 B %bb.3
44
45 bb.2:
5446 liveins: %x1
5547
5648 %x0 = LDRXui %x1, 0
6860 tracksRegLiveness: true
6961 body: |
7062 bb.0:
71 successors: %bb.1, %bb.2
7263 liveins: %x0, %x1, %x2
7364
7465 %x0 = COPY %x1
7667 CBNZX %x1, %bb.2
7768
7869 bb.1:
79 successors: %bb.3
80
81 %x0 = COPY %xzr
82 B %bb.3
83
84 bb.2:
85 successors: %bb.3
70 %x0 = COPY %xzr
71 B %bb.3
72
73 bb.2:
8674 liveins: %x1
8775
8876 %x0 = LDRXui %x1, 0
10088 tracksRegLiveness: true
10189 body: |
10290 bb.0:
103 successors: %bb.1, %bb.2
10491 liveins: %x0, %x1, %x2
10592
10693 %x1 = COPY %x0
10895 CBNZX %x1, %bb.2
10996
11097 bb.1:
111 successors: %bb.3
112
113 %x0 = COPY %xzr
114 B %bb.3
115
116 bb.2:
117 successors: %bb.3
98 %x0 = COPY %xzr
99 B %bb.3
100
101 bb.2:
118102 liveins: %x1
119103
120104 %x0 = LDRXui %x1, 0
132116 tracksRegLiveness: true
133117 body: |
134118 bb.0:
135 successors: %bb.1, %bb.2
136119 liveins: %x0, %x1, %x2
137120
138121 %x1 = COPY %x0
140123 CBNZX %x1, %bb.2
141124
142125 bb.1:
143 successors: %bb.3
144
145 %x0 = COPY %xzr
146 B %bb.3
147
148 bb.2:
149 successors: %bb.3
126 %x0 = COPY %xzr
127 B %bb.3
128
129 bb.2:
150130 liveins: %x1
151131
152132 %x0 = LDRXui %x1, 0
164144 tracksRegLiveness: true
165145 body: |
166146 bb.0:
167 successors: %bb.1, %bb.2
168147 liveins: %x0, %x1, %x2
169148
170149 %x2 = COPY %x0
172151 CBNZX %x1, %bb.2
173152
174153 bb.1:
175 successors: %bb.3
176
177 %x0 = COPY %xzr
178 B %bb.3
179
180 bb.2:
181 successors: %bb.3
154 %x0 = COPY %xzr
155 B %bb.3
156
157 bb.2:
182158 liveins: %x1
183159
184160 %x0 = LDRXui %x1, 0
196172 tracksRegLiveness: true
197173 body: |
198174 bb.0:
199 successors: %bb.1, %bb.2
200175 liveins: %x0, %x1, %x2
201176
202177 %x2 = COPY %x0
205180 CBNZX %x1, %bb.2
206181
207182 bb.1:
208 successors: %bb.3
209
210 %x0 = COPY %xzr
211 B %bb.3
212
213 bb.2:
214 successors: %bb.3
183 %x0 = COPY %xzr
184 B %bb.3
185
186 bb.2:
215187 liveins: %x1
216188
217189 %x0 = LDRXui %x1, 0
231203 tracksRegLiveness: true
232204 body: |
233205 bb.0:
234 successors: %bb.1, %bb.2
235206 liveins: %x0, %x1
236207
237208 %x1 = COPY %x0
238209 CBNZX %x1, %bb.2
239210
240211 bb.1:
241 successors: %bb.3
242212 liveins: %x0, %x2
243213
244214 %x0, %x1 = LDPXi %x2, 0
247217 B %bb.3
248218
249219 bb.2:
250 successors: %bb.3
251220 liveins: %x1
252221
253222 %x0 = LDRXui %x1, 0
266235 tracksRegLiveness: true
267236 body: |
268237 bb.0:
269 successors: %bb.1, %bb.2
270238 liveins: %x0, %x1
271239
272240 CBNZX %x0, %bb.2
273241
274242 bb.1:
275 successors: %bb.3
276243 liveins: %x0, %x2
277244
278245 %x0 = COPY %xzr
279246 B %bb.3
280247
281248 bb.2:
282 successors: %bb.1, %bb.3
283249 liveins: %x1
284250
285251 %x0 = LDRXui %x1, 0
303269 tracksRegLiveness: true
304270 body: |
305271 bb.0.entry:
306 successors: %bb.1, %bb.2
307272 liveins: %w0, %x1
308273
309274 dead %wzr = SUBSWri killed %w0, 7, 0, implicit-def %nzcv
311276 B %bb.1
312277
313278 bb.1:
314 successors: %bb.2
315279 liveins: %x1
316280
317281 %w0 = MOVi32imm 7
331295 tracksRegLiveness: true
332296 body: |
333297 bb.0.entry:
334 successors: %bb.1, %bb.2
335298 liveins: %x0, %x1
336299
337300 dead %xzr = SUBSXri killed %x0, 7, 0, implicit-def %nzcv
339302 B %bb.1
340303
341304 bb.1:
342 successors: %bb.2
343305 liveins: %x1
344306
345307 %w0 = MOVi32imm 7, implicit-def %x0
359321 tracksRegLiveness: true
360322 body: |
361323 bb.0.entry:
362 successors: %bb.1, %bb.2
363324 liveins: %x0, %x1
364325
365326 dead %xzr = SUBSXri killed %x0, 7, 0, implicit-def %nzcv
367328 B %bb.1
368329
369330 bb.1:
370 successors: %bb.2
371331 liveins: %x1
372332
373333 %w0 = MOVi32imm 7
387347 tracksRegLiveness: true
388348 body: |
389349 bb.0.entry:
390 successors: %bb.1, %bb.2
391350 liveins: %w0, %x1
392351
393352 dead %wzr = SUBSWri killed %w0, 7, 0, implicit-def %nzcv
395354 B %bb.1
396355
397356 bb.1:
398 successors: %bb.2
399357 liveins: %x1
400358
401359 %w0 = MOVi32imm 7, implicit-def %x0
412370 tracksRegLiveness: true
413371 body: |
414372 bb.0.entry:
415 successors: %bb.1, %bb.2
416373 liveins: %w0, %x1, %x2
417374
418375 dead %wzr = SUBSWri killed %w0, 7, 0, implicit-def %nzcv
422379 B %bb.1
423380
424381 bb.1:
425 successors: %bb.2
426382 liveins: %x1
427383
428384 %w0 = MOVi32imm 7
439395 tracksRegLiveness: true
440396 body: |
441397 bb.0.entry:
442 successors: %bb.1, %bb.2
443398 liveins: %w0, %x1, %x2
444399
445400 dead %wzr = SUBSWri killed %w0, 7, 0, implicit-def %nzcv
447402 B %bb.1
448403
449404 bb.1:
450 successors: %bb.2
451405 liveins: %x1, %x2
452406
453407 %w0 = LDRWui %x1, 0
466420 tracksRegLiveness: true
467421 body: |
468422 bb.0.entry:
469 successors: %bb.1, %bb.2
470423 liveins: %w0, %x1
471424
472425 dead %wzr = SUBSWri %w0, 7, 0, implicit-def %nzcv
475428 B %bb.1
476429
477430 bb.1:
478 successors: %bb.2
479431 liveins: %x1
480432
481433 %w2 = MOVi32imm 7
492444 tracksRegLiveness: true
493445 body: |
494446 bb.0.entry:
495 successors: %bb.1, %bb.2
496447 liveins: %w0, %x1
497448
498449 dead %w0 = SUBSWri killed %w0, 7, 0, implicit-def %nzcv
500451 B %bb.1
501452
502453 bb.1:
503 successors: %bb.2
504454 liveins: %x1
505455
506456 %w0 = MOVi32imm 7
519469 tracksRegLiveness: true
520470 body: |
521471 bb.0.entry:
522 successors: %bb.1, %bb.2
523472 liveins: %x0, %x1
524473
525474 CBNZX killed %x0, %bb.2
526475 B %bb.1
527476
528477 bb.1:
529 successors: %bb.2
530478 liveins: %x1
531479
532480 %x0 = MOVi64imm 4252017623040
546494 tracksRegLiveness: true
547495 body: |
548496 bb.0.entry:
549 successors: %bb.1, %bb.2
550497 liveins: %w0, %x1
551498
552499 dead %wzr = ADDSWri killed %w0, 1, 0, implicit-def %nzcv
554501 B %bb.1
555502
556503 bb.1:
557 successors: %bb.2
558504 liveins: %x1
559505
560506 %w0 = MOVi32imm -1
574520 tracksRegLiveness: true
575521 body: |
576522 bb.0:
577 successors: %bb.1, %bb.2
578523 liveins: %x0, %x1
579524
580525 dead %xzr = ADDSXri killed %x0, 1, 0, implicit-def %nzcv
582527 B %bb.1
583528
584529 bb.1:
585 successors: %bb.2
586530 liveins: %x1
587531
588532 %x0 = MOVi64imm -1
602546 tracksRegLiveness: true
603547 body: |
604548 bb.0.entry:
605 successors: %bb.1, %bb.2
606549 liveins: %x0, %x1
607550
608551 dead %xzr = ADDSXri killed %x0, 1, 0, implicit-def %nzcv
610553 B %bb.1
611554
612555 bb.1:
613 successors: %bb.2
614556 liveins: %x1
615557
616558 %w0 = MOVi32imm -1
628570 tracksRegLiveness: true
629571 body: |
630572 bb.0.entry:
631 successors: %bb.1, %bb.2
632573 liveins: %w0, %x1
633574
634575 dead %wzr = ADDSWri killed %w0, 1, 0, implicit-def %nzcv
636577 B %bb.1
637578
638579 bb.1:
639 successors: %bb.2
640580 liveins: %x1
641581
642582 %x0 = MOVi64imm -1
653593 tracksRegLiveness: true
654594 body: |
655595 bb.0.entry:
656 successors: %bb.1, %bb.2
657596 liveins: %w0, %x1
658597
659598 dead %wzr = SUBSWri killed %w0, 1, 12, implicit-def %nzcv
661600 B %bb.1
662601
663602 bb.1:
664 successors: %bb.2
665603 liveins: %x1
666604
667605 %w0 = MOVi32imm 4096
1616 ; CHECK-LABEL: bb.0:
1717 ; CHECK-NOT: COPY %wzr
1818 bb.0:
19 successors: %bb.3, %bb.1
2019 liveins: %w0
2120
2221 %0 = COPY %w0
2726 ; CHECK: COPY %wzr
2827
2928 bb.1:
30 successors: %bb.2
31
3229 B %bb.2
3330
3431 bb.2:
35 successors: %bb.3, %bb.2
36
3732 %2 = PHI %0, %bb.1, %4, %bb.2
3833 %w0 = COPY %1
3934 %3 = SUBSWri %2, 1, 0, implicit-def dead %nzcv
9292 name: func1
9393 body: |
9494 bb.0:
95 successors: %bb.1, %bb.2
9695 ; Cannot coalesce physreg because we have reads on other CFG paths (we
9796 ; currently abort for any control flow)
9897 ; CHECK-NOT: %fp = SUBXri
116115 name: func2
117116 body: |
118117 bb.0:
119 successors: %bb.1, %bb.2
120118 ; We can coalesce copies from physreg to vreg across multiple blocks.
121119 ; CHECK-NOT: COPY
122120 ; CHECK: CBZX undef %x0, %bb.1
293293 - { id: 5, class: sreg_128 }
294294 body: |
295295 bb.0:
296 successors: %bb.1
297296 S_NOP 0, implicit-def %0
298297 S_NOP 0, implicit-def %1
299298 S_NOP 0, implicit-def %2
301300 S_BRANCH %bb.1
302301
303302 bb.1:
304 successors: %bb.1, %bb.2
305303 %4 = PHI %3, %bb.0, %5, %bb.1
306304
307305 ; let's swiffle some lanes around for fun...
347345 - { id: 6, class: sreg_128 }
348346 body: |
349347 bb.0:
350 successors: %bb.1
351348 S_NOP 0, implicit-def %0
352349 S_NOP 0, implicit-def %1
353350 S_NOP 0, implicit-def dead %2
356353 S_BRANCH %bb.1
357354
358355 bb.1:
359 successors: %bb.1, %bb.2
360356 %5 = PHI %4, %bb.0, %6, %bb.1
361357
362358 ; rotate lanes, but skip sub2 lane...
395391 - { id: 3, class: sreg_128 }
396392 body: |
397393 bb.0:
398 successors: %bb.1
399394 S_NOP 0, implicit-def %0
400395 %1 = REG_SEQUENCE %0, %subreg.sub0
401396 S_BRANCH %bb.1
402397
403398 bb.1:
404 successors: %bb.1, %bb.2
405399 %2 = PHI %1, %bb.0, %3, %bb.1
406400
407401 ; rotate subreg lanes, skipping sub1
7676
7777 body: |
7878 bb.0:
79 successors: %bb.1
8079 %vcc = S_MOV_B64 0
8180 %vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec
8281 S_BRANCH %bb.1
8382
8483 bb.1:
85 successors: %bb.2
8684 implicit %vcc = V_CMP_EQ_I32_e32 %vgpr1, %vgpr2, implicit %exec
8785 %vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec
8886 S_BRANCH %bb.2
8987
9088 bb.2:
91 successors: %bb.3
9289 %vcc = V_CMP_EQ_I32_e64 %vgpr1, %vgpr2, implicit %exec
9390 %vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec
9491 S_BRANCH %bb.3
129126
130127 body: |
131128 bb.0:
132 successors: %bb.1
133129 S_SETREG_B32 %sgpr0, 1
134130 %sgpr1 = S_GETREG_B32 1
135131 S_BRANCH %bb.1
136132
137133 bb.1:
138 successors: %bb.2
139134 S_SETREG_IMM32_B32 0, 1
140135 %sgpr1 = S_GETREG_B32 1
141136 S_BRANCH %bb.2
142137
143138 bb.2:
144 successors: %bb.3
145139 S_SETREG_B32 %sgpr0, 1
146140 %sgpr1 = S_MOV_B32 0
147141 %sgpr2 = S_GETREG_B32 1
177171
178172 body: |
179173 bb.0:
180 successors: %bb.1
181174 S_SETREG_B32 %sgpr0, 1
182175 S_SETREG_B32 %sgpr1, 1
183176 S_BRANCH %bb.1
184177
185178 bb.1:
186 successors: %bb.2
187179 S_SETREG_B32 %sgpr0, 64
188180 S_SETREG_B32 %sgpr1, 128
189181 S_BRANCH %bb.2
236228
237229 body: |
238230 bb.0:
239 successors: %bb.1
240231 BUFFER_STORE_DWORD_OFFSET %vgpr3, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
241232 %vgpr3 = V_MOV_B32_e32 0, implicit %exec
242233 BUFFER_STORE_DWORDX3_OFFSET %vgpr2_vgpr3_vgpr4, %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec
309300
310301 body: |
311302 bb.0:
312 successors: %bb.1
313303 %vgpr0,%sgpr0_sgpr1 = V_ADD_I32_e64 %vgpr1, %vgpr2, implicit %vcc, implicit %exec
314304 %sgpr4 = V_READLANE_B32 %vgpr4, %sgpr0
315305 S_BRANCH %bb.1
316306
317307 bb.1:
318 successors: %bb.2
319308 %vgpr0,%sgpr0_sgpr1 = V_ADD_I32_e64 %vgpr1, %vgpr2, implicit %vcc, implicit %exec
320309 %vgpr4 = V_WRITELANE_B32 %sgpr0, %sgpr0
321310 S_BRANCH %bb.2
322311
323312 bb.2:
324 successors: %bb.3
325313 %vgpr0,implicit %vcc = V_ADD_I32_e32 %vgpr1, %vgpr2, implicit %vcc, implicit %exec
326314 %sgpr4 = V_READLANE_B32 %vgpr4, %vcc_lo
327315 S_BRANCH %bb.3
351339
352340 body: |
353341 bb.0:
354 successors: %bb.1
355342 S_SETREG_B32 %sgpr0, 3
356343 S_RFE_B64 %sgpr2_sgpr3
357344 S_BRANCH %bb.1
381368
382369 body: |
383370 bb.0:
384 successors: %bb.1
385371 %sgpr0 = S_MOV_FED_B32 %sgpr0
386372 %sgpr0 = S_MOV_B32 %sgpr0
387373 S_BRANCH %bb.1
422408
423409 body: |
424410 bb.0:
425 successors: %bb.1
426411 %m0 = S_MOV_B32 0
427412 %sgpr0 = S_MOVRELS_B32 %sgpr0, implicit %m0
428413 S_BRANCH %bb.1
429414
430415 bb.1:
431 successors: %bb.2
432416 %m0 = S_MOV_B32 0
433417 %sgpr0_sgpr1 = S_MOVRELS_B64 %sgpr0_sgpr1, implicit %m0
434418 S_BRANCH %bb.2
435419
436420 bb.2:
437 successors: %bb.3
438421 %m0 = S_MOV_B32 0
439422 %sgpr0 = S_MOVRELD_B32 %sgpr0, implicit %m0
440423 S_BRANCH %bb.3
474457
475458 body: |
476459 bb.0:
477 successors: %bb.1
478460 %m0 = S_MOV_B32 0
479461 %vgpr0 = V_INTERP_P1_F32 %vgpr0, 0, 0, implicit %m0, implicit %exec
480462 S_BRANCH %bb.1
481463
482464 bb.1:
483 successors: %bb.2
484465 %m0 = S_MOV_B32 0
485466 %vgpr0 = V_INTERP_P2_F32 %vgpr0, %vgpr1, 0, 0, implicit %m0, implicit %exec
486467 S_BRANCH %bb.2
487468
488469 bb.2:
489 successors: %bb.3
490470 %m0 = S_MOV_B32 0
491471 %vgpr0 = V_INTERP_P1_F32_16bank %vgpr0, 0, 0, implicit %m0, implicit %exec
492472 S_BRANCH %bb.3
5252 hasMustTailInVarArgFunc: false
5353 body: |
5454 bb.0.entry:
55 successors: %bb.2.if, %bb.1.else
5655 liveins: %sgpr0_sgpr1
5756
5857 %sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
6160 S_CBRANCH_VCCNZ %bb.2.if, implicit undef %vcc
6261
6362 bb.1.else:
64 successors: %bb.3.done
6563 liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
6664
6765 %vgpr0 = V_MOV_B32_e32 100, implicit %exec
7068 S_BRANCH %bb.3.done
7169
7270 bb.2.if:
73 successors: %bb.3.done
7471 liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
7572
7673 %vgpr0 = V_MOV_B32_e32 9, implicit %exec
1515 - { id: 0, class: sreg_64 }
1616 body: |
1717 bb.0:
18 successors: %bb.1, %bb.2
1918 S_NOP 0, implicit-def undef %0.sub0
2019 S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
2120 S_BRANCH %bb.2
2221
2322 bb.1:
24 successors: %bb.2
2523 S_NOP 0, implicit-def %0.sub1
2624 S_NOP 0, implicit %0.sub1
2725 S_BRANCH %bb.2
175175 hasMustTailInVarArgFunc: false
176176 body: |
177177 bb.0.main_body:
178 successors: %bb.1.if, %bb.2.end
179178 liveins: %vgpr0
180179
181180 %sgpr0_sgpr1 = COPY %exec
188187 S_BRANCH %bb.1.if
189188
190189 bb.1.if:
191 successors: %bb.2.end
192190 liveins: %sgpr0_sgpr1
193191
194192 %sgpr7 = S_MOV_B32 61440
235233 hasMustTailInVarArgFunc: false
236234 body: |
237235 bb.0.main_body:
238 successors: %bb.1.if, %bb.2.end
239236 liveins: %vgpr0
240237
241238 %sgpr0_sgpr1 = COPY %exec
247244 S_BRANCH %bb.1.if
248245
249246 bb.1.if:
250 successors: %bb.2.end
251247 liveins: %sgpr0_sgpr1
252248
253249 %sgpr7 = S_MOV_B32 61440
294290 hasMustTailInVarArgFunc: false
295291 body: |
296292 bb.0.main_body:
297 successors: %bb.1.if, %bb.2.end
298293 liveins: %vgpr0
299294
300295 %sgpr0_sgpr1 = COPY %exec
306301 S_BRANCH %bb.1.if
307302
308303 bb.1.if:
309 successors: %bb.2.end
310304 liveins: %sgpr0_sgpr1
311305
312306 %sgpr7 = S_MOV_B32 61440
355349 hasMustTailInVarArgFunc: false
356350 body: |
357351 bb.0.main_body:
358 successors: %bb.1.if, %bb.2.end
359352 liveins: %vgpr0
360353
361354 %sgpr0_sgpr1 = COPY %exec
369362 S_BRANCH %bb.1.if
370363
371364 bb.1.if:
372 successors: %bb.2.end
373365 liveins: %sgpr0_sgpr1
374366
375367 %sgpr7 = S_MOV_B32 61440
417409 hasMustTailInVarArgFunc: false
418410 body: |
419411 bb.0.main_body:
420 successors: %bb.1.if, %bb.2.end
421412 liveins: %vgpr0
422413
423414 %sgpr6 = S_MOV_B32 -1
432423 S_BRANCH %bb.1.if
433424
434425 bb.1.if:
435 successors: %bb.2.end
436426 liveins: %sgpr0_sgpr1 , %sgpr4_sgpr5_sgpr6_sgpr7
437427 %vgpr0 = BUFFER_LOAD_DWORD_OFFSET %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `i32 addrspace(1)* undef`)
438428
479469 hasMustTailInVarArgFunc: false
480470 body: |
481471 bb.0.main_body:
482 successors: %bb.1.if, %bb.2.end
483472 liveins: %vgpr0
484473
485474 %sgpr0_sgpr1 = COPY %exec
493482 S_BRANCH %bb.1.if
494483
495484 bb.1.if:
496 successors: %bb.2.end
497485 liveins: %sgpr0_sgpr1
498486
499487 %sgpr7 = S_MOV_B32 61440
543531 hasMustTailInVarArgFunc: false
544532 body: |
545533 bb.0.main_body:
546 successors: %bb.1.if, %bb.2.end
547534 liveins: %vgpr0
548535
549536 %sgpr0_sgpr1 = COPY %exec
556543 S_BRANCH %bb.1.if
557544
558545 bb.1.if:
559 successors: %bb.2.end
560546 liveins: %sgpr0_sgpr1, %sgpr2_sgpr3
561547 S_SLEEP 0, implicit %sgpr2_sgpr3
562548 %sgpr7 = S_MOV_B32 61440
605591 hasMustTailInVarArgFunc: false
606592 body: |
607593 bb.0.main_body:
608 successors: %bb.1.if, %bb.2.end
609594 liveins: %vgpr0
610595
611596 %sgpr0_sgpr1 = COPY %exec
617602 S_BRANCH %bb.1.if
618603
619604 bb.1.if:
620 successors: %bb.2.end
621605 liveins: %sgpr0_sgpr1
622606
623607 %sgpr7 = S_MOV_B32 61440
664648 hasMustTailInVarArgFunc: false
665649 body: |
666650 bb.0.main_body:
667 successors: %bb.1.if, %bb.2.end
668651 liveins: %vgpr0
669652
670653 %sgpr0_sgpr1 = COPY %exec
676659 S_BRANCH %bb.1.if
677660
678661 bb.1.if:
679 successors: %bb.2.end
680662 liveins: %sgpr0_sgpr1
681663
682664 %sgpr7 = S_MOV_B32 61440
723705 hasMustTailInVarArgFunc: false
724706 body: |
725707 bb.0.main_body:
726 successors: %bb.1.if, %bb.2.end
727708 liveins: %vgpr0
728709
729710 %sgpr0_sgpr1 = COPY %exec
735716 S_BRANCH %bb.1.if
736717
737718 bb.1.if:
738 successors: %bb.2.end
739719 liveins: %sgpr0_sgpr1
740720
741721 %sgpr7 = S_MOV_B32 61440
4848 - { id: 1, class: sreg_128 }
4949 body: |
5050 bb.0:
51 successors: %bb.1, %bb.2
5251 S_NOP 0, implicit-def undef %0.sub2
5352 S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
5453 S_BRANCH %bb.2
1919 ; GCN: V_ADD_I32
2020 bb.0:
2121 liveins: %vgpr0
22 successors: %bb.1
2322 %7 = COPY %vgpr0
2423 %8 = S_MOV_B32 0
2524
2625 bb.1:
27 successors: %bb.1, %bb.2
2826 %0 = PHI %8, %bb.0, %0, %bb.1, %2, %bb.2
2927 %9 = V_MOV_B32_e32 9, implicit %exec
3028 %10 = V_CMP_EQ_U32_e64 %7, %9, implicit %exec
3230 S_BRANCH %bb.1
3331
3432 bb.2:
35 successors: %bb.1
3633 SI_END_CF %1, implicit-def %exec, implicit-def %scc, implicit %exec
3734 %11 = S_MOV_B32 1
3835 %2 = S_ADD_I32 %0, %11, implicit-def %scc
3030 - { id: 0, class: sreg_64 }
3131 body: |
3232 bb.0:
33 successors: %bb.1, %bb.2
3433 S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
3534 S_BRANCH %bb.2
3635
3736 bb.1:
38 successors: %bb.3
3937 S_NOP 0, implicit-def undef %0.sub0
4038 S_BRANCH %bb.3
4139
4240 bb.2:
43 successors: %bb.3
4441 S_NOP 0, implicit-def %0
4542 S_BRANCH %bb.3
4643
7474 hasMustTailInVarArgFunc: false
7575 body: |
7676 bb.0.entry:
77 successors: %bb.2.if, %bb.1.else
7877 liveins: %sgpr0_sgpr1
7978
8079 %sgpr2 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 9, 0 :: (non-temporal dereferenceable invariant load 4 from `float addrspace(2)* undef`)
8584 S_CBRANCH_VCCZ %bb.1.else, implicit killed %vcc
8685
8786 bb.2.if:
88 successors: %bb.3.done
8987 liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
9088
9189 %vgpr0 = V_MOV_B32_e32 9, implicit %exec
9492 S_BRANCH %bb.3.done
9593
9694 bb.1.else:
97 successors: %bb.3.done
9895 liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
9996
10097 %vgpr0 = V_MOV_B32_e32 100, implicit %exec
140137 hasMustTailInVarArgFunc: false
141138 body: |
142139 bb.0.entry:
143 successors: %bb.2.if, %bb.1.else
144140 liveins: %sgpr0_sgpr1
145141
146142 %sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
149145 S_CBRANCH_VCCZ %bb.1.else, implicit undef %vcc
150146
151147 bb.2.if:
152 successors: %bb.3.done
153148 liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
154149
155150 %vgpr0 = V_MOV_B32_e32 9, implicit %exec
158153 S_BRANCH %bb.3.done
159154
160155 bb.1.else:
161 successors: %bb.3.done
162156 liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
163157
164158 %vgpr0 = V_MOV_B32_e32 100, implicit %exec
117117 - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7' }
118118 body: |
119119 bb.0.entry:
120 successors: %bb.1, %bb.2.if.end
121120 liveins: %r0, %r1, %r2, %r3, %lr, %r7
122121
123122 DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28
5454 # CHECK-NOT: tCMPi8
5555 body: |
5656 bb.0.entry:
57 successors: %bb.1.entry(0x40000000), %bb.2.entry(0x40000000)
5857 liveins: %r0, %r1
5958
6059 %1 = COPY %r1
6665 tBcc %bb.2.entry, 0, %cpsr
6766
6867 bb.1.entry:
69 successors: %bb.2.entry(0x80000000)
70
7168
7269 bb.2.entry:
7370 %5 = PHI %4, %bb.1.entry, %3, %bb.0.entry
7575 # CHECK-NEXT: tCMPi8
7676 body: |
7777 bb.0.entry:
78 successors: %bb.1.if.then(0x40000000), %bb.2.if.end(0x40000000)
7978 liveins: %r0, %r1
8079
8180 %1 = COPY %r1
8786 tB %bb.1.if.then, 14, _
8887
8988 bb.1.if.then:
90 successors: %bb.3.return(0x80000000)
91
9289 %4, %cpsr = tMOVi8 42, 14, _
9390 tSTRspi killed %4, %stack.0.retval, 0, 14, _ :: (store 4 into %ir.retval)
9491 tB %bb.3.return, 14, _
9592
9693 bb.2.if.end:
97 successors: %bb.3.return(0x80000000)
98
9994 %3, %cpsr = tMOVi8 1, 14, _
10095 tSTRspi killed %3, %stack.0.retval, 0, 14, _ :: (store 4 into %ir.retval)
10196
208208 - { id: 5, type: spill-slot, offset: -24, size: 4, alignment: 4, callee-saved-register: '%r4' }
209209 body: |
210210 bb.0.entry:
211 successors: %bb.5.if.end, %bb.1.if.then
212211 liveins: %r0, %r4, %r5, %r6, %r7, %r11, %lr
213212
214213 %sp = frame-setup STMDB_UPD %sp, 14, _, killed %r4, killed %r5, killed %r6, killed %r7, killed %r11, killed %lr
231230 Bcc %bb.5.if.end, 0, killed %cpsr
232231
233232 bb.1.if.then:
234 successors: %bb.3.for.cond
235233 liveins: %r4, %r5
236234
237235 %r0 = MOVi 12, 14, _, _, debug-location !26
244242 B %bb.3.for.cond
245243
246244 bb.2.for.body:
247 successors: %bb.3.for.cond
248245 liveins: %r4, %r5, %r6, %r7
249246
250247 %r1 = ADDrr %r5, %r7, 14, _, _, debug-location !36
254251 DBG_VALUE debug-use %r7, debug-use _, !18, !20, debug-location !28
255252
256253 bb.3.for.cond:
257 successors: %bb.2.for.body, %bb.4.for.cond.cleanup
258254 liveins: %r4, %r5, %r6, %r7
259255
260256 DBG_VALUE debug-use %r7, debug-use _, !18, !20, debug-location !28
262258 Bcc %bb.2.for.body, 11, killed %cpsr, debug-location !33
263259
264260 bb.4.for.cond.cleanup:
265 successors: %bb.5.if.end
266261 liveins: %r4, %r5, %r6
267262
268263 %r0 = MOVr %r5, 14, _, _, debug-location !34
+0
-28
test/CodeGen/MIR/Generic/branch-probabilities.ll less more
None ; RUN: llc -stop-after machine-sink %s -o %t.mir
1 ; RUN: FileCheck %s < %t.mir
2 ; RUN: llc %t.mir -run-pass machine-sink
3 ; Check that branch probabilities are printed in a format that can then be parsed.
4 ; This test fails on powerpc because of an undefined physical register use in the MIR. See PR31062.
5 ; XFAIL: powerpc
6
7 declare void @foo()
8 declare void @bar()
9
10 define void @test(i1 %c) {
11 ; CHECK-LABEL: name: test
12 entry:
13 br i1 %c, label %then, label %else
14
15 then:
16 call void @foo()
17 br label %end
18 ; CHECK: successors: %{{[a-z0-9\-\.]+}}({{0x[0-9a-f]+}}), %{{[a-z0-9\-\.]+}}({{0x[0-9a-f]+}})
19
20 else:
21 call void @bar()
22 br label %end
23 ; CHECK: successors: %{{[a-z0-9\-\.]+}}({{0x[0-9a-f]+}})
24
25 end:
26 ret void
27 }
0 # RUN: llc -o - %s -run-pass=none -verify-machineinstrs -simplify-mir | FileCheck %s
1 ---
2 # We shouldn't need any explicit successor lists in these examples
3 # CHECK-LABEL: name: func0
4 # CHECK: bb.0:
5 # CHECK-NOT: successors
6 # CHECK: JE_1 %bb.1, implicit undef %eflags
7 # CHECK: JMP_1 %bb.3
8 # CHECK: bb.1:
9 # CHECK-NOT: successors
10 # CHECK: bb.2:
11 # CHECK-NOT: successors
12 # CHECK: JE_1 %bb.1, implicit undef %eflags
13 # CHECK: bb.3:
14 # CHECK: RETQ undef %eax
15 name: func0
16 body: |
17 bb.0:
18 JE_1 %bb.1, implicit undef %eflags
19 JMP_1 %bb.3
20
21 bb.1:
22
23 bb.2:
24 JE_1 %bb.1, implicit undef %eflags
25
26 bb.3:
27 JE_1 %bb.4, implicit undef %eflags ; condjump+fallthrough to same block
28
29 bb.4:
30 RETQ undef %eax
31 ...
32 ---
33 # Some cases that need explicit successors:
34 # CHECK-LABEL: name: func1
35 name: func1
36 body: |
37 bb.0:
38 ; CHECK: bb.0:
39 ; CHECK: successors: %bb.3, %bb.1
40 successors: %bb.3, %bb.1 ; different order than operands
41 JE_1 %bb.1, implicit undef %eflags
42 JMP_1 %bb.3
43
44 bb.1:
45 ; CHECK: bb.1:
46 ; CHECK: successors: %bb.2, %bb.1
47 successors: %bb.2, %bb.1 ; different order (fallthrough variant)
48 JE_1 %bb.1, implicit undef %eflags
49
50 bb.2:
51 ; CHECK: bb.2:
52 ; CHECK: successors: %bb.1(0x60000000), %bb.3(0x20000000)
53 successors: %bb.1(3), %bb.3(1) ; branch probabilities not normalized
54 JE_1 %bb.1, implicit undef %eflags
55
56 bb.3:
57 ; CHECK: bb.3:
58 ; CHECK: RETQ undef %eax
59 RETQ undef %eax
60 ...
0 # RUN: llc -o - %s -mtriple=x86_64-- -run-pass=none | FileCheck %s
1 ---
2 # Check that branch probabilities are printed correctly as hex numbers.
3 # CHECK-LABEL: name: test
4 # CHECK: bb.0:
5 # CHECK-NEXT: successors: %bb.1(0x66666666), %bb.2(0x1999999a)
6 name: test
7 body: |
8 bb.0:
9 successors: %bb.1(4), %bb.2(1)
10 JE_1 %bb.2, implicit undef %eflags
11
12 bb.1:
13 NOOP
14
15 bb.2:
16 RETQ undef %eax
17 ...
3131 name: foo
3232 body: |
3333 ; CHECK-LABEL: bb.0.entry:
34 ; CHECK: successors: %bb.1.less(0x40000000), %bb.2.exit(0x40000000)
3534 ; CHECK-LABEL: bb.1.less:
3635 bb.0.entry:
3736 successors: %bb.1.less, %bb.2.exit
1515 tracksRegLiveness: true
1616 body: |
1717 bb.0:
18 successors: %bb.1, %bb.2
1918 JE_1 %bb.1, implicit undef %eflags
2019 JMP_1 %bb.2
2120
2424 body: |
2525 bb.0.entry:
2626 liveins: %edi
27 successors: %bb.1.false
2827 NOOP implicit-def %al
2928
3029 ; The bug was triggered only when LivePhysReg is used, which
383383
384384 body: |
385385 bb.0.entry:
386 successors: %bb.3.is_null, %bb.1.not_null
387386 liveins: %esi, %rdi
388387
389388 TEST64rr %rdi, %rdi, implicit-def %eflags
390389 JE_1 %bb.3.is_null, implicit %eflags
391390
392391 bb.1.not_null:
393 successors: %bb.4.ret_100, %bb.2.ret_200
394392 liveins: %esi, %rdi
395393
396394 %eax = MOV32ri 2200000
426424
427425 body: |
428426 bb.0.entry:
429 successors: %bb.3.is_null, %bb.1.not_null
430427 liveins: %esi, %rdi, %rdx
431428
432429 %eax = MOV32rm killed %rdx, 1, _, 0, _ :: (volatile load 4 from %ir.ptr)
434431 JE_1 %bb.3.is_null, implicit %eflags
435432
436433 bb.1.not_null:
437 successors: %bb.4.ret_100, %bb.2.ret_200
438434 liveins: %esi, %rdi
439435
440436 %eax = MOV32ri 2200000
443439 JE_1 %bb.4.ret_100, implicit %eflags
444440
445441 bb.2.ret_200:
446 successors: %bb.3.is_null
447442
448443 %eax = MOV32ri 200
449444
471466
472467 body: |
473468 bb.0.entry:
474 successors: %bb.3.is_null, %bb.1.not_null
475469 liveins: %esi, %rdi
476470
477471 TEST64rr %rdi, %rdi, implicit-def %eflags
478472 JE_1 %bb.3.is_null, implicit %eflags
479473
480474 bb.1.not_null:
481 successors: %bb.4.ret_100, %bb.2.ret_200
482475 liveins: %esi, %rdi
483476
484477 %eax = MOV32ri 2200000
514507
515508 body: |
516509 bb.0.entry:
517 successors: %bb.3.is_null, %bb.1.not_null
518510 liveins: %rsi, %rdi
519511
520512 TEST64rr %rdi, %rdi, implicit-def %eflags
521513 JE_1 %bb.3.is_null, implicit %eflags
522514
523515 bb.1.not_null:
524 successors: %bb.4.ret_100, %bb.2.ret_200
525516 liveins: %rsi, %rdi
526517
527518 %rdi = MOV64ri 5000
556547
557548 body: |
558549 bb.0.entry:
559 successors: %bb.3.is_null, %bb.1.not_null
560550 liveins: %rsi, %rdi, %rdx
561551
562552 TEST64rr %rdi, %rdi, implicit-def %eflags
563553 JE_1 %bb.3.is_null, implicit %eflags
564554
565555 bb.1.not_null:
566 successors: %bb.4.ret_100, %bb.2.ret_200
567556 liveins: %rsi, %rdi, %rdx
568557
569558 %rbx = MOV64rr %rdx
602591 # CHECK: CALL64pcrel32
603592 body: |
604593 bb.0.entry:
605 successors: %bb.2.leave, %bb.1.stay
606594 liveins: %rdi, %rbx
607595
608596 frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
644632 - { reg: '%rsi' }
645633 body: |
646634 bb.0.entry:
647 successors: %bb.2.is_null, %bb.1.not_null
648635 liveins: %rdi, %rsi
649636
650637 TEST64rr %rdi, %rdi, implicit-def %eflags
679666 - { reg: '%rsi' }
680667 body: |
681668 bb.0.entry:
682 successors: %bb.2.is_null, %bb.1.not_null
683669 liveins: %rdi, %rsi
684670
685671 TEST64rr %rdi, %rdi, implicit-def %eflags
711697 - { reg: '%rsi' }
712698 body: |
713699 bb.0.entry:
714 successors: %bb.1.is_null(0x30000000), %bb.2.not_null(0x50000000)
715700 liveins: %rsi, %rdi
716701
717702 TEST64rr %rdi, %rdi, implicit-def %eflags
744729 - { reg: '%rsi' }
745730 body: |
746731 bb.0.entry:
747 successors: %bb.1.is_null(0x30000000), %bb.2.not_null(0x50000000)
748732 liveins: %rsi, %rdi
749733
750734 TEST64rr %rdi, %rdi, implicit-def %eflags
778762 - { reg: '%rsi' }
779763 body: |
780764 bb.0.entry:
781 successors: %bb.2.is_null, %bb.1.not_null
782765 liveins: %rdi, %rsi
783766
784767 TEST64rr %rdi, %rdi, implicit-def %eflags
809792 - { reg: '%rsi' }
810793 body: |
811794 bb.0.entry:
812 successors: %bb.2.is_null, %bb.1.not_null
813795 liveins: %rdi, %rsi
814796
815797 TEST64rr %rdi, %rdi, implicit-def %eflags
841823 - { reg: '%rsi' }
842824 body: |
843825 bb.0.entry:
844 successors: %bb.2.is_null, %bb.1.not_null
845826 liveins: %rdi, %rsi
846827
847828 TEST64rr %rdi, %rdi, implicit-def %eflags
873854 - { reg: '%rsi' }
874855 body: |
875856 bb.0.entry:
876 successors: %bb.2.is_null, %bb.1.not_null
877857 liveins: %rdi, %rsi
878858
879859 TEST64rr %rdi, %rdi, implicit-def %eflags
909889 - { reg: '%rsi' }
910890 body: |
911891 bb.0.entry:
912 successors: %bb.2.is_null, %bb.1.not_null
913892 liveins: %rdi, %rsi
914893
915894 TEST64rr %rdi, %rdi, implicit-def %eflags
940919 - { reg: '%rsi' }
941920 body: |
942921 bb.0.entry:
943 successors: %bb.2.is_null, %bb.1.not_null
944922 liveins: %rdi, %rsi
945923
946924 TEST64rr %rdi, %rdi, implicit-def %eflags
973951 - { reg: '%rsi' }
974952 body: |
975953 bb.0.entry:
976 successors: %bb.2.is_null, %bb.1.not_null
977954 liveins: %rdi, %rsi
978955
979956 TEST64rr %rdi, %rdi, implicit-def %eflags
1005982 - { reg: '%rsi' }
1006983 body: |
1007984 bb.0.entry:
1008 successors: %bb.2.is_null, %bb.1.not_null
1009985 liveins: %rdi, %rsi
1010986
1011987 TEST64rr %rdi, %rdi, implicit-def %eflags
10411017 '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ]
10421018 body: |
10431019 bb.0.entry:
1044 successors: %bb.2.is_null, %bb.1.not_null
10451020 liveins: %rdi, %rbx
10461021
10471022 frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
10811056 - { reg: '%rsi' }
10821057 body: |
10831058 bb.0.entry:
1084 successors: %bb.2.is_null, %bb.1.not_null
10851059 liveins: %rdi, %rsi
10861060
10871061 TEST64rr %rdi, %rdi, implicit-def %eflags
11151089 - { reg: '%rsi' }
11161090 body: |
11171091 bb.0.entry:
1118 successors: %bb.2.is_null, %bb.1.not_null
11191092 liveins: %rdi, %rsi
11201093
11211094 TEST64rr %rdi, %rdi, implicit-def %eflags
11481121 - { reg: '%rsi' }
11491122 body: |
11501123 bb.0.entry:
1151 successors: %bb.2.is_null, %bb.1.not_null
11521124 liveins: %rdi, %rsi
11531125
11541126 TEST64rr %rdi, %rdi, implicit-def %eflags
11811153 - { reg: '%rsi' }
11821154 body: |
11831155 bb.0.entry:
1184 successors: %bb.2.is_null, %bb.1.not_null
11851156 liveins: %rdi, %rsi
11861157
11871158 TEST64rr %rdi, %rdi, implicit-def %eflags
12131184 - { reg: '%rsi' }
12141185 body: |
12151186 bb.0.entry:
1216 successors: %bb.2.is_null, %bb.1.not_null
12171187 liveins: %rdi, %rsi
12181188
12191189 TEST64rr %rdi, %rdi, implicit-def %eflags
12451215 - { reg: '%rsi' }
12461216 body: |
12471217 bb.0.entry:
1248 successors: %bb.2.is_null, %bb.1.not_null
12491218 liveins: %rdi, %rsi
12501219
12511220 TEST64rr %rdi, %rdi, implicit-def %eflags
12781247 - { reg: '%rsi' }
12791248 body: |
12801249 bb.0.entry:
1281 successors: %bb.2.is_null, %bb.1.not_null
12821250 liveins: %rdi, %rsi
12831251
12841252 TEST64rr %rdi, %rdi, implicit-def %eflags
1515 - { id: 0, class: gr32 }
1616 body: |
1717 bb.0:
18 successors: %bb.2, %bb.3
1918 JG_1 %bb.2, implicit %eflags
2019 JMP_1 %bb.3
2120
2221 bb.2:
23 successors: %bb.3
2422 %0 = IMPLICIT_DEF
2523 JMP_1 %bb.3
2624
33 name: fun
44 body: |
55 bb.0:
6 successors: %bb.1, %bb.7
7
86 CMP32ri8 %edi, 40, implicit-def %eflags
97 JNE_1 %bb.7, implicit killed %eflags
108 JMP_1 %bb.1
119
1210 bb.1:
13 successors: %bb.2, %bb.11
14
1511 CMP32ri8 %edi, 1, implicit-def %eflags
1612 JNE_1 %bb.11, implicit killed %eflags
1713 JMP_1 %bb.2
1814
1915 bb.2:
20 successors: %bb.3, %bb.5
21
2216 CMP32ri8 %edi, 2, implicit-def %eflags
2317 JNE_1 %bb.5, implicit killed %eflags
2418 JMP_1 %bb.3
2519
2620 bb.3:
27 successors: %bb.4, %bb.5
28
2921 CMP32ri8 %edi, 90, implicit-def %eflags
3022 JNE_1 %bb.5, implicit killed %eflags
3123 JMP_1 %bb.4
3224
3325 bb.4:
34 successors: %bb.5
3526
3627 bb.5:
37 successors: %bb.6, %bb.11
38
3928 CMP32ri8 %edi, 4, implicit-def %eflags
4029 JNE_1 %bb.11, implicit killed %eflags
4130 JMP_1 %bb.6
4231
4332 bb.6:
44 successors: %bb.11
45
4633 JMP_1 %bb.11
4734
4835 bb.7:
49 successors: %bb.9, %bb.8
50
5136 CMP32ri8 %edi, 5, implicit-def %eflags
5237 JE_1 %bb.9, implicit killed %eflags
5338 JMP_1 %bb.8
5439
5540 bb.8:
56 successors: %bb.9
5741
5842 bb.9:
59 successors: %bb.11, %bb.10
60
6143 CMP32ri8 %edi, 6, implicit-def %eflags
6244 JE_1 %bb.11, implicit killed %eflags
6345 JMP_1 %bb.10
6446
6547 bb.10:
66 successors: %bb.11
6748
6849 bb.11:
6950 RET 0
7354 # CHECK: Region tree:
7455 # CHECK-NEXT: [0] BB#0 =>
7556 # CHECK-NEXT: [1] BB#0 => BB#11
57 # CHECK-NEXT: [2] BB#7 => BB#9
58 # CHECK-NEXT: [2] BB#9 => BB#11
7659 # CHECK-NEXT: [2] BB#1 => BB#11
7760 # CHECK-NEXT: [3] BB#2 => BB#5
7861 # CHECK-NEXT: [4] BB#3 => BB#5
7962 # CHECK-NEXT: [3] BB#5 => BB#11
80 # CHECK-NEXT: [2] BB#7 => BB#9
81 # CHECK-NEXT: [2] BB#9 => BB#11
8263 # CHECK-NEXT: End region tree
2424 - { id: 2, type: spill-slot, offset: -32, size: 4, alignment: 4 }
2525 body: |
2626 bb.0:
27 successors: %bb.1
2827 liveins: %ebp, %ebx, %edi, %esi
2928
3029 frame-setup PUSH32r killed %ebp, implicit-def %esp, implicit %esp
4039 %edx = MOV32ri 6
4140
4241 bb.1:
43 successors: %bb.3, %bb.2
4442 liveins: %eax, %ebp, %ebx, %ecx, %edi, %edx
4543
4644 %ebp = SHR32rCL killed %ebp, implicit-def dead %eflags, implicit %cl
6563 JE_1 %bb.3, implicit %eflags
6664
6765 bb.2:
68 successors: %bb.3
6966 liveins: %cl, %eax, %ebp, %esi
7067
7168 OR32mr %esp, 1, _, 8, _, killed %eax, implicit-def %eflags ; :: (store 4 into %stack.1)
8282 hasMustTailInVarArgFunc: false
8383 body: |
8484 bb.0.entry:
85 successors: %bb.4(0x30000000), %bb.1.while.body.preheader(0x50000000)
86
8785 %0 = MOV64rm %rip, 1, _, @b, _ :: (dereferenceable load 8 from @b)
8886 %12 = MOV8rm %0, 1, _, 0, _ :: (load 1 from %ir.t0)
8987 TEST8rr %12, %12, implicit-def %eflags
9189 JNE_1 %bb.1.while.body.preheader, implicit killed %eflags
9290
9391 bb.4:
94 successors: %bb.3.while.end(0x80000000)
95
9692 %10 = COPY %11
9793 JMP_1 %bb.3.while.end
9894
9995 bb.1.while.body.preheader:
100 successors: %bb.2.while.body(0x80000000)
10196
10297 bb.2.while.body:
103 successors: %bb.3.while.end(0x04000000), %bb.2.while.body(0x7c000000)
104
10598 %8 = MOVSX32rr8 %12
10699 %10 = COPY %11
107100 %10 = SHL32ri %10, 5, implicit-def dead %eflags