llvm.org GIT mirror llvm / 0c9f0c0
ARM: enable decoding of pc-relative PLD/PLI git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184701 91177308-0d34-0410-b5e6-96231b3b80d8 Amaury de la Vieuville 7 years ago
4 changed file(s) with 180 addition(s) and 46 deletion(s). Raw diff Collapse all Expand all
10231023 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
10241024 opc, ".w\t$Rt, $addr",
10251025 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
1026 bits<4> Rt;
1027 bits<13> addr;
10281026 let isReMaterializable = 1;
10291027 let Inst{31-27} = 0b11111;
10301028 let Inst{26-25} = 0b00;
10311029 let Inst{24} = signed;
1032 let Inst{23} = addr{12}; // add = (U == '1')
10331030 let Inst{22-21} = opcod;
10341031 let Inst{20} = 1; // load
10351032 let Inst{19-16} = 0b1111; // Rn
1033
1034 bits<4> Rt;
10361035 let Inst{15-12} = Rt{3-0};
1036
1037 bits<13> addr;
1038 let Inst{23} = addr{12}; // add = (U == '1')
10371039 let Inst{11-0} = addr{11-0};
10381040
10391041 let DecoderMethod = "DecodeT2LoadLabel";
15631565 Sched<[WritePreLd]> {
15641566 let Inst{31-25} = 0b1111100;
15651567 let Inst{24} = instr;
1568 let Inst{23} = 1;
15661569 let Inst{22} = 0;
15671570 let Inst{21} = write;
15681571 let Inst{20} = 1;
15691572 let Inst{15-12} = 0b1111;
15701573
15711574 bits<17> addr;
1572 let addr{12} = 1; // add = TRUE
15731575 let Inst{19-16} = addr{16-13}; // Rn
1574 let Inst{23} = addr{12}; // U
15751576 let Inst{11-0} = addr{11-0}; // imm12
1577
1578 let DecoderMethod = "DecodeT2LoadImm12";
15761579 }
15771580
15781581 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
15911594 bits<13> addr;
15921595 let Inst{19-16} = addr{12-9}; // Rn
15931596 let Inst{7-0} = addr{7-0}; // imm8
1597
1598 let DecoderMethod = "DecodeT2LoadImm8";
15941599 }
15951600
15961601 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
16041609 let Inst{21} = write;
16051610 let Inst{20} = 1;
16061611 let Inst{15-12} = 0b1111;
1607 let Inst{11-6} = 0000000;
1612 let Inst{11-6} = 0b000000;
16081613
16091614 bits<10> addr;
16101615 let Inst{19-16} = addr{9-6}; // Rn
16131618
16141619 let DecoderMethod = "DecodeT2LoadShift";
16151620 }
1616 // FIXME: We should have a separate 'pci' variant here. As-is we represent
1617 // it via the i12 variant, which it's related to, but that means we can
1618 // represent negative immediates, which aren't legal for anything except
1619 // the 'pci' case (Rn == 15).
1621
1622 // pci variant is very similar to i12, but supports negative offsets
1623 // from the PC.
1624 def pci : T2Iso<(outs), (ins t2ldrlabel:$addr), IIC_Preload, opc,
1625 "\t$addr",
1626 [(ARMPreload (ARMWrapper tconstpool:$addr),
1627 (i32 write), (i32 instr))]>,
1628 Sched<[WritePreLd]> {
1629 let Inst{31-25} = 0b1111100;
1630 let Inst{24} = instr;
1631 let Inst{22} = 0;
1632 let Inst{21} = write;
1633 let Inst{20} = 1;
1634 let Inst{19-16} = 0b1111;
1635 let Inst{15-12} = 0b1111;
1636
1637 bits<13> addr;
1638 let Inst{23} = addr{12}; // add = (U == '1')
1639 let Inst{11-0} = addr{11-0}; // imm12
1640
1641 let DecoderMethod = "DecodeT2LoadLabel";
1642 }
16201643 }
16211644
16221645 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
31983198 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
31993199 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
32003200
3201 if (Rn == 0xF) {
3201 if (Rn == 15) {
32023202 switch (Inst.getOpcode()) {
3203 case ARM::t2LDRBs:
3204 Inst.setOpcode(ARM::t2LDRBpci);
3205 break;
3206 case ARM::t2LDRHs:
3207 Inst.setOpcode(ARM::t2LDRHpci);
3208 break;
3209 case ARM::t2LDRSHs:
3210 Inst.setOpcode(ARM::t2LDRSHpci);
3211 break;
3212 case ARM::t2LDRSBs:
3213 Inst.setOpcode(ARM::t2LDRSBpci);
3214 break;
3215 case ARM::t2LDRs:
3216 Inst.setOpcode(ARM::t2LDRpci);
3217 break;
3218 case ARM::t2PLDs: {
3219 Inst.setOpcode(ARM::t2PLDi12);
3220 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
3221 int imm = fieldFromInstruction(Insn, 0, 12);
3222 if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1;
3223 Inst.addOperand(MCOperand::CreateImm(imm));
3224 return S;
3225 }
3226 default:
3227 return MCDisassembler::Fail;
3203 case ARM::t2LDRBs:
3204 Inst.setOpcode(ARM::t2LDRBpci);
3205 break;
3206 case ARM::t2LDRHs:
3207 Inst.setOpcode(ARM::t2LDRHpci);
3208 break;
3209 case ARM::t2LDRSHs:
3210 Inst.setOpcode(ARM::t2LDRSHpci);
3211 break;
3212 case ARM::t2LDRSBs:
3213 Inst.setOpcode(ARM::t2LDRSBpci);
3214 break;
3215 case ARM::t2LDRs:
3216 Inst.setOpcode(ARM::t2LDRpci);
3217 break;
3218 case ARM::t2PLDs:
3219 Inst.setOpcode(ARM::t2PLDpci);
3220 break;
3221 case ARM::t2PLIs:
3222 Inst.setOpcode(ARM::t2PLIpci);
3223 break;
3224 default:
3225 return MCDisassembler::Fail;
32283226 }
32293227
32303228 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3229 }
3230
3231 if (Rt == 15) {
3232 switch (Inst.getOpcode()) {
3233 case ARM::t2LDRSHs:
3234 return MCDisassembler::Fail;
3235 case ARM::t2LDRHs:
3236 // FIXME: this instruction is only available with MP extensions,
3237 // this should be checked first but we don't have access to the
3238 // feature bits here.
3239 Inst.setOpcode(ARM::t2PLDWs);
3240 break;
3241 default:
3242 break;
3243 }
32313244 }
32323245
32333246 switch (Inst.getOpcode()) {
32773290 case ARM::t2LDRSHi8:
32783291 Inst.setOpcode(ARM::t2LDRSHpci);
32793292 break;
3293 case ARM::t2PLDi8:
3294 Inst.setOpcode(ARM::t2PLDpci);
3295 break;
3296 case ARM::t2PLIi8:
3297 Inst.setOpcode(ARM::t2PLIpci);
3298 break;
32803299 default:
32813300 return MCDisassembler::Fail;
32823301 }
32833302 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
32843303 }
32853304
3286 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3287 return MCDisassembler::Fail;
3305 if (Rt == 15) {
3306 switch (Inst.getOpcode()) {
3307 case ARM::t2LDRSHi8:
3308 return MCDisassembler::Fail;
3309 default:
3310 break;
3311 }
3312 }
3313
3314 switch (Inst.getOpcode()) {
3315 case ARM::t2PLDi8:
3316 case ARM::t2PLIi8:
3317 break;
3318 default:
3319 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3320 return MCDisassembler::Fail;
3321 }
3322
32883323 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
32893324 return MCDisassembler::Fail;
32903325 return S;
33163351 case ARM::t2LDRSBi12:
33173352 Inst.setOpcode(ARM::t2LDRSBpci);
33183353 break;
3354 case ARM::t2PLDi12:
3355 Inst.setOpcode(ARM::t2PLDpci);
3356 break;
3357 case ARM::t2PLIi12:
3358 Inst.setOpcode(ARM::t2PLIpci);
3359 break;
33193360 default:
33203361 return MCDisassembler::Fail;
33213362 }
33223363 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
33233364 }
33243365
3325 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3326 return MCDisassembler::Fail;
3366 if (Rt == 15) {
3367 switch (Inst.getOpcode()) {
3368 case ARM::t2LDRSHi12:
3369 return MCDisassembler::Fail;
3370 case ARM::t2LDRHi12:
3371 Inst.setOpcode(ARM::t2PLDi12);
3372 break;
3373 default:
3374 break;
3375 }
3376 }
3377
3378 switch (Inst.getOpcode()) {
3379 case ARM::t2PLDi12:
3380 case ARM::t2PLIi12:
3381 break;
3382 default:
3383 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3384 return MCDisassembler::Fail;
3385 }
3386
33273387 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
33283388 return MCDisassembler::Fail;
33293389 return S;
33763436 unsigned U = fieldFromInstruction(Insn, 23, 1);
33773437 int imm = fieldFromInstruction(Insn, 0, 12);
33783438
3379 // FIXME: detect and decode PLD properly
3380 if (Inst.getOpcode() == ARM::t2LDRBpci && Rt == 15) {
3381 Inst.setOpcode(ARM::t2PLDi12);
3382 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
3383 } else {
3439 if (Rt == 15) {
3440 switch (Inst.getOpcode()) {
3441 case ARM::t2LDRBpci:
3442 case ARM::t2LDRHpci:
3443 Inst.setOpcode(ARM::t2PLDpci);
3444 break;
3445 case ARM::t2LDRSBpci:
3446 Inst.setOpcode(ARM::t2PLIpci);
3447 break;
3448 case ARM::t2LDRSHpci:
3449 return MCDisassembler::Fail;
3450 default:
3451 break;
3452 }
3453 }
3454
3455 switch(Inst.getOpcode()) {
3456 case ARM::t2PLDpci:
3457 case ARM::t2PLIpci:
3458 break;
3459 default:
33843460 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
33853461 return MCDisassembler::Fail;
33863462 }
35273603 break;
35283604 case ARM::t2LDRSB_PRE:
35293605 case ARM::t2LDRSB_POST:
3530 Inst.setOpcode(ARM::t2LDRSBpci);
3606 if (Rt == 15)
3607 Inst.setOpcode(ARM::t2PLIpci);
3608 else
3609 Inst.setOpcode(ARM::t2LDRSBpci);
35313610 break;
35323611 case ARM::t2LDRSH_PRE:
35333612 case ARM::t2LDRSH_POST:
0 # invalid LDRSHs Rt=PC
1 # RUN: echo "0x30 0xf9 0x00 0xf0" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
2
3 # invalid LDRSHi8 Rt=PC
4 # RUN: echo "0x30 0xf9 0x00 0xfc" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
5
6 # invalid LDRSHi12 Rt=PC
7 # RUN: echo "0xb0 0xf9 0x00 0xf0" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
8
9 # CHECK: invalid instruction encoding
13031303 0x1d 0xf8 0x02 0xf0
13041304
13051305 #------------------------------------------------------------------------------
1306 # PLD(literal)
1307 #------------------------------------------------------------------------------
1308 # CHECK: pld [pc, #-0]
1309 # CHECK: pld [pc, #455]
1310 # CHECK: pld [pc, #0]
1311
1312 0x1f 0xf8 0x00 0xf0
1313 0x9f 0xf8 0xc7 0xf1
1314 0x9f 0xf8 0x00 0xf0
1315
1316 #------------------------------------------------------------------------------
13061317 # PLI(immediate)
13071318 #------------------------------------------------------------------------------
13081319 # CHECK: pli [r5, #-4]
13331344 0x18 0xf9 0x22 0xf0
13341345 0x1d 0xf9 0x12 0xf0
13351346 0x1d 0xf9 0x02 0xf0
1347
1348 #------------------------------------------------------------------------------
1349 # PLI(literal)
1350 #------------------------------------------------------------------------------
1351 # CHECK: pli [pc, #-0]
1352 # CHECK: pli [pc, #-328]
1353 # CHECK: pli [pc, #0]
1354
1355 0x1f 0xf9 0x00 0xf0
1356 0x1f 0xf9 0x48 0xf1
1357 0x9f 0xf9 0x00 0xf0
13361358
13371359
13381360 #------------------------------------------------------------------------------