llvm.org GIT mirror llvm / 0c79dd7
Add DAG mutation interface to the post-RA scheduler Differential Revision: http://reviews.llvm.org/D17868 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262774 91177308-0d34-0410-b5e6-96231b3b80d8 Krzysztof Parzyszek 4 years ago
5 changed file(s) with 64 addition(s) and 15 deletion(s). Raw diff Collapse all Expand all
8080 #include "llvm/CodeGen/MachinePassRegistry.h"
8181 #include "llvm/CodeGen/RegisterPressure.h"
8282 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
83 #include "llvm/CodeGen/ScheduleDAGMutation.h"
8384 #include
8485
8586 namespace llvm {
217218 /// When all successor dependencies have been resolved, free this node for
218219 /// bottom-up scheduling.
219220 virtual void releaseBottomNode(SUnit *SU) = 0;
220 };
221
222 /// Mutate the DAG as a postpass after normal DAG building.
223 class ScheduleDAGMutation {
224 virtual void anchor();
225 public:
226 virtual ~ScheduleDAGMutation() {}
227
228 virtual void apply(ScheduleDAGMI *DAG) = 0;
229221 };
230222
231223 /// ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply
0 //==- ScheduleDAGMutation.h - MachineInstr Scheduling ------------*- C++ -*-==//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the ScheduleDAGMutation class, which represents
10 // a target-specific mutation of the dependency graph for scheduling.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef LLVM_CODEGEN_SCHEDULEDAGMUTATION_H
15 #define LLVM_CODEGEN_SCHEDULEDAGMUTATION_H
16
17 namespace llvm {
18 class ScheduleDAGInstrs;
19
20 /// Mutate the DAG as a postpass after normal DAG building.
21 class ScheduleDAGMutation {
22 virtual void anchor();
23 public:
24 virtual ~ScheduleDAGMutation() {}
25
26 virtual void apply(ScheduleDAGInstrs *DAG) = 0;
27 };
28 }
29
30 #endif
1515
1616 #include "llvm/CodeGen/PBQPRAConstraint.h"
1717 #include "llvm/CodeGen/SchedulerRegistry.h"
18 #include "llvm/CodeGen/ScheduleDAGMutation.h"
1819 #include "llvm/MC/MCSubtargetInfo.h"
1920 #include "llvm/Support/CodeGen.h"
21 #include
2022
2123 namespace llvm {
2224
164166 return CriticalPathRCs.clear();
165167 }
166168
169 // \brief Provide an ordered list of schedule DAG mutations for the post-RA
170 // scheduler.
171 virtual void getPostRAMutations(
172 std::vector> &Mutations) const {
173 }
174
167175 // For use with PostRAScheduling: get the minimum optimization level needed
168176 // to enable post-RA scheduling.
169177 virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const {
13761376 const TargetRegisterInfo *tri)
13771377 : TII(tii), TRI(tri) {}
13781378
1379 void apply(ScheduleDAGMI *DAG) override;
1379 void apply(ScheduleDAGInstrs *DAGInstrs) override;
13801380 protected:
13811381 void clusterNeighboringLoads(ArrayRef Loads, ScheduleDAGMI *DAG);
13821382 };
14281428 }
14291429
14301430 /// \brief Callback from DAG postProcessing to create cluster edges for loads.
1431 void LoadClusterMutation::apply(ScheduleDAGMI *DAG) {
1431 void LoadClusterMutation::apply(ScheduleDAGInstrs *DAGInstrs) {
1432 ScheduleDAGMI *DAG = static_cast(DAGInstrs);
1433
14321434 // Map DAG NodeNum to store chain ID.
14331435 DenseMap StoreChainIDs;
14341436 // Map each store chain to a set of dependent loads.
14731475 MacroFusion(const TargetInstrInfo &TII, const TargetRegisterInfo &TRI)
14741476 : TII(TII), TRI(TRI) {}
14751477
1476 void apply(ScheduleDAGMI *DAG) override;
1478 void apply(ScheduleDAGInstrs *DAGInstrs) override;
14771479 };
14781480 } // anonymous
14791481
14931495
14941496 /// \brief Callback from DAG postProcessing to create cluster edges to encourage
14951497 /// fused operations.
1496 void MacroFusion::apply(ScheduleDAGMI *DAG) {
1498 void MacroFusion::apply(ScheduleDAGInstrs *DAGInstrs) {
1499 ScheduleDAGMI *DAG = static_cast(DAGInstrs);
1500
14971501 // For now, assume targets can only fuse with the branch.
14981502 SUnit &ExitSU = DAG->ExitSU;
14991503 MachineInstr *Branch = ExitSU.getInstr();
15441548 public:
15451549 CopyConstrain(const TargetInstrInfo *, const TargetRegisterInfo *) {}
15461550
1547 void apply(ScheduleDAGMI *DAG) override;
1551 void apply(ScheduleDAGInstrs *DAGInstrs) override;
15481552
15491553 protected:
15501554 void constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG);
16971701
16981702 /// \brief Callback from DAG postProcessing to create weak edges to encourage
16991703 /// copy elimination.
1700 void CopyConstrain::apply(ScheduleDAGMI *DAG) {
1704 void CopyConstrain::apply(ScheduleDAGInstrs *DAGInstrs) {
1705 ScheduleDAGMI *DAG = static_cast(DAGInstrs);
17011706 assert(DAG->hasVRegLiveness() && "Expect VRegs with LiveIntervals");
17021707
17031708 MachineBasicBlock::iterator FirstPos = nextIfDebug(DAG->begin(), DAG->end());
127127 /// The schedule. Null SUnit*'s represent noop instructions.
128128 std::vector Sequence;
129129
130 /// Ordered list of DAG postprocessing steps.
131 std::vector> Mutations;
132
130133 /// The index in BB of RegionEnd.
131134 ///
132135 /// This is the instruction number from the top of the current block, not
175178 void finishBlock() override;
176179
177180 private:
181 /// Apply each ScheduleDAGMutation step in order.
182 void postprocessDAG();
183
178184 void ReleaseSucc(SUnit *SU, SDep *SuccEdge);
179185 void ReleaseSuccessors(SUnit *SU);
180186 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
202208 HazardRec =
203209 MF.getSubtarget().getInstrInfo()->CreateTargetPostRAHazardRecognizer(
204210 InstrItins, this);
211 MF.getSubtarget().getPostRAMutations(Mutations);
205212
206213 assert((AntiDepMode == TargetSubtargetInfo::ANTIDEP_NONE ||
207214 MRI.tracksLiveness()) &&
426433
427434 // Call the superclass.
428435 ScheduleDAGInstrs::finishBlock();
436 }
437
438 /// Apply each ScheduleDAGMutation step in order.
439 void SchedulePostRATDList::postprocessDAG() {
440 for (auto &M : Mutations)
441 M->apply(this);
429442 }
430443
431444 //===----------------------------------------------------------------------===//