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[SparcV9] For codegen generated library calls that return float, set inreg flag manually in LowerCall(). This makes the sparc backend to generate Sparc64 ABI compliant code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198149 91177308-0d34-0410-b5e6-96231b3b80d8 Venkatraman Govindaraju 5 years ago
2 changed file(s) with 28 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
12511251 SmallVector RVLocs;
12521252 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(),
12531253 DAG.getTarget(), RVLocs, *DAG.getContext());
1254
1255 // Set inreg flag manually for codegen generated library calls that
1256 // return float.
1257 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && CLI.CS == 0)
1258 CLI.Ins[0].Flags.setInReg();
1259
12541260 RVInfo.AnalyzeCallResult(CLI.Ins, CC_Sparc64);
12551261
12561262 // Copy all of the result registers out of their specified physreg.
439439 ret i64 %0
440440 }
441441
442
442 ; CHECK-LABEL: test_call_libfunc
443 ; CHECK: st %f1, [%fp+[[Offset0:[0-9]+]]]
444 ; CHECK: fmovs %f3, %f1
445 ; CHECK: call cosf
446 ; CHECK: st %f0, [%fp+[[Offset1:[0-9]+]]]
447 ; CHECK: ld [%fp+[[Offset0]]], %f1
448 ; CHECK: call sinf
449 ; CHECK: ld [%fp+[[Offset1]]], %f1
450 ; CHECK: fmuls %f1, %f0, %f0
451
452 define inreg float @test_call_libfunc(float %arg0, float %arg1) {
453 entry:
454 %0 = tail call inreg float @cosf(float %arg1)
455 %1 = tail call inreg float @sinf(float %arg0)
456 %2 = fmul float %0, %1
457 ret float %2
458 }
459
460 declare inreg float @cosf(float %arg) readnone nounwind
461 declare inreg float @sinf(float %arg) readnone nounwind
462
463