llvm.org GIT mirror llvm / 0bc25f4
Convert EXTRACT_SUBREG to COPY when emitting machine instrs. EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead. Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg(). The isMoveInstr hook will be removed later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107879 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 9 years ago
18 changed file(s) with 103 addition(s) and 131 deletion(s). Raw diff Collapse all Expand all
214214 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
215215 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
216216 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
217 bool isExtractSubreg() const {
218 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
219 }
220217 bool isInsertSubreg() const {
221218 return getOpcode() == TargetOpcode::INSERT_SUBREG;
222219 }
233230 /// isCopyLike - Return true if the instruction behaves like a copy.
234231 /// This does not include native copy instructions.
235232 bool isCopyLike() const {
236 return isCopy() || isSubregToReg() || isExtractSubreg() || isInsertSubreg();
233 return isCopy() || isSubregToReg();
234 }
235
236 /// isIdentityCopy - Return true is the instruction is an identity copy.
237 bool isIdentityCopy() const {
238 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
239 getOperand(0).getSubReg() == getOperand(1).getSubReg();
237240 }
238241
239242 /// readsRegister - Return true if the MachineInstr reads the specified
120120 if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
121121 SrcReg == DstReg)
122122 return true;
123
124 if (MI.getOpcode() == TargetOpcode::EXTRACT_SUBREG &&
125 MI.getOperand(0).getReg() == MI.getOperand(1).getReg())
126 return true;
127123
128124 if ((MI.getOpcode() == TargetOpcode::INSERT_SUBREG ||
129125 MI.getOpcode() == TargetOpcode::SUBREG_TO_REG) &&
191191 if (tii_->isMoveInstr(MI, SrcReg, DstReg, SrcSubReg, DstSubReg))
192192 if (SrcReg == li.reg || DstReg == li.reg)
193193 continue;
194 if (MI.isCopy() && MI.getOperand(0).getReg() == li.reg &&
195 MI.getOperand(1).getReg() == li.reg)
196 continue;
194197
195198 // Check for operands using reg
196199 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5252 bool runOnMachineFunction(MachineFunction&);
5353
5454 private:
55 bool LowerExtract(MachineInstr *MI);
5655 bool LowerSubregToReg(MachineInstr *MI);
5756 bool LowerCopy(MachineInstr *MI);
5857
120119 }
121120 }
122121
123 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
124 MachineBasicBlock *MBB = MI->getParent();
125
126 assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
127 MI->getOperand(1).isReg() && MI->getOperand(1).isUse() &&
128 MI->getOperand(2).isImm() && "Malformed extract_subreg");
129
130 unsigned DstReg = MI->getOperand(0).getReg();
131 unsigned SuperReg = MI->getOperand(1).getReg();
132 unsigned SubIdx = MI->getOperand(2).getImm();
133 unsigned SrcReg = TRI->getSubReg(SuperReg, SubIdx);
134
135 assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
136 "Extract supperg source must be a physical register");
137 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
138 "Extract destination must be in a physical register");
139 assert(SrcReg && "invalid subregister index for register");
140
141 DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
142
143 if (SrcReg == DstReg) {
144 // No need to insert an identity copy instruction.
145 if (MI->getOperand(1).isKill()) {
146 // We must make sure the super-register gets killed. Replace the
147 // instruction with KILL.
148 MI->setDesc(TII->get(TargetOpcode::KILL));
149 MI->RemoveOperand(2); // SubIdx
150 DEBUG(dbgs() << "subreg: replace by: " << *MI);
151 return true;
152 }
153
154 DEBUG(dbgs() << "subreg: eliminated!");
155 } else {
156 TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstReg, SrcReg, false);
157 // Transfer the kill/dead flags, if needed.
158 if (MI->getOperand(0).isDead())
159 TransferDeadFlag(MI, DstReg, TRI);
160 if (MI->getOperand(1).isKill())
161 TransferKillFlag(MI, SuperReg, TRI, true);
162 TransferImplicitDefs(MI);
163 DEBUG({
164 MachineBasicBlock::iterator dMI = MI;
165 dbgs() << "subreg: " << *(--dMI);
166 });
167 }
168
169 DEBUG(dbgs() << '\n');
170 MBB->erase(MI);
171 return true;
172 }
173
174122 bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
175123 MachineBasicBlock *MBB = MI->getParent();
176124 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
279227 MachineBasicBlock::iterator nmi = llvm::next(mi);
280228 MachineInstr *MI = mi;
281229 assert(!MI->isInsertSubreg() && "INSERT_SUBREG should no longer appear");
282 if (MI->isExtractSubreg()) {
283 MadeChange |= LowerExtract(MI);
284 } else if (MI->isSubregToReg()) {
230 assert(MI->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
231 "EXTRACT_SUBREG should no longer appear");
232 if (MI->isSubregToReg()) {
285233 MadeChange |= LowerSubregToReg(MI);
286234 } else if (MI->isCopy()) {
287235 MadeChange |= LowerCopy(MI);
125125 ++NumCoalesces;
126126 Changed = true;
127127 }
128
129 if (!DefMI->isCopy())
130 continue;
131 SrcReg = DefMI->getOperand(1).getReg();
132 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
133 continue;
134 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg())
135 continue;
136 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
137 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
138 const TargetRegisterClass *NewRC = getCommonSubClass(RC, SRC);
139 if (!NewRC)
140 continue;
141 DEBUG(dbgs() << "Coalescing: " << *DefMI);
142 DEBUG(dbgs() << "*** to: " << *MI);
143 MO.setReg(SrcReg);
144 MRI->clearKillFlags(SrcReg);
145 if (NewRC != SRC)
146 MRI->setRegClass(SrcReg, NewRC);
147 DefMI->eraseFromParent();
148 ++NumCoalesces;
149 Changed = true;
128150 }
129151
130152 return Changed;
127127 //
128128 // %reg1025 = %reg1024
129129 // ...
130 // %reg1027 = EXTRACT_SUBREG %reg1025, 4
130 // %reg1027 = COPY %reg1025:4
131131 // %reg1026 = SUBREG_TO_REG 0, %reg1027, 4
132132 //
133133 // The problem here is that SUBREG_TO_REG is there to assert that an
134134 // implicit zext occurs. It doesn't insert a zext instruction. If we allow
135 // the EXTRACT_SUBREG here, it will give us the value after the ,
135 // the COPY here, it will give us the value after the ,
136136 // not the original value of %reg1024 before .
137137 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
138138 continue;
184184 continue;
185185 unsigned NewVR = MRI->createVirtualRegister(RC);
186186 BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
187 TII->get(TargetOpcode::EXTRACT_SUBREG), NewVR)
188 .addReg(DstReg).addImm(SubIdx);
187 TII->get(TargetOpcode::COPY), NewVR)
188 .addReg(DstReg, 0, SubIdx);
189189 UseMO->setReg(NewVR);
190190 ++NumReuse;
191191 Changed = true;
4949 return true;
5050
5151 switch(OpIdx) {
52 case 1: return (MI->isExtractSubreg() || MI->isCopy()) &&
53 MI->getOperand(0).getSubReg() == 0;
52 case 1: return MI->isCopy() && MI->getOperand(0).getSubReg() == 0;
5453 case 2: return MI->isSubregToReg() && MI->getOperand(0).getSubReg() == 0;
5554 default: return false;
5655 }
421421 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
422422 if (vni->def != SlotIndex() && vni->isDefAccurate() &&
423423 (CopyMI = li_->getInstructionFromIndex(vni->def)) &&
424 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
424 (CopyMI->isCopy() ||
425 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)))
425426 // Defined by a copy, try to extend SrcReg forward
426 CandReg = SrcReg;
427 CandReg = CopyMI->isCopy() ? CopyMI->getOperand(1).getReg() : SrcReg;
427428 else if (TrivCoalesceEnds &&
428429 (CopyMI =
429430 li_->getInstructionFromIndex(range.end.getBaseIndex())) &&
979980 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
980981 if (CopyMI &&
981982 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
983 unsigned Reg = 0;
984 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
985 Reg = SrcReg;
986 else if (vrm_->isAssignedReg(SrcReg))
987 Reg = vrm_->getPhys(SrcReg);
988 if (Reg) {
989 if (SrcSubReg)
990 Reg = tri_->getSubReg(Reg, SrcSubReg);
991 if (DstSubReg)
992 Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
993 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
994 mri_->setRegAllocationHint(cur->reg, 0, Reg);
995 }
996 } else if (CopyMI && CopyMI->isCopy()) {
997 DstReg = CopyMI->getOperand(0).getReg();
998 DstSubReg = CopyMI->getOperand(0).getSubReg();
999 SrcReg = CopyMI->getOperand(1).getReg();
1000 SrcSubReg = CopyMI->getOperand(1).getSubReg();
9821001 unsigned Reg = 0;
9831002 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
9841003 Reg = SrcReg;
4848 DstSub = MI->getOperand(0).getSubReg();
4949 Src = MI->getOperand(1).getReg();
5050 SrcSub = MI->getOperand(1).getSubReg();
51 } else if (MI->isExtractSubreg()) {
52 Dst = MI->getOperand(0).getReg();
53 DstSub = MI->getOperand(0).getSubReg();
54 Src = MI->getOperand(1).getReg();
55 SrcSub = compose(MI->getOperand(1).getSubReg(), MI->getOperand(2).getImm());
5651 } else if (MI->isSubregToReg()) {
5752 Dst = MI->getOperand(0).getReg();
5853 DstSub = compose(MI->getOperand(0).getSubReg(), MI->getOperand(3).getImm());
11311131 unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
11321132 unsigned Op0, bool Op0IsKill,
11331133 uint32_t Idx) {
1134 const TargetRegisterClass* RC = MRI.getRegClass(Op0);
1135
11361134 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1137 const TargetInstrDesc &II = TII.get(TargetOpcode::EXTRACT_SUBREG);
1138
1139 if (II.getNumDefs() >= 1)
1140 BuildMI(MBB, DL, II, ResultReg)
1141 .addReg(Op0, Op0IsKill * RegState::Kill)
1142 .addImm(Idx);
1143 else {
1144 BuildMI(MBB, DL, II)
1145 .addReg(Op0, Op0IsKill * RegState::Kill)
1146 .addImm(Idx);
1147 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1148 II.ImplicitDefs[0], RC, RC, DL);
1149 if (!InsertedCopy)
1150 ResultReg = 0;
1151 }
1135 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
1136 "Cannot yet extract from physregs");
1137 BuildMI(MBB, DL, TII.get(TargetOpcode::COPY), ResultReg)
1138 .addReg(Op0, getKillRegState(Op0IsKill), Idx);
11521139 return ResultReg;
11531140 }
11541141
427427 }
428428
429429 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
430 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub
430431 unsigned SubIdx = cast(Node->getOperand(1))->getZExtValue();
431
432 // Create the extract_subreg machine instruction.
433 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
434 TII->get(TargetOpcode::EXTRACT_SUBREG));
435432
436433 // Figure out the register class to create for the destreg.
437434 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
449446 VRBase = MRI->createVirtualRegister(SRC);
450447 }
451448
452 // Add def, source, and subreg index
453 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
449 // Create the extract_subreg machine instruction.
450 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
451 TII->get(TargetOpcode::COPY), VRBase);
452
453 // Add source, and subreg index
454454 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap, /*IsDebug=*/false,
455455 IsClone, IsCloned);
456 MI->addOperand(MachineOperand::CreateImm(SubIdx));
456 assert(TargetRegisterInfo::isVirtualRegister(MI->getOperand(1).getReg()) &&
457 "Cannot yet extract from physregs");
458 MI->getOperand(1).setSubReg(SubIdx);
457459 MBB->insert(InsertPos, MI);
458460 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
459461 Opc == TargetOpcode::SUBREG_TO_REG) {
15241524 // If this isn't a copy nor a extract_subreg, we can't join intervals.
15251525 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
15261526 bool isInsUndef = false;
1527 if (Inst->isCopy() || Inst->isExtractSubreg()) {
1527 if (Inst->isCopy()) {
15281528 DstReg = Inst->getOperand(0).getReg();
15291529 SrcReg = Inst->getOperand(1).getReg();
15301530 } else if (Inst->isSubregToReg()) {
16561656 E = mri_->use_nodbg_end(); I != E; ++I) {
16571657 MachineOperand &Use = I.getOperand();
16581658 MachineInstr *UseMI = Use.getParent();
1659 if (UseMI->isIdentityCopy())
1660 continue;
16591661 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
16601662 if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
16611663 SrcReg == DstReg && SrcSubIdx == DstSubIdx)
16861688
16871689 // Ignore identity copies.
16881690 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1689 if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
1691 if (!MI->isIdentityCopy() &&
1692 !(tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
16901693 SrcReg == DstReg && SrcSubIdx == DstSubIdx))
16911694 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
16921695 MachineOperand &Use = MI->getOperand(i);
18171820
18181821 // If the move will be an identity move delete it
18191822 bool isMove= tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
1820 if (isMove && SrcReg == DstReg && SrcSubIdx == DstSubIdx) {
1823 if (MI->isIdentityCopy() ||
1824 (isMove && SrcReg == DstReg && SrcSubIdx == DstSubIdx)) {
18211825 if (li_->hasInterval(SrcReg)) {
18221826 LiveInterval &RegInt = li_->getInterval(SrcReg);
18231827 // If def of this move instruction is dead, remove its live range
507507
508508 // Abort the use is actually a sub-register def. We don't have enough
509509 // information to figure out if it is really legal.
510 if (MO.getSubReg() || MII->isExtractSubreg() || MII->isSubregToReg())
510 if (MO.getSubReg() || MII->isSubregToReg())
511511 return false;
512512
513513 const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI);
569569
570570 // Abort the use is actually a sub-register use. We don't have enough
571571 // information to figure out if it is really legal.
572 if (MO.getSubReg() || MII->isExtractSubreg())
572 if (MO.getSubReg())
573573 return false;
574574
575575 const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI);
381381 DstReg = 0;
382382 unsigned SrcSubIdx, DstSubIdx;
383383 if (!TII->isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
384 if (MI.isCopy() || MI.isExtractSubreg()) {
384 if (MI.isCopy()) {
385385 DstReg = MI.getOperand(0).getReg();
386386 SrcReg = MI.getOperand(1).getReg();
387387 } else if (MI.isInsertSubreg()) {
12901290 if (SrcDefMI->getParent() != DstDefMI->getParent())
12911291 continue;
12921292
1293 // If there are no other uses than extract_subreg which feed into
1293 // If there are no other uses than copies which feed into
12941294 // the reg_sequence, then we might be able to coalesce them.
12951295 bool CanCoalesce = true;
12961296 SmallVector SrcSubIndices, DstSubIndices;
12981298 UI = MRI->use_nodbg_begin(SrcReg),
12991299 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
13001300 MachineInstr *UseMI = &*UI;
1301 if (!UseMI->isExtractSubreg() ||
1302 UseMI->getOperand(0).getReg() != DstReg ||
1303 UseMI->getOperand(1).getSubReg() != 0) {
1301 if (!UseMI->isCopy() || UseMI->getOperand(0).getReg() != DstReg) {
13041302 CanCoalesce = false;
13051303 break;
13061304 }
1307 SrcSubIndices.push_back(UseMI->getOperand(2).getImm());
1305 SrcSubIndices.push_back(UseMI->getOperand(1).getSubReg());
13081306 DstSubIndices.push_back(UseMI->getOperand(0).getSubReg());
13091307 }
13101308
13391337 UI = MRI->use_nodbg_begin(SrcReg),
13401338 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
13411339 MachineInstr *UseMI = &*UI;
1342 assert(UseMI->isExtractSubreg());
1340 assert(UseMI->isCopy());
13431341 unsigned DstSubIdx = UseMI->getOperand(0).getSubReg();
1344 unsigned SrcSubIdx = UseMI->getOperand(2).getImm();
1342 unsigned SrcSubIdx = UseMI->getOperand(1).getSubReg();
13451343 assert(DstSubIdx != 0 && "missing subreg from RegSequence elimination");
13461344 if ((NewDstSubIdx == 0 &&
13471345 TRI->composeSubRegIndices(NewSrcSubIdx, DstSubIdx) != SrcSubIdx) ||
13561354 if (!CanCoalesce)
13571355 continue;
13581356
1359 // Insert a copy or an extract to replace the original extracts.
1357 // Insert a copy to replace the original.
13601358 MachineBasicBlock::iterator InsertLoc = SomeMI;
13611359 MachineInstr *CopyMI = BuildMI(*SomeMI->getParent(), SomeMI,
13621360 SomeMI->getDebugLoc(),
13721370 ++UI;
13731371 if (UseMI == CopyMI)
13741372 continue;
1375 assert(UseMI->isExtractSubreg());
1373 assert(UseMI->isCopy());
13761374 // Move any kills to the new copy or extract instruction.
13771375 if (UseMI->getOperand(1).isKill()) {
1378 MachineOperand *KillMO = CopyMI->findRegisterUseOperand(SrcReg);
1379 KillMO->setIsKill();
1376 CopyMI->getOperand(1).setIsKill();
13801377 if (LV)
13811378 // Update live variables
13821379 LV->replaceKillInstruction(SrcReg, UseMI, &*CopyMI);
14371434 }
14381435 IsImpDef = false;
14391436
1440 // Remember EXTRACT_SUBREG sources. These might be candidate for
1441 // coalescing.
1442 if (DefMI->isExtractSubreg())
1437 // Remember COPY sources. These might be candidate for coalescing.
1438 if (DefMI->isCopy())
14431439 RealSrcs.push_back(DefMI->getOperand(1).getReg());
14441440
14451441 if (!Seen.insert(SrcReg) ||
20112011 // = EXTRACT_SUBREG fi#1
20122012 // fi#1 is available in EDI, but it cannot be reused because it's not in
20132013 // the right register file.
2014 if (PhysReg && !AvoidReload && (SubIdx || MI.isExtractSubreg())) {
2014 if (PhysReg && !AvoidReload && SubIdx) {
20152015 const TargetRegisterClass* RC = MRI->getRegClass(VirtReg);
20162016 if (!RC->contains(PhysReg))
20172017 PhysReg = 0;
406406 "expected a virtual register");
407407 // Extracting from a Q or QQ register.
408408 MachineInstr *DefMI = MRI->getVRegDef(VirtReg);
409 if (!DefMI || !DefMI->isExtractSubreg())
409 if (!DefMI || !DefMI->isCopy() || !DefMI->getOperand(1).getSubReg())
410410 return false;
411411 VirtReg = DefMI->getOperand(1).getReg();
412412 if (LastSrcReg && LastSrcReg != VirtReg)
417417 RC != ARM::QQPRRegisterClass &&
418418 RC != ARM::QQQQPRRegisterClass)
419419 return false;
420 unsigned SubIdx = DefMI->getOperand(2).getImm();
420 unsigned SubIdx = DefMI->getOperand(1).getSubReg();
421421 if (LastSubIdx) {
422422 if (LastSubIdx != SubIdx-Stride)
423423 return false;
444444 MachineOperand &MO = MI->getOperand(FirstOpnd + R);
445445 unsigned OldReg = MO.getReg();
446446 MachineInstr *DefMI = MRI->getVRegDef(OldReg);
447 assert(DefMI->isExtractSubreg());
447 assert(DefMI->isCopy());
448448 MO.setReg(LastSrcReg);
449449 MO.setSubReg(SubIds[R]);
450450 MO.setIsKill(false);
10381038 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC, DL);
10391039
10401040 // The shift instruction uses X86::CL. If we defined a super-register
1041 // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what
1042 // we're doing here.
1041 // of X86::CL, emit a subreg KILL to precisely describe what we're doing here.
10431042 if (CReg != X86::CL)
1044 BuildMI(MBB, DL, TII.get(TargetOpcode::EXTRACT_SUBREG), X86::CL)
1045 .addReg(CReg).addImm(X86::sub_8bit);
1043 BuildMI(MBB, DL, TII.get(TargetOpcode::KILL), X86::CL)
1044 .addReg(CReg, RegState::Kill);
10461045
10471046 unsigned ResultReg = createResultReg(RC);
10481047 BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg);
12001200
12011201 MachineInstr *NewMI = MIB;
12021202 MachineInstr *ExtMI =
1203 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG))
1203 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
12041204 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1205 .addReg(leaOutReg, RegState::Kill)
1206 .addImm(X86::sub_16bit);
1205 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
12071206
12081207 if (LV) {
12091208 // Update live variables