llvm.org GIT mirror llvm / 0b94b5f
Fix 11769. In CanXFormVExtractWithShuffleIntoLoad we assumed that EXTRACT_VECTOR_ELT can be later handled by the DAGCombiner. However, in some cases on AVX, the EXTRACT_VECTOR_ELT is legalized to EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which currently is not handled by the DAGCombiner. In this patch I added a check that we only extract from the XMM part. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148298 91177308-0d34-0410-b5e6-96231b3b80d8 Nadav Rotem 8 years ago
2 changed file(s) with 19 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
62396239 unsigned Elt = cast(EltNo)->getZExtValue();
62406240 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
62416241 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
6242
6243 // If we are accessing the upper part of a YMM register
6244 // then the EXTRACT_VECTOR_ELT is likely to be legalized to a sequence of
6245 // EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which are not detected at this point
6246 // because the legalization of N did not happen yet.
6247 if (Idx >= NumElems/2 && VT.getSizeInBits() == 256)
6248 return false;
62426249
62436250 // Skip one more bit_convert if necessary
62446251 if (V.getOpcode() == ISD::BITCAST)
5959
6060 define <16 x i16> @test7(<4 x i16> %a) nounwind {
6161 ; CHECK: test7
62
6362 %b = shufflevector <4 x i16> %a, <4 x i16> undef, <16 x i32>
63 ; CHECK: ret
6464 ret <16 x i16> %b
6565 }
66
67 ; CHECK: test8
68 define void @test8() {
69 entry:
70 %0 = load <16 x i64> addrspace(1)* null, align 128
71 %1 = shufflevector <16 x i64> , <16 x i64> %0, <16 x i32>
72 %2 = shufflevector <16 x i64> %1, <16 x i64> %0, <16 x i32>
73 store <16 x i64> %2, <16 x i64> addrspace(1)* undef, align 128
74 ; CHECK: ret
75 ret void
76 }