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Merging r181577: ------------------------------------------------------------------------ r181577 | tstellar | 2013-05-09 19:09:29 -0700 (Thu, 09 May 2013) | 10 lines R600: Expand SRA for v4i32/v2i32 v2: Add v4i32 test Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181951 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Wendling 7 years ago
2 changed file(s) with 15 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
4949 setOperationAction(ISD::SHL, MVT::v2i32, Expand);
5050 setOperationAction(ISD::SRL, MVT::v4i32, Expand);
5151 setOperationAction(ISD::SRL, MVT::v2i32, Expand);
52 setOperationAction(ISD::SRA, MVT::v4i32, Expand);
53 setOperationAction(ISD::SRA, MVT::v2i32, Expand);
5254 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Expand);
5355 setOperationAction(ISD::UDIV, MVT::v4i32, Expand);
5456 setOperationAction(ISD::UREM, MVT::v4i32, Expand);
0 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ; CHECK: @ashr_v4i32
3 ; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
4 ; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
5 ; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
6 ; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
7
8 define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) {
9 %result = ashr <4 x i32> %a, %b
10 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
11 ret void
12 }