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Merging r322373: ------------------------------------------------------------------------ r322373 | d0k | 2018-01-12 07:03:24 -0800 (Fri, 12 Jan 2018) | 4 lines [PowerPC] Don't miscompile rotate+mask into an ANDIo if it can't recreate the immediate I'm not even sure if this transform is ever worth it, but this at least stops the bleeding. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@330082 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 2 years ago
2 changed file(s) with 139 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
24442444 Is64BitLI = Opc != PPC::RLDICL_32;
24452445 NewImm = InVal.getSExtValue();
24462446 SetCR = Opc == PPC::RLDICLo;
2447 if (SetCR && (SExtImm & NewImm) != NewImm)
2448 return false;
24472449 break;
24482450 }
24492451 return false;
24712473 Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
24722474 NewImm = InVal.getSExtValue();
24732475 SetCR = Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o;
2476 if (SetCR && (SExtImm & NewImm) != NewImm)
2477 return false;
24742478 break;
24752479 }
24762480 return false;
560560 }
561561
562562 ; Function Attrs: norecurse nounwind readnone
563 define i64 @testRLDICLo3(i64 %a, i64 %b) local_unnamed_addr #0 {
563 define i64 @testRLDICLo2(i64 %a, i64 %b) local_unnamed_addr #0 {
564564 entry:
565565 %shr = lshr i64 %a, 11
566566 %and = and i64 %shr, 16777215
568568 %cond = select i1 %tobool, i64 %b, i64 %and
569569 ret i64 %cond
570570 }
571
572 define i64 @testRLDICLo3(i64 %a, i64 %b) local_unnamed_addr #0 {
573 entry:
574 %shr = lshr i64 %a, 11
575 %and = and i64 %shr, 16777215
576 %tobool = icmp eq i64 %and, 0
577 %cond = select i1 %tobool, i64 %b, i64 %and
578 ret i64 %cond
579 }
571580
572581 ; Function Attrs: norecurse nounwind readnone
573582 define zeroext i32 @testRLWINM(i32 zeroext %a) local_unnamed_addr #0 {
610619 ret i32 %cond
611620 }
612621
622 ; Function Attrs: norecurse nounwind readnone
623 define zeroext i32 @testRLWINMo2(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
624 entry:
625 %and = and i32 %a, 255
626 %tobool = icmp eq i32 %and, 0
627 %cond = select i1 %tobool, i32 %b, i32 %a
628 ret i32 %cond
629 }
630
613631 ; Function Attrs: norecurse nounwind readnone
614632 define i64 @testRLWINM8o(i64 %a, i64 %b) local_unnamed_addr #0 {
615633 entry:
39133931
39143932 ...
39153933 ---
3934 name: testRLDICLo2
3935 # CHECK-ALL: name: testRLDICLo2
3936 alignment: 4
3937 exposesReturnsTwice: false
3938 legalized: false
3939 regBankSelected: false
3940 selected: false
3941 tracksRegLiveness: true
3942 registers:
3943 - { id: 0, class: g8rc, preferred-register: '' }
3944 - { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' }
3945 - { id: 2, class: g8rc_and_g8rc_nox0, preferred-register: '' }
3946 - { id: 3, class: crrc, preferred-register: '' }
3947 - { id: 4, class: g8rc, preferred-register: '' }
3948 liveins:
3949 - { reg: '%x3', virtual-reg: '%0' }
3950 - { reg: '%x4', virtual-reg: '%1' }
3951 frameInfo:
3952 isFrameAddressTaken: false
3953 isReturnAddressTaken: false
3954 hasStackMap: false
3955 hasPatchPoint: false
3956 stackSize: 0
3957 offsetAdjustment: 0
3958 maxAlignment: 0
3959 adjustsStack: false
3960 hasCalls: false
3961 stackProtector: ''
3962 maxCallFrameSize: 4294967295
3963 hasOpaqueSPAdjustment: false
3964 hasVAStart: false
3965 hasMustTailInVarArgFunc: false
3966 savePoint: ''
3967 restorePoint: ''
3968 fixedStack:
3969 stack:
3970 constants:
3971 body: |
3972 bb.0.entry:
3973 liveins: %x3, %x4
3974
3975 %1 = COPY %x4
3976 %0 = LI8 200
3977 %2 = RLDICLo %0, 61, 3, implicit-def %cr0
3978 ; CHECK-NOT: ANDI
3979 ; CHECK-LATE-NOT: andi.
3980 %3 = COPY killed %cr0
3981 %4 = ISEL8 %1, %2, %3.sub_eq
3982 %x3 = COPY %4
3983 BLR8 implicit %lr8, implicit %rm, implicit %x3
3984
3985 ...
3986 ---
39163987 name: testRLDICLo3
39173988 # CHECK-ALL: name: testRLDICLo3
39183989 alignment: 4
42234294 ; CHECK: ANDIo %3, 234
42244295 ; CHECK-LATE: li 3, -22
42254296 ; CHECK-LATE: andi. 5, 3, 234
4297 %5 = COPY killed %cr0
4298 %6 = ISEL %2, %3, %5.sub_eq
4299 %8 = IMPLICIT_DEF
4300 %7 = INSERT_SUBREG %8, killed %6, 1
4301 %9 = RLDICL killed %7, 0, 32
4302 %x3 = COPY %9
4303 BLR8 implicit %lr8, implicit %rm, implicit %x3
4304
4305 ...
4306 ---
4307 name: testRLWINMo2
4308 # CHECK-ALL: name: testRLWINMo2
4309 alignment: 4
4310 exposesReturnsTwice: false
4311 legalized: false
4312 regBankSelected: false
4313 selected: false
4314 tracksRegLiveness: true
4315 registers:
4316 - { id: 0, class: g8rc, preferred-register: '' }
4317 - { id: 1, class: g8rc, preferred-register: '' }
4318 - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
4319 - { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' }
4320 - { id: 4, class: gprc, preferred-register: '' }
4321 - { id: 5, class: crrc, preferred-register: '' }
4322 - { id: 6, class: gprc, preferred-register: '' }
4323 - { id: 7, class: g8rc, preferred-register: '' }
4324 - { id: 8, class: g8rc, preferred-register: '' }
4325 - { id: 9, class: g8rc, preferred-register: '' }
4326 liveins:
4327 - { reg: '%x3', virtual-reg: '%0' }
4328 - { reg: '%x4', virtual-reg: '%1' }
4329 frameInfo:
4330 isFrameAddressTaken: false
4331 isReturnAddressTaken: false
4332 hasStackMap: false
4333 hasPatchPoint: false
4334 stackSize: 0
4335 offsetAdjustment: 0
4336 maxAlignment: 0
4337 adjustsStack: false
4338 hasCalls: false
4339 stackProtector: ''
4340 maxCallFrameSize: 4294967295
4341 hasOpaqueSPAdjustment: false
4342 hasVAStart: false
4343 hasMustTailInVarArgFunc: false
4344 savePoint: ''
4345 restorePoint: ''
4346 fixedStack:
4347 stack:
4348 constants:
4349 body: |
4350 bb.0.entry:
4351 liveins: %x3, %x4
4352
4353 %1 = COPY %x4
4354 %0 = COPY %x3
4355 %2 = COPY %1.sub_32
4356 %3 = LI -22
4357 %4 = RLWINMo %3, 5, 24, 31, implicit-def %cr0
4358 ; CHECK-NOT: ANDI
4359 ; CHECK-LATE-NOT: andi.
42264360 %5 = COPY killed %cr0
42274361 %6 = ISEL %2, %3, %5.sub_eq
42284362 %8 = IMPLICIT_DEF