llvm.org GIT mirror llvm / 0aba46f
ARM MachO: sort out isTargetDarwin/isTargetIOS/... checks. The ARM backend has been using most of the MachO related subtarget checks almost interchangeably, and since the only target it's had to run on has been IOS (which is all three of MachO, Darwin and IOS) it's worked out OK so far. But we'd like to support embedded targets under the "*-*-none-macho" triple, which means everything starts falling apart and inconsistent behaviours emerge. This patch should pick a reasonably sensible set of behaviours for the new triple (and any others that come along, with luck). Some choices were debatable (notably FP == r7 or r11), but we can revisit those later when deficiencies become apparent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198617 91177308-0d34-0410-b5e6-96231b3b80d8 Tim Northover 6 years ago
27 changed file(s) with 201 addition(s) and 94 deletion(s). Raw diff Collapse all Expand all
145145 assert(GV && "C++ constructor pointer was not a GlobalValue!");
146146
147147 const MCExpr *E = MCSymbolRefExpr::Create(getSymbol(GV),
148 (Subtarget->isTargetDarwin()
149 ? MCSymbolRefExpr::VK_None
150 : MCSymbolRefExpr::VK_ARM_TARGET1),
148 (Subtarget->isTargetELF()
149 ? MCSymbolRefExpr::VK_ARM_TARGET1
150 : MCSymbolRefExpr::VK_None),
151151 OutContext);
152152
153153 OutStreamer.EmitValue(E, Size);
439439 }
440440
441441 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
442 if (Subtarget->isTargetDarwin()) {
442 if (Subtarget->isTargetMachO()) {
443443 Reloc::Model RelocM = TM.getRelocationModel();
444444 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
445445 // Declare all the text sections up front (before the DWARF sections
514514
515515
516516 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
517 if (Subtarget->isTargetDarwin()) {
517 if (Subtarget->isTargetMachO()) {
518518 // All darwin targets use mach-o.
519519 const TargetLoweringObjectFileMachO &TLOFMacho =
520520 static_cast(getObjFileLowering());
782782
783783 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
784784 unsigned char TargetFlags) {
785 bool isIndirect = Subtarget->isTargetDarwin() &&
785 bool isIndirect = Subtarget->isTargetMachO() &&
786786 (TargetFlags & ARMII::MO_NONLAZY) &&
787787 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
788788 if (!isIndirect)
823823
824824 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
825825 // flag the global as MO_NONLAZY.
826 unsigned char TF = Subtarget->isTargetDarwin() ? ARMII::MO_NONLAZY : 0;
826 unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
827827 MCSym = GetARMGVSymbol(GV, TF);
828828 } else if (ACPV->isMachineBasicBlock()) {
829829 const MachineBasicBlock *MBB = cast(ACPV)->getMBB();
15351535 case ARM::TRAP: {
15361536 // Non-Darwin binutils don't yet support the "trap" mnemonic.
15371537 // FIXME: Remove this special case when they do.
1538 if (!Subtarget->isTargetDarwin()) {
1538 if (!Subtarget->isTargetMachO()) {
15391539 //.long 0xe7ffdefe @ trap
15401540 uint32_t Val = 0xe7ffdefeUL;
15411541 OutStreamer.AddComment("trap");
15541554 case ARM::tTRAP: {
15551555 // Non-Darwin binutils don't yet support the "trap" mnemonic.
15561556 // FIXME: Remove this special case when they do.
1557 if (!Subtarget->isTargetDarwin()) {
1557 if (!Subtarget->isTargetMachO()) {
15581558 //.short 57086 @ trap
15591559 uint16_t Val = 0xdefe;
15601560 OutStreamer.AddComment("trap");
102102
103103 virtual unsigned getISAEncoding() LLVM_OVERRIDE {
104104 // ARM/Darwin adds ISA to the DWARF info for each function.
105 if (!Subtarget->isTargetDarwin())
105 if (!Subtarget->isTargetMachO())
106106 return 0;
107107 return Subtarget->isThumb() ?
108108 ARM::DW_ISA_ARM_thumb : ARM::DW_ISA_ARM_arm;
4444
4545 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMSubtarget &sti)
4646 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti),
47 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
47 FramePtr((STI.isTargetMachO() || STI.isThumb()) ? ARM::R7 : ARM::R11),
4848 BasePtr(ARM::R6) {
4949 }
5050
674674 (const TargetRegisterClass*)&ARM::GPRRegClass;
675675 unsigned DestReg = createResultReg(RC);
676676
677 // FastISel TLS support on non-Darwin is broken, punt to SelectionDAG.
677 // FastISel TLS support on non-MachO is broken, punt to SelectionDAG.
678678 const GlobalVariable *GVar = dyn_cast(GV);
679679 bool IsThreadLocal = GVar && GVar->isThreadLocal();
680 if (!Subtarget->isTargetDarwin() && IsThreadLocal) return 0;
680 if (!Subtarget->isTargetMachO() && IsThreadLocal) return 0;
681681
682682 // Use movw+movt when possible, it avoids constant pool entries.
683683 // Non-darwin targets only support static movt relocations in FastISel.
684684 if (Subtarget->useMovt() &&
685 (Subtarget->isTargetDarwin() || RelocM == Reloc::Static)) {
685 (Subtarget->isTargetMachO() || RelocM == Reloc::Static)) {
686686 unsigned Opc;
687687 unsigned char TF = 0;
688 if (Subtarget->isTargetDarwin())
688 if (Subtarget->isTargetMachO())
689689 TF = ARMII::MO_NONLAZY;
690690
691691 switch (RelocM) {
31433143 const ARMSubtarget *Subtarget = &TM.getSubtarget();
31443144 // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
31453145 bool UseFastISel = false;
3146 UseFastISel |= Subtarget->isTargetIOS() && !Subtarget->isThumb1Only();
3146 UseFastISel |= Subtarget->isTargetMachO() && !Subtarget->isThumb1Only();
31473147 UseFastISel |= Subtarget->isTargetLinux() && !Subtarget->isThumb();
31483148 UseFastISel |= Subtarget->isTargetNaCl() && !Subtarget->isThumb();
31493149
194194 case ARM::R12:
195195 if (Reg == FramePtr)
196196 FramePtrSpillFI = FI;
197 if (STI.isTargetIOS())
197 if (STI.isTargetMachO())
198198 GPRCS2Size += 4;
199199 else
200200 GPRCS1Size += 4;
453453 // Jump to label or value in register.
454454 if (RetOpcode == ARM::TCRETURNdi) {
455455 unsigned TCOpcode = STI.isThumb() ?
456 (STI.isTargetIOS() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) :
456 (STI.isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) :
457457 ARM::TAILJMPd;
458458 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
459459 if (JumpTarget.isGlobal())
598598 unsigned LastReg = 0;
599599 for (; i != 0; --i) {
600600 unsigned Reg = CSI[i-1].getReg();
601 if (!(Func)(Reg, STI.isTargetIOS())) continue;
601 if (!(Func)(Reg, STI.isTargetMachO())) continue;
602602
603603 // D-registers in the aligned area DPRCS2 are NOT spilled here.
604604 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
671671 bool DeleteRet = false;
672672 for (; i != 0; --i) {
673673 unsigned Reg = CSI[i-1].getReg();
674 if (!(Func)(Reg, STI.isTargetIOS())) continue;
674 if (!(Func)(Reg, STI.isTargetMachO())) continue;
675675
676676 // The aligned reloads from area DPRCS2 are not inserted here.
677677 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
12201220 if (Spilled) {
12211221 NumGPRSpills++;
12221222
1223 if (!STI.isTargetIOS()) {
1223 if (!STI.isTargetMachO()) {
12241224 if (Reg == ARM::LR)
12251225 LRSpilled = true;
12261226 CS1Spilled = true;
12421242 break;
12431243 }
12441244 } else {
1245 if (!STI.isTargetIOS()) {
1245 if (!STI.isTargetMachO()) {
12461246 UnspilledCS1GPRs.push_back(Reg);
12471247 continue;
12481248 }
160160 }
161161
162162 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
163 if (TM.getSubtarget().isTargetDarwin())
163 if (TM.getSubtarget().isTargetMachO())
164164 return new TargetLoweringObjectFileMachO();
165165
166166 return new ARMElfTargetObjectFile();
174174
175175 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
176176
177 if (Subtarget->isTargetIOS()) {
177 if (Subtarget->isTargetMachO()) {
178178 // Uses VFP for Thumb libfuncs if available.
179179 if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
180180 Subtarget->hasARMOps()) {
257257 setLibcallName(RTLIB::SRL_I128, 0);
258258 setLibcallName(RTLIB::SRA_I128, 0);
259259
260 if (Subtarget->isAAPCS_ABI() && !Subtarget->isTargetDarwin()) {
260 if (Subtarget->isAAPCS_ABI() && !Subtarget->isTargetMachO()) {
261261 // Double-precision floating-point arithmetic helper functions
262262 // RTABI chapter 4.1.2, Table 2
263263 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
732732 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
733733 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
734734
735 if (!Subtarget->isTargetDarwin()) {
736 // Non-Darwin platforms may return values in these registers via the
735 if (!Subtarget->isTargetMachO()) {
736 // Non-MachO platforms may return values in these registers via the
737737 // personality function.
738738 setExceptionPointerRegister(ARM::R0);
739739 setExceptionSelectorRegister(ARM::R1);
16931693 const GlobalValue *GV = G->getGlobal();
16941694 isDirect = true;
16951695 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1696 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1696 bool isStub = (isExt && Subtarget->isTargetMachO()) &&
16971697 getTargetMachine().getRelocationModel() != Reloc::Static;
16981698 isARMFunc = !Subtarget->isThumb() || isStub;
16991699 // ARM call to a local ARM function is predicable.
17001700 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
17011701 // tBX takes a register source operand.
17021702 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1703 assert(Subtarget->isTargetDarwin() && "WrapperPIC use on non-Darwin?");
1703 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?");
17041704 Callee = DAG.getNode(ARMISD::WrapperPIC, dl, getPointerTy(),
17051705 DAG.getTargetGlobalAddress(GV, dl, getPointerTy()));
17061706 } else {
17131713 }
17141714 } else if (ExternalSymbolSDNode *S = dyn_cast(Callee)) {
17151715 isDirect = true;
1716 bool isStub = Subtarget->isTargetDarwin() &&
1716 bool isStub = Subtarget->isTargetMachO() &&
17171717 getTargetMachine().getRelocationModel() != Reloc::Static;
17181718 isARMFunc = !Subtarget->isThumb() || isStub;
17191719 // tBX takes a register source operand.
37773777 EVT VT = Op.getValueType();
37783778 SDLoc dl(Op); // FIXME probably not meaningful
37793779 unsigned Depth = cast(Op.getOperand(0))->getZExtValue();
3780 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
3780 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetMachO())
37813781 ? ARM::R7 : ARM::R11;
37823782 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
37833783 while (Depth--)
60646064 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
60656065 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
60666066 case ISD::GlobalAddress:
6067 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
6067 return Subtarget->isTargetMachO() ? LowerGlobalAddressDarwin(Op, DAG) :
60686068 LowerGlobalAddressELF(Op, DAG);
60696069 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
60706070 case ISD::SELECT: return LowerSELECT(Op, DAG);
259259 AssemblerPredicate<"!ModeThumb", "arm-mode">;
260260 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
261261 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
262 def IsMachO : Predicate<"Subtarget->isTargetMachO()">;
263 def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">;
262264 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
263265 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
264266 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
544544 (tBX GPR:$dst, (ops 14, zero_reg))>,
545545 Requires<[IsThumb]>, Sched<[WriteBr]>;
546546 }
547 // tTAILJMPd: IOS version uses a Thumb2 branch (no Thumb1 tail calls
548 // on IOS), so it's in ARMInstrThumb2.td.
549 // Non-IOS version:
547 // tTAILJMPd: MachO version uses a Thumb2 branch (no Thumb1 tail calls
548 // on MachO), so it's in ARMInstrThumb2.td.
549 // Non-MachO version:
550550 let Uses = [SP] in {
551551 def tTAILJMPdND : tPseudoExpand<(outs),
552552 (ins t_brtarget:$dst, pred:$p),
553553 4, IIC_Br, [],
554554 (tB t_brtarget:$dst, pred:$p)>,
555 Requires<[IsThumb, IsNotIOS]>, Sched<[WriteBr]>;
555 Requires<[IsThumb, IsNotMachO]>, Sched<[WriteBr]>;
556556 }
557557 }
558558
35483548 let AsmMatchConverter = "cvtThumbBranches";
35493549 }
35503550
3551 // Tail calls. The IOS version of thumb tail calls uses a t2 branch, so
3551 // Tail calls. The MachO version of thumb tail calls uses a t2 branch, so
35523552 // it goes here.
35533553 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
35543554 // IOS version.
35573557 (ins uncondbrtarget:$dst, pred:$p),
35583558 4, IIC_Br, [],
35593559 (t2B uncondbrtarget:$dst, pred:$p)>,
3560 Requires<[IsThumb2, IsIOS]>, Sched<[WriteBr]>;
3560 Requires<[IsThumb2, IsMachO]>, Sched<[WriteBr]>;
35613561 }
35623562
35633563 // IT block
144144 SDValue Src, SDValue Size,
145145 unsigned Align, bool isVolatile,
146146 MachinePointerInfo DstPtrInfo) const {
147 // Use default for non-AAPCS (or Darwin) subtargets
148 if (!Subtarget->isAAPCS_ABI() || Subtarget->isTargetDarwin())
147 // Use default for non-AAPCS (or MachO) subtargets
148 if (!Subtarget->isAAPCS_ABI() || Subtarget->isTargetMachO())
149149 return SDValue();
150150
151151 const ARMTargetLowering &TLI =
195195 case Triple::EABIHF:
196196 case Triple::GNUEABI:
197197 case Triple::GNUEABIHF:
198 case Triple::MachO:
198199 TargetABI = ARM_ABI_AAPCS;
199200 break;
200201 default:
211212
212213 UseMovt = hasV6T2Ops() && ArmUseMOVT;
213214
214 if (!isTargetIOS()) {
215 if (isTargetMachO()) {
216 IsR9Reserved = ReserveR9 | !HasV6Ops;
217 SupportsTailCall = !isTargetIOS() || !getTargetTriple().isOSVersionLT(5, 0);
218 } else
215219 IsR9Reserved = ReserveR9;
216 } else {
217 IsR9Reserved = ReserveR9 | !HasV6Ops;
218 SupportsTailCall = !getTargetTriple().isOSVersionLT(5, 0);
219 }
220220
221221 if (!isThumb() || hasThumb2())
222222 PostRAScheduler = true;
238238 // The above behavior is consistent with GCC.
239239 AllowsUnalignedMem = (
240240 (hasV7Ops() && (isTargetLinux() || isTargetNaCl())) ||
241 (hasV6Ops() && isTargetDarwin()));
241 (hasV6Ops() && isTargetMachO()));
242242 break;
243243 case StrictAlign:
244244 AllowsUnalignedMem = false;
280280 if (GV->isDeclaration() && !GV->isMaterializable())
281281 isDecl = true;
282282
283 if (!isTargetDarwin()) {
283 if (!isTargetMachO()) {
284284 // Extra load is needed for all externally visible.
285285 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
286286 return false;
310310 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
311311 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
312312 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
313
313314 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
315 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
316
314317 // ARM EABI is the bare-metal EABI described in ARM ABI documents and
315318 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
316319 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
2525 #include "llvm/MC/MCAsmInfo.h"
2626 #include "llvm/MC/MCAssembler.h"
2727 #include "llvm/MC/MCContext.h"
28 #include "llvm/MC/MCDisassembler.h"
2829 #include "llvm/MC/MCELFStreamer.h"
2930 #include "llvm/MC/MCExpr.h"
3031 #include "llvm/MC/MCInst.h"
3839 #include "llvm/MC/MCStreamer.h"
3940 #include "llvm/MC/MCSubtargetInfo.h"
4041 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/Support/Debug.h"
4143 #include "llvm/Support/ELF.h"
4244 #include "llvm/Support/MathExtras.h"
4345 #include "llvm/Support/SourceMgr.h"
664664 StringRef TT, StringRef CPU) {
665665 Triple TheTriple(TT);
666666
667 if (TheTriple.isOSDarwin()) {
667 if (TheTriple.isOSBinFormatMachO()) {
668668 MachO::CPUSubTypeARM CS =
669669 StringSwitch(TheTriple.getArchName())
670670 .Cases("armv4t", "thumbv4t", MachO::CPU_SUBTYPE_ARM_V4T)
5555 bool isThumb2() const {
5656 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
5757 }
58 bool isTargetDarwin() const {
58 bool isTargetMachO() const {
5959 Triple TT(STI.getTargetTriple());
60 return TT.isOSDarwin();
60 return TT.isOSBinFormatMachO();
6161 }
6262
6363 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
914914 switch (ARM16Expr->getKind()) {
915915 default: llvm_unreachable("Unsupported ARMFixup");
916916 case ARMMCExpr::VK_ARM_HI16:
917 if (!isTargetDarwin() && EvaluateAsPCRel(E))
917 if (!isTargetMachO() && EvaluateAsPCRel(E))
918918 Kind = MCFixupKind(isThumb2()
919919 ? ARM::fixup_t2_movt_hi16_pcrel
920920 : ARM::fixup_arm_movt_hi16_pcrel);
924924 : ARM::fixup_arm_movt_hi16);
925925 break;
926926 case ARMMCExpr::VK_ARM_LO16:
927 if (!isTargetDarwin() && EvaluateAsPCRel(E))
927 if (!isTargetMachO() && EvaluateAsPCRel(E))
928928 Kind = MCFixupKind(isThumb2()
929929 ? ARM::fixup_t2_movw_lo16_pcrel
930930 : ARM::fixup_arm_movw_lo16_pcrel);
941941 // it's just a plain immediate expression, and those evaluate to
942942 // the lower 16 bits of the expression regardless of whether
943943 // we have a movt or a movw.
944 if (!isTargetDarwin() && EvaluateAsPCRel(E))
944 if (!isTargetMachO() && EvaluateAsPCRel(E))
945945 Kind = MCFixupKind(isThumb2()
946946 ? ARM::fixup_t2_movw_lo16_pcrel
947947 : ARM::fixup_arm_movw_lo16_pcrel);
211211 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
212212 Triple TheTriple(TT);
213213
214 if (TheTriple.isOSDarwin())
214 if (TheTriple.isOSBinFormatMachO())
215215 return new ARMMCAsmInfoDarwin();
216216
217217 return new ARMELFMCAsmInfo();
239239 bool NoExecStack) {
240240 Triple TheTriple(TT);
241241
242 if (TheTriple.isOSDarwin())
242 if (TheTriple.isOSBinFormatMachO())
243243 return createMachOStreamer(Ctx, MAB, OS, Emitter, false);
244244
245245 if (TheTriple.isOSWindows()) {
134134 case ARM::R11:
135135 if (Reg == FramePtr)
136136 FramePtrSpillFI = FI;
137 if (STI.isTargetIOS())
137 if (STI.isTargetMachO())
138138 GPRCS2Size += 4;
139139 else
140140 GPRCS1Size += 4;
802802 StringRef CPU) {
803803 Triple TheTriple(TT);
804804
805 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
805 if (TheTriple.isOSBinFormatMachO())
806806 return new DarwinX86_32AsmBackend(T, MRI, CPU,
807807 TheTriple.isMacOSX() &&
808808 !TheTriple.isMacOSXVersionLT(10, 7));
820820 StringRef CPU) {
821821 Triple TheTriple(TT);
822822
823 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) {
823 if (TheTriple.isOSBinFormatMachO()) {
824824 MachO::CPUSubTypeX86 CS =
825825 StringSwitch(TheTriple.getArchName())
826826 .Case("x86_64h", MachO::CPU_SUBTYPE_X86_64_H)
267267 bool is64Bit = TheTriple.getArch() == Triple::x86_64;
268268
269269 MCAsmInfo *MAI;
270 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) {
270 if (TheTriple.isOSBinFormatMachO()) {
271271 if (is64Bit)
272272 MAI = new X86_64MCAsmInfoDarwin(TheTriple);
273273 else
361361 bool NoExecStack) {
362362 Triple TheTriple(TT);
363363
364 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
364 if (TheTriple.isOSBinFormatMachO())
365365 return createMachOStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll);
366366
367367 if (TheTriple.isOSWindows() && TheTriple.getEnvironment() != Triple::ELF)
None ; RUN: llc -mtriple=thumbv6m-apple-darwin-eabi -relocation-model=pic -o - %s | FileCheck %s --check-prefix=CHECK-THUMB-PIC
1 ; RUN: llc -mtriple=arm-apple-darwin-eabi -relocation-model=pic -o - %s | FileCheck %s --check-prefix=CHECK-ARM-PIC
2 ; RUN: llc -mtriple=thumbv6m-apple-darwin-eabi -relocation-model=dynamic-no-pic -o - %s | FileCheck %s --check-prefix=CHECK-DYNAMIC
3 ; RUN: llc -mtriple=arm-apple-darwin-eabi -relocation-model=dynamic-no-pic -o - %s | FileCheck %s --check-prefix=CHECK-DYNAMIC
4 ; RUN: llc -mtriple=thumbv6m-apple-darwin-eabi -relocation-model=static -o - %s | FileCheck %s --check-prefix=CHECK-STATIC
5 ; RUN: llc -mtriple=arm-apple-darwin-eabi -relocation-model=static -o - %s | FileCheck %s --check-prefix=CHECK-STATIC
0 ; RUN: llc -mtriple=thumbv6m-apple-none-macho -relocation-model=pic -o - %s | FileCheck %s --check-prefix=CHECK-THUMB-PIC
1 ; RUN: llc -mtriple=arm-apple-none-macho -relocation-model=pic -o - %s | FileCheck %s --check-prefix=CHECK-ARM-PIC
2 ; RUN: llc -mtriple=thumbv6m-apple-none-macho -relocation-model=dynamic-no-pic -o - %s | FileCheck %s --check-prefix=CHECK-DYNAMIC
3 ; RUN: llc -mtriple=arm-apple-none-macho -relocation-model=dynamic-no-pic -o - %s | FileCheck %s --check-prefix=CHECK-DYNAMIC
4 ; RUN: llc -mtriple=thumbv6m-apple-none-macho -relocation-model=static -o - %s | FileCheck %s --check-prefix=CHECK-STATIC
5 ; RUN: llc -mtriple=arm-apple-none-macho -relocation-model=static -o - %s | FileCheck %s --check-prefix=CHECK-STATIC
66 @var = global [16 x i32] zeroinitializer
77
88 declare void @bar(i32*)
None ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-apple-darwin
1 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-linux-gnueabi
0 ; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=thumbv7-apple-darwin
1 ; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=armv7-linux-gnueabi
22 ; rdar://9515076
33 ; (Make sure this doesn't crash.)
44
None ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=DARWIN-ARM
0 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=DARWIN-ARM
11 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=LINUX-ARM
2 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=DARWIN-THUMB2
2 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=DARWIN-THUMB2
33 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-linux-gnueabi | FileCheck %s --check-prefix=LINUX-THUMB2
44
55 define i8* @frameaddr_index0() nounwind {
3333 ; DARWIN-ARM-LABEL: frameaddr_index1:
3434 ; DARWIN-ARM: push {r7}
3535 ; DARWIN-ARM: mov r7, sp
36 ; DARWIN-ARM: mov r0, r7
37 ; DARWIN-ARM: ldr r0, [r0]
36 ; DARWIN-ARM: ldr r0, [r7]
3837
3938 ; DARWIN-THUMB2-LABEL: frameaddr_index1:
4039 ; DARWIN-THUMB2: str r7, [sp, #-4]!
4140 ; DARWIN-THUMB2: mov r7, sp
42 ; DARWIN-THUMB2: mov r0, r7
43 ; DARWIN-THUMB2: ldr r0, [r0]
41 ; DARWIN-THUMB2: ldr r0, [r7]
4442
4543 ; LINUX-ARM-LABEL: frameaddr_index1:
4644 ; LINUX-ARM: push {r11}
6260 ; DARWIN-ARM-LABEL: frameaddr_index3:
6361 ; DARWIN-ARM: push {r7}
6462 ; DARWIN-ARM: mov r7, sp
65 ; DARWIN-ARM: mov r0, r7
66 ; DARWIN-ARM: ldr r0, [r0]
63 ; DARWIN-ARM: ldr r0, [r7]
6764 ; DARWIN-ARM: ldr r0, [r0]
6865 ; DARWIN-ARM: ldr r0, [r0]
6966
7067 ; DARWIN-THUMB2-LABEL: frameaddr_index3:
7168 ; DARWIN-THUMB2: str r7, [sp, #-4]!
7269 ; DARWIN-THUMB2: mov r7, sp
73 ; DARWIN-THUMB2: mov r0, r7
74 ; DARWIN-THUMB2: ldr r0, [r0]
70 ; DARWIN-THUMB2: ldr r0, [r7]
7571 ; DARWIN-THUMB2: ldr r0, [r0]
7672 ; DARWIN-THUMB2: ldr r0, [r0]
7773
None ; RUN: llc -mtriple=thumbv7-apple-darwin-eabi < %s | FileCheck %s
1 ; RUN: llc -mtriple=thumbv6m-apple-darwin-eabi -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-T1
0 ; RUN: llc -mtriple=thumbv7-apple-none-macho < %s | FileCheck %s
1 ; RUN: llc -mtriple=thumbv6m-apple-none-macho -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-T1
22 ; RUN: llc -mtriple=thumbv7-apple-darwin-ios -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-IOS
33
44
1010
1111 define void @check_simple() minsize {
1212 ; CHECK-LABEL: check_simple:
13 ; CHECK: push.w {r7, r8, r9, r10, r11, lr}
13 ; CHECK: push {r3, r4, r5, r6, r7, lr}
1414 ; CHECK-NOT: sub sp, sp,
1515 ; ...
1616 ; CHECK-NOT: add sp, sp,
17 ; CHECK: pop.w {r0, r1, r2, r3, r11, pc}
17 ; CHECK: pop {r0, r1, r2, r3, r7, pc}
1818
1919 ; CHECK-T1-LABEL: check_simple:
2020 ; CHECK-T1: push {r3, r4, r5, r6, r7, lr}
4242
4343 define void @check_simple_too_big() minsize {
4444 ; CHECK-LABEL: check_simple_too_big:
45 ; CHECK: push.w {r11, lr}
45 ; CHECK: push {r7, lr}
4646 ; CHECK: sub sp,
4747 ; ...
4848 ; CHECK: add sp,
49 ; CHECK: pop.w {r11, pc}
49 ; CHECK: pop {r7, pc}
5050 %var = alloca i8, i32 64
5151 call void @bar(i8* %var)
5252 ret void
9191 ; folded in except that doing so would clobber the value being returned.
9292 define i64 @check_no_return_clobber() minsize {
9393 ; CHECK-LABEL: check_no_return_clobber:
94 ; CHECK: push.w {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, lr}
94 ; CHECK: push {r1, r2, r3, r4, r5, r6, r7, lr}
9595 ; CHECK-NOT: sub sp,
9696 ; ...
97 ; CHECK: add sp, #40
98 ; CHECK: pop.w {r11, pc}
97 ; CHECK: add sp, #24
98 ; CHECK: pop {r7, pc}
9999
100100 ; Just to keep iOS FileCheck within previous function:
101101 ; CHECK-IOS-LABEL: check_no_return_clobber:
102102
103 %var = alloca i8, i32 40
103 %var = alloca i8, i32 20
104104 call void @bar(i8* %var)
105105 ret i64 0
106106 }
160160 ; We want the epilogue to be the only thing in a basic block so that we hit
161161 ; the correct edge-case (first inst in block is correct one to adjust).
162162 ret void
163 }
163 }
0 ; RUN: llc -mtriple=arm-none-none-eabi -mcpu=cortex-a15 -o - %s | FileCheck --check-prefix=CHECK-A %s
11 ; RUN: llc -mtriple=thumb-none-none-eabi -mcpu=cortex-a15 -o - %s | FileCheck --check-prefix=CHECK-A-THUMB %s
2 ; RUN: llc -mtriple=thumb-apple-darwin -mcpu=cortex-m3 -o - %s | FileCheck --check-prefix=CHECK-M %s
2 ; RUN: llc -mtriple=thumb-apple-none-macho -mcpu=cortex-m3 -o - %s | FileCheck --check-prefix=CHECK-M %s
33
44 declare arm_aapcscc void @bar()
55
3333
3434 ; Normal AAPCS function (r0-r3 pushed onto stack by hardware, lr set to
3535 ; appropriate sentinel so no special return needed).
36 ; CHECK-M-LABEL: irq_fn:
3637 ; CHECK-M: push {r4, r7, lr}
3738 ; CHECK-M: add r7, sp, #4
38 ; CHECK-M: sub sp, #4
3939 ; CHECK-M: mov r4, sp
40 ; CHECK-M: bic r4, r4, #7
4041 ; CHECK-M: mov sp, r4
4142 ; CHECK-M: blx _bar
4243 ; CHECK-M: subs r4, r7, #4
6061 ; CHECK-A: pop {r0, r1, r2, r3, r4, r5, r6, r7, r11, lr}
6162 ; CHECK-A: subs pc, lr, #4
6263
64 ; CHECK-A-THUMB-LABEL: fiq_fn:
65 ; CHECK-M-LABEL: fiq_fn:
6366 %val = load volatile [16 x i32]* @bigvar
6467 store volatile [16 x i32] %val, [16 x i32]* @bigvar
6568 ret void
None ; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
1 ; RUN: llc < %s -mtriple=armv4t-apple-darwin | FileCheck %s -check-prefix=V4T
0 ; RUN: llc < %s -mtriple=armv7-apple-ios3.0 | FileCheck %s
1 ; RUN: llc < %s -mtriple=armv4t-apple-ios3.0 | FileCheck %s -check-prefix=V4T
22
33 @X = external global [0 x i32] ; <[0 x i32]*> [#uses=5]
44
0 ; RUN: llc < %s -mtriple=armv7-apple-ios -o - | FileCheck %s
1 ; RUN: llc < %s -mtriple=thumbv7m-darwin-eabi -o - | FileCheck %s --check-prefix=DARWIN
1 ; RUN: llc < %s -mtriple=thumbv7m-none-macho -o - | FileCheck %s --check-prefix=DARWIN
22 ; RUN: llc < %s -mtriple=arm-none-eabi -o - | FileCheck --check-prefix=EABI %s
33 ; RUN: llc < %s -mtriple=arm-none-eabihf -o - | FileCheck --check-prefix=EABI %s
44
0 ; RUN: llc -mtriple=thumbv7m-none-macho %s -o - -relocation-model=pic -disable-fp-elim | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NON-FAST
1 ; RUN: llc -mtriple=thumbv7m-none-macho -O0 %s -o - -relocation-model=pic -disable-fp-elim | FileCheck %s
2 ; RUN: llc -mtriple=thumbv7m-none-macho -filetype=obj %s -o /dev/null
3
4 ; Bare-metal should probably "declare" segments just like normal MachO
5 ; CHECK: __picsymbolstub4
6 ; CHECK: __StaticInit
7 ; CHECK: __text
8
9 @var = external global i32
10
11 define i32 @test_litpool() minsize {
12 ; CHECK-LABEL: test_litpool:
13 %val = load i32* @var
14 ret i32 %val
15
16 ; Lit-pool entries need to produce a "$non_lazy_ptr" version of the symbol.
17 ; CHECK: LCPI0_0:
18 ; CHECK-NEXT: .long L_var$non_lazy_ptr-(LPC0_0+4)
19 }
20
21 define i32 @test_movw_movt() {
22 ; CHECK-LABEL: test_movw_movt:
23 %val = load i32* @var
24 ret i32 %val
25
26 ; movw/movt should also address their symbols MachO-style
27 ; CHECK: movw [[RTMP:r[0-9]+]], :lower16:(L_var$non_lazy_ptr-(LPC1_0+4))
28 ; CHECK: movt [[RTMP]], :upper16:(L_var$non_lazy_ptr-(LPC1_0+4))
29 ; CHECK: LPC1_0:
30 ; CHECK: add [[RTMP]], pc
31 }
32
33 declare void @llvm.trap()
34
35 define void @test_trap() {
36 ; CHECK-LABEL: test_trap:
37
38 ; Bare-metal MachO gets compiled on top of normal MachO toolchain which
39 ; understands trap natively.
40 call void @llvm.trap()
41 ; CHECK: trap
42
43 ret void
44 }
45
46 define i32 @test_frame_ptr() {
47 ; CHECK-LABEL: test_frame_ptr:
48 call void @test_trap()
49
50 ; Frame pointer is r7 as for Darwin
51 ; CHECK: mov r7, sp
52 ret i32 42
53 }
54
55 %big_arr = type [8 x i32]
56 define void @test_two_areas(%big_arr* %addr) {
57 ; CHECK-LABEL: test_two_areas:
58 %val = load %big_arr* %addr
59 call void @test_trap()
60 store %big_arr %val, %big_arr* %addr
61
62 ; This goes with the choice of r7 as FP (largely). FP and LR have to be stored
63 ; consecutively on the stack for the frame record to be valid, which means we
64 ; need the 2 register-save areas employed by iOS.
65 ; CHECK-NON-FAST: push {r4, r5, r6, r7, lr}
66 ; CHECK-NON-FAST: push.w {r8, r9, r10, r11}
67 ; ...
68 ; CHECK-NON-FAST: pop.w {r8, r9, r10, r11}
69 ; CHECK-NON-FAST: pop {r4, r5, r6, r7, pc}
70 ret void
71 }
72
73 define void @test_tail_call() {
74 ; CHECK-LABEL: test_tail_call:
75 tail call void @test_trap()
76
77 ; Tail calls should be available and use Thumb2 branch.
78 ; CHECK: b.w _test_trap
79 ret void
80 }
81
82 define float @test_softfloat_calls(float %in) {
83 ; CHECK-LABEL: test_softfloat_calls:
84 %sum = fadd float %in, %in
85
86 ; Soft-float calls should be GNU-style rather than RTABI and should not be the
87 ; *vfp variants used for ARMv6 iOS.
88 ; CHECK: blx ___addsf3{{$}}
89 ret float %sum
90 }
91
92 ; Even bare-metal PIC needs GOT-like behaviour, in principle. Depends a bit on
93 ; the use-case of course, but LLVM doesn't know what that is.
94 ; CHECK: non_lazy_symbol_pointers
95 ; CHECK: L_var$non_lazy_ptr:
96 ; CHECK-NEXT: .indirect_symbol _var
97
98 ; All MachO objects should have this to give the linker leeway in removing
99 ; dead code.
100 ; CHECK: .subsections_via_symbols