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[ARM] Add new system registers to ARMv8-M Baseline/Mainline This patch was originally committed as r257884, but was reverted due to windows failures. The cause of these failures has been fixed under r258677, hence re-committing the original patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@258682 91177308-0d34-0410-b5e6-96231b3b80d8 Bradley Smith 4 years ago
8 changed file(s) with 529 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
34433443 .Case("basepri_max", 0x12)
34443444 .Case("faultmask", 0x13)
34453445 .Case("control", 0x14)
3446 .Case("msplim", 0x0a)
3447 .Case("psplim", 0x0b)
3448 .Case("sp", 0x18)
34463449 .Default(-1);
34473450 }
34483451
34723475 if (!Subtarget->hasV7Ops() && SYSmvalue >= 0x11 && SYSmvalue <= 0x13)
34733476 return -1;
34743477
3478 if (Subtarget->has8MSecExt() && Flags.lower() == "ns") {
3479 Flags = "";
3480 SYSmvalue |= 0x80;
3481 }
3482
3483 if (!Subtarget->has8MSecExt() &&
3484 (SYSmvalue == 0xa || SYSmvalue == 0xb || SYSmvalue > 0x14))
3485 return -1;
3486
3487 if (!Subtarget->hasV8MMainlineOps() &&
3488 (SYSmvalue == 0x8a || SYSmvalue == 0x8b || SYSmvalue == 0x91 ||
3489 SYSmvalue == 0x93))
3490 return -1;
3491
34753492 // If it was a read then we won't be expecting flags and so at this point
34763493 // we can return the mask.
34773494 if (IsRead) {
3478 assert (Flags.empty() && "Unexpected flags for reading M class register.");
3479 return SYSmvalue;
3495 if (Flags.empty())
3496 return SYSmvalue;
3497 else
3498 return -1;
34803499 }
34813500
34823501 // We know we are now handling a write so need to get the mask for the flags.
36353654 // is an acceptable value, so check that a mask can be constructed from the
36363655 // string.
36373656 if (Subtarget->isMClass()) {
3638 int SYSmValue = getMClassRegisterMask(SpecialReg, "", true, Subtarget);
3657 StringRef Flags = "", Reg = SpecialReg;
3658 if (Reg.endswith("_ns")) {
3659 Flags = "ns";
3660 Reg = Reg.drop_back(3);
3661 }
3662
3663 int SYSmValue = getMClassRegisterMask(Reg, Flags, true, Subtarget);
36393664 if (SYSmValue == -1)
36403665 return nullptr;
36413666
37293754 return CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops);
37303755 }
37313756
3732 SmallVector Fields;
3733 StringRef(SpecialReg).split(Fields, '_', 1, false);
3734 std::string Reg = Fields[0].str();
3735 StringRef Flags = Fields.size() == 2 ? Fields[1] : "";
3757 std::pair Fields;
3758 Fields = StringRef(SpecialReg).rsplit('_');
3759 std::string Reg = Fields.first.str();
3760 StringRef Flags = Fields.second;
37363761
37373762 // If the target was M Class then need to validate the special register value
37383763 // and retrieve the mask for use in the instruction node.
270270 }
271271 bool hasV8MBaseline() const {
272272 return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps];
273 }
274 bool hasV8MMainline() const {
275 return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps];
276 }
277 bool has8MSecExt() const {
278 return getSTI().getFeatureBits()[ARM::Feature8MSecExt];
273279 }
274280 bool hasARM() const {
275281 return !getSTI().getFeatureBits()[ARM::FeatureNoARM];
40074013 .Case("basepri_max", 0x812)
40084014 .Case("faultmask", 0x813)
40094015 .Case("control", 0x814)
4016 .Case("msplim", 0x80a)
4017 .Case("psplim", 0x80b)
4018 .Case("msp_ns", 0x888)
4019 .Case("psp_ns", 0x889)
4020 .Case("msplim_ns", 0x88a)
4021 .Case("psplim_ns", 0x88b)
4022 .Case("primask_ns", 0x890)
4023 .Case("basepri_ns", 0x891)
4024 .Case("basepri_max_ns", 0x892)
4025 .Case("faultmask_ns", 0x893)
4026 .Case("control_ns", 0x894)
4027 .Case("sp_ns", 0x898)
40104028 .Default(~0U);
40114029
40124030 if (FlagsVal == ~0U)
40194037
40204038 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
40214039 // basepri, basepri_max and faultmask only valid for V7m.
4040 return MatchOperand_NoMatch;
4041
4042 if (!has8MSecExt() && (FlagsVal == 0x80a || FlagsVal == 0x80b ||
4043 (FlagsVal > 0x814 && FlagsVal < 0xc00)))
4044 return MatchOperand_NoMatch;
4045
4046 if (!hasV8MMainline() && (FlagsVal == 0x88a || FlagsVal == 0x88b ||
4047 (FlagsVal > 0x890 && FlagsVal <= 0x893)))
40224048 return MatchOperand_NoMatch;
40234049
40244050 Parser.Lex(); // Eat identifier token.
41184118 // Values basepri, basepri_max and faultmask are only valid for v7m.
41194119 return MCDisassembler::Fail;
41204120 break;
4121 case 0x8a: // msplim_ns
4122 case 0x8b: // psplim_ns
4123 case 0x91: // basepri_ns
4124 case 0x92: // basepri_max_ns
4125 case 0x93: // faultmask_ns
4126 if (!(FeatureBits[ARM::HasV8MMainlineOps]))
4127 return MCDisassembler::Fail;
4128 // fall through
4129 case 10: // msplim
4130 case 11: // psplim
4131 case 0x88: // msp_ns
4132 case 0x89: // psp_ns
4133 case 0x90: // primask_ns
4134 case 0x94: // control_ns
4135 case 0x98: // sp_ns
4136 if (!(FeatureBits[ARM::Feature8MSecExt]))
4137 return MCDisassembler::Fail;
4138 break;
41214139 default:
41224140 return MCDisassembler::Fail;
41234141 }
928928 case 20:
929929 O << "control";
930930 return;
931 case 10:
932 O << "msplim";
933 return;
934 case 11:
935 O << "psplim";
936 return;
937 case 0x88:
938 O << "msp_ns";
939 return;
940 case 0x89:
941 O << "psp_ns";
942 return;
943 case 0x8a:
944 O << "msplim_ns";
945 return;
946 case 0x8b:
947 O << "psplim_ns";
948 return;
949 case 0x90:
950 O << "primask_ns";
951 return;
952 case 0x91:
953 O << "basepri_ns";
954 return;
955 case 0x92:
956 O << "basepri_max_ns";
957 return;
958 case 0x93:
959 O << "faultmask_ns";
960 return;
961 case 0x94:
962 O << "control_ns";
963 return;
964 case 0x98:
965 O << "sp_ns";
966 return;
931967 }
932968 }
933969
0 ; RUN: not llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=V7M
1 ; RUN: llc < %s -mtriple=thumbv8m.base-none-eabi 2>&1 | FileCheck %s
2
3 ; V7M: LLVM ERROR: Invalid register name "sp_ns".
4
5 define i32 @read_mclass_registers() nounwind {
6 entry:
7 ; CHECK-LABEL: read_mclass_registers:
8 ; CHECK: mrs r0, apsr
9 ; CHECK: mrs r1, iapsr
10 ; CHECK: mrs r1, eapsr
11 ; CHECK: mrs r1, xpsr
12 ; CHECK: mrs r1, ipsr
13 ; CHECK: mrs r1, epsr
14 ; CHECK: mrs r1, iepsr
15 ; CHECK: mrs r1, msp
16 ; CHECK: mrs r1, psp
17 ; CHECK: mrs r1, primask
18 ; CHECK: mrs r1, control
19 ; CHECK: mrs r1, msplim
20 ; CHECK: mrs r1, psplim
21 ; CHECK: mrs r1, msp_ns
22 ; CHECK: mrs r1, psp_ns
23 ; CHECK: mrs r1, primask_ns
24 ; CHECK: mrs r1, control_ns
25 ; CHECK: mrs r1, sp_ns
26
27 %0 = call i32 @llvm.read_register.i32(metadata !0)
28 %1 = call i32 @llvm.read_register.i32(metadata !4)
29 %add1 = add i32 %1, %0
30 %2 = call i32 @llvm.read_register.i32(metadata !8)
31 %add2 = add i32 %add1, %2
32 %3 = call i32 @llvm.read_register.i32(metadata !12)
33 %add3 = add i32 %add2, %3
34 %4 = call i32 @llvm.read_register.i32(metadata !16)
35 %add4 = add i32 %add3, %4
36 %5 = call i32 @llvm.read_register.i32(metadata !17)
37 %add5 = add i32 %add4, %5
38 %6 = call i32 @llvm.read_register.i32(metadata !18)
39 %add6 = add i32 %add5, %6
40 %7 = call i32 @llvm.read_register.i32(metadata !19)
41 %add7 = add i32 %add6, %7
42 %8 = call i32 @llvm.read_register.i32(metadata !20)
43 %add8 = add i32 %add7, %8
44 %9 = call i32 @llvm.read_register.i32(metadata !21)
45 %add9 = add i32 %add8, %9
46 %10 = call i32 @llvm.read_register.i32(metadata !25)
47 %add10 = add i32 %add9, %10
48 %11 = call i32 @llvm.read_register.i32(metadata !26)
49 %add11 = add i32 %add10, %11
50 %12 = call i32 @llvm.read_register.i32(metadata !27)
51 %add12 = add i32 %add11, %12
52 %13 = call i32 @llvm.read_register.i32(metadata !28)
53 %add13 = add i32 %add12, %13
54 %14 = call i32 @llvm.read_register.i32(metadata !29)
55 %add14 = add i32 %add13, %14
56 %15 = call i32 @llvm.read_register.i32(metadata !32)
57 %add15 = add i32 %add14, %15
58 %16 = call i32 @llvm.read_register.i32(metadata !35)
59 %add16 = add i32 %add15, %16
60 %17 = call i32 @llvm.read_register.i32(metadata !36)
61 %add17 = add i32 %add16, %17
62 ret i32 %add10
63 }
64
65 define void @write_mclass_registers(i32 %x) nounwind {
66 entry:
67 ; CHECK-LABEL: write_mclass_registers:
68 ; CHECK: msr apsr, r0
69 ; CHECK: msr apsr, r0
70 ; CHECK: msr iapsr, r0
71 ; CHECK: msr iapsr, r0
72 ; CHECK: msr eapsr, r0
73 ; CHECK: msr eapsr, r0
74 ; CHECK: msr xpsr, r0
75 ; CHECK: msr xpsr, r0
76 ; CHECK: msr ipsr, r0
77 ; CHECK: msr epsr, r0
78 ; CHECK: msr iepsr, r0
79 ; CHECK: msr msp, r0
80 ; CHECK: msr psp, r0
81 ; CHECK: msr primask, r0
82 ; CHECK: msr control, r0
83 ; CHECK: msr msplim, r0
84 ; CHECK: msr psplim, r0
85 ; CHECK: msr msp_ns, r0
86 ; CHECK: msr psp_ns, r0
87 ; CHECK: msr primask_ns, r0
88 ; CHECK: msr control_ns, r0
89 ; CHECK: msr sp_ns, r0
90
91 call void @llvm.write_register.i32(metadata !0, i32 %x)
92 call void @llvm.write_register.i32(metadata !1, i32 %x)
93 call void @llvm.write_register.i32(metadata !4, i32 %x)
94 call void @llvm.write_register.i32(metadata !5, i32 %x)
95 call void @llvm.write_register.i32(metadata !8, i32 %x)
96 call void @llvm.write_register.i32(metadata !9, i32 %x)
97 call void @llvm.write_register.i32(metadata !12, i32 %x)
98 call void @llvm.write_register.i32(metadata !13, i32 %x)
99 call void @llvm.write_register.i32(metadata !16, i32 %x)
100 call void @llvm.write_register.i32(metadata !17, i32 %x)
101 call void @llvm.write_register.i32(metadata !18, i32 %x)
102 call void @llvm.write_register.i32(metadata !19, i32 %x)
103 call void @llvm.write_register.i32(metadata !20, i32 %x)
104 call void @llvm.write_register.i32(metadata !21, i32 %x)
105 call void @llvm.write_register.i32(metadata !25, i32 %x)
106 call void @llvm.write_register.i32(metadata !26, i32 %x)
107 call void @llvm.write_register.i32(metadata !27, i32 %x)
108 call void @llvm.write_register.i32(metadata !28, i32 %x)
109 call void @llvm.write_register.i32(metadata !29, i32 %x)
110 call void @llvm.write_register.i32(metadata !32, i32 %x)
111 call void @llvm.write_register.i32(metadata !35, i32 %x)
112 call void @llvm.write_register.i32(metadata !36, i32 %x)
113 ret void
114 }
115
116 declare i32 @llvm.read_register.i32(metadata) nounwind
117 declare void @llvm.write_register.i32(metadata, i32) nounwind
118
119 !0 = !{!"apsr"}
120 !1 = !{!"apsr_nzcvq"}
121 !4 = !{!"iapsr"}
122 !5 = !{!"iapsr_nzcvq"}
123 !8 = !{!"eapsr"}
124 !9 = !{!"eapsr_nzcvq"}
125 !12 = !{!"xpsr"}
126 !13 = !{!"xpsr_nzcvq"}
127 !16 = !{!"ipsr"}
128 !17 = !{!"epsr"}
129 !18 = !{!"iepsr"}
130 !19 = !{!"msp"}
131 !20 = !{!"psp"}
132 !21 = !{!"primask"}
133 !25 = !{!"control"}
134 !26 = !{!"msplim"}
135 !27 = !{!"psplim"}
136 !28 = !{!"msp_ns"}
137 !29 = !{!"psp_ns"}
138 !32 = !{!"primask_ns"}
139 !35 = !{!"control_ns"}
140 !36 = !{!"sp_ns"}
141
0 ; RUN: not llc < %s -mtriple=thumbv8m.base-none-eabi 2>&1 | FileCheck %s --check-prefix=BASELINE
1 ; RUN: llc < %s -mtriple=thumbv8m.main-none-eabi -mattr=+dsp 2>&1 | FileCheck %s --check-prefix=MAINLINE
2
3 ; BASELINE: LLVM ERROR: Invalid register name "basepri_max_ns".
4
5 define i32 @read_mclass_registers() nounwind {
6 entry:
7 ; MAINLINE-LABEL: read_mclass_registers:
8 ; MAINLINE: mrs r0, apsr
9 ; MAINLINE: mrs r1, iapsr
10 ; MAINLINE: mrs r1, eapsr
11 ; MAINLINE: mrs r1, xpsr
12 ; MAINLINE: mrs r1, ipsr
13 ; MAINLINE: mrs r1, epsr
14 ; MAINLINE: mrs r1, iepsr
15 ; MAINLINE: mrs r1, msp
16 ; MAINLINE: mrs r1, psp
17 ; MAINLINE: mrs r1, primask
18 ; MAINLINE: mrs r1, basepri
19 ; MAINLINE: mrs r1, basepri_max
20 ; MAINLINE: mrs r1, faultmask
21 ; MAINLINE: mrs r1, control
22 ; MAINLINE: mrs r1, msplim
23 ; MAINLINE: mrs r1, psplim
24 ; MAINLINE: mrs r1, msp_ns
25 ; MAINLINE: mrs r1, psp_ns
26 ; MAINLINE: mrs r1, msplim_ns
27 ; MAINLINE: mrs r1, psplim_ns
28 ; MAINLINE: mrs r1, primask_ns
29 ; MAINLINE: mrs r1, basepri_ns
30 ; MAINLINE: mrs r1, faultmask_ns
31 ; MAINLINE: mrs r1, control_ns
32 ; MAINLINE: mrs r1, sp_ns
33 ; MAINLINE: mrs r1, basepri_max_ns
34
35 %0 = call i32 @llvm.read_register.i32(metadata !0)
36 %1 = call i32 @llvm.read_register.i32(metadata !4)
37 %add1 = add i32 %1, %0
38 %2 = call i32 @llvm.read_register.i32(metadata !8)
39 %add2 = add i32 %add1, %2
40 %3 = call i32 @llvm.read_register.i32(metadata !12)
41 %add3 = add i32 %add2, %3
42 %4 = call i32 @llvm.read_register.i32(metadata !16)
43 %add4 = add i32 %add3, %4
44 %5 = call i32 @llvm.read_register.i32(metadata !17)
45 %add5 = add i32 %add4, %5
46 %6 = call i32 @llvm.read_register.i32(metadata !18)
47 %add6 = add i32 %add5, %6
48 %7 = call i32 @llvm.read_register.i32(metadata !19)
49 %add7 = add i32 %add6, %7
50 %8 = call i32 @llvm.read_register.i32(metadata !20)
51 %add8 = add i32 %add7, %8
52 %9 = call i32 @llvm.read_register.i32(metadata !21)
53 %add9 = add i32 %add8, %9
54 %10 = call i32 @llvm.read_register.i32(metadata !22)
55 %add10 = add i32 %add9, %10
56 %11 = call i32 @llvm.read_register.i32(metadata !23)
57 %add11 = add i32 %add10, %11
58 %12 = call i32 @llvm.read_register.i32(metadata !24)
59 %add12 = add i32 %add11, %12
60 %13 = call i32 @llvm.read_register.i32(metadata !25)
61 %add13 = add i32 %add12, %13
62 %14 = call i32 @llvm.read_register.i32(metadata !26)
63 %add14 = add i32 %add13, %14
64 %15 = call i32 @llvm.read_register.i32(metadata !27)
65 %add15 = add i32 %add14, %15
66 %16 = call i32 @llvm.read_register.i32(metadata !28)
67 %add16 = add i32 %add15, %16
68 %17 = call i32 @llvm.read_register.i32(metadata !29)
69 %add17 = add i32 %add16, %17
70 %18 = call i32 @llvm.read_register.i32(metadata !30)
71 %add18 = add i32 %add17, %18
72 %19 = call i32 @llvm.read_register.i32(metadata !31)
73 %add19 = add i32 %add18, %19
74 %20 = call i32 @llvm.read_register.i32(metadata !32)
75 %add20 = add i32 %add19, %20
76 %21 = call i32 @llvm.read_register.i32(metadata !33)
77 %add21 = add i32 %add20, %21
78 %22 = call i32 @llvm.read_register.i32(metadata !34)
79 %add22 = add i32 %add21, %22
80 %23 = call i32 @llvm.read_register.i32(metadata !35)
81 %add23 = add i32 %add22, %23
82 %24 = call i32 @llvm.read_register.i32(metadata !36)
83 %add24 = add i32 %add23, %24
84 %25 = call i32 @llvm.read_register.i32(metadata !37)
85 %add25 = add i32 %add24, %25
86 ret i32 %add25
87 }
88
89 define void @write_mclass_registers(i32 %x) nounwind {
90 entry:
91 ; MAINLINE-LABEL: write_mclass_registers:
92 ; MAINLINE: msr apsr_nzcvqg, r0
93 ; MAINLINE: msr apsr_nzcvq, r0
94 ; MAINLINE: msr apsr_g, r0
95 ; MAINLINE: msr apsr_nzcvqg, r0
96 ; MAINLINE: msr iapsr_nzcvqg, r0
97 ; MAINLINE: msr iapsr_nzcvq, r0
98 ; MAINLINE: msr iapsr_g, r0
99 ; MAINLINE: msr iapsr_nzcvqg, r0
100 ; MAINLINE: msr eapsr_nzcvqg, r0
101 ; MAINLINE: msr eapsr_nzcvq, r0
102 ; MAINLINE: msr eapsr_g, r0
103 ; MAINLINE: msr eapsr_nzcvqg, r0
104 ; MAINLINE: msr xpsr_nzcvqg, r0
105 ; MAINLINE: msr xpsr_nzcvq, r0
106 ; MAINLINE: msr xpsr_g, r0
107 ; MAINLINE: msr xpsr_nzcvqg, r0
108 ; MAINLINE: msr ipsr, r0
109 ; MAINLINE: msr epsr, r0
110 ; MAINLINE: msr iepsr, r0
111 ; MAINLINE: msr msp, r0
112 ; MAINLINE: msr psp, r0
113 ; MAINLINE: msr primask, r0
114 ; MAINLINE: msr basepri, r0
115 ; MAINLINE: msr basepri_max, r0
116 ; MAINLINE: msr faultmask, r0
117 ; MAINLINE: msr control, r0
118 ; MAINLINE: msr msplim, r0
119 ; MAINLINE: msr psplim, r0
120 ; MAINLINE: msr msp_ns, r0
121 ; MAINLINE: msr psp_ns, r0
122 ; MAINLINE: msr msplim_ns, r0
123 ; MAINLINE: msr psplim_ns, r0
124 ; MAINLINE: msr primask_ns, r0
125 ; MAINLINE: msr basepri_ns, r0
126 ; MAINLINE: msr faultmask_ns, r0
127 ; MAINLINE: msr control_ns, r0
128 ; MAINLINE: msr sp_ns, r0
129 ; MAINLINE: msr basepri_max_ns, r0
130
131 call void @llvm.write_register.i32(metadata !0, i32 %x)
132 call void @llvm.write_register.i32(metadata !1, i32 %x)
133 call void @llvm.write_register.i32(metadata !2, i32 %x)
134 call void @llvm.write_register.i32(metadata !3, i32 %x)
135 call void @llvm.write_register.i32(metadata !4, i32 %x)
136 call void @llvm.write_register.i32(metadata !5, i32 %x)
137 call void @llvm.write_register.i32(metadata !6, i32 %x)
138 call void @llvm.write_register.i32(metadata !7, i32 %x)
139 call void @llvm.write_register.i32(metadata !8, i32 %x)
140 call void @llvm.write_register.i32(metadata !9, i32 %x)
141 call void @llvm.write_register.i32(metadata !10, i32 %x)
142 call void @llvm.write_register.i32(metadata !11, i32 %x)
143 call void @llvm.write_register.i32(metadata !12, i32 %x)
144 call void @llvm.write_register.i32(metadata !13, i32 %x)
145 call void @llvm.write_register.i32(metadata !14, i32 %x)
146 call void @llvm.write_register.i32(metadata !15, i32 %x)
147 call void @llvm.write_register.i32(metadata !16, i32 %x)
148 call void @llvm.write_register.i32(metadata !17, i32 %x)
149 call void @llvm.write_register.i32(metadata !18, i32 %x)
150 call void @llvm.write_register.i32(metadata !19, i32 %x)
151 call void @llvm.write_register.i32(metadata !20, i32 %x)
152 call void @llvm.write_register.i32(metadata !21, i32 %x)
153 call void @llvm.write_register.i32(metadata !22, i32 %x)
154 call void @llvm.write_register.i32(metadata !23, i32 %x)
155 call void @llvm.write_register.i32(metadata !24, i32 %x)
156 call void @llvm.write_register.i32(metadata !25, i32 %x)
157 call void @llvm.write_register.i32(metadata !26, i32 %x)
158 call void @llvm.write_register.i32(metadata !27, i32 %x)
159 call void @llvm.write_register.i32(metadata !28, i32 %x)
160 call void @llvm.write_register.i32(metadata !29, i32 %x)
161 call void @llvm.write_register.i32(metadata !30, i32 %x)
162 call void @llvm.write_register.i32(metadata !31, i32 %x)
163 call void @llvm.write_register.i32(metadata !32, i32 %x)
164 call void @llvm.write_register.i32(metadata !33, i32 %x)
165 call void @llvm.write_register.i32(metadata !34, i32 %x)
166 call void @llvm.write_register.i32(metadata !35, i32 %x)
167 call void @llvm.write_register.i32(metadata !36, i32 %x)
168 call void @llvm.write_register.i32(metadata !37, i32 %x)
169 ret void
170 }
171
172 declare i32 @llvm.read_register.i32(metadata) nounwind
173 declare void @llvm.write_register.i32(metadata, i32) nounwind
174
175 !0 = !{!"apsr"}
176 !1 = !{!"apsr_nzcvq"}
177 !2 = !{!"apsr_g"}
178 !3 = !{!"apsr_nzcvqg"}
179 !4 = !{!"iapsr"}
180 !5 = !{!"iapsr_nzcvq"}
181 !6 = !{!"iapsr_g"}
182 !7 = !{!"iapsr_nzcvqg"}
183 !8 = !{!"eapsr"}
184 !9 = !{!"eapsr_nzcvq"}
185 !10 = !{!"eapsr_g"}
186 !11 = !{!"eapsr_nzcvqg"}
187 !12 = !{!"xpsr"}
188 !13 = !{!"xpsr_nzcvq"}
189 !14 = !{!"xpsr_g"}
190 !15 = !{!"xpsr_nzcvqg"}
191 !16 = !{!"ipsr"}
192 !17 = !{!"epsr"}
193 !18 = !{!"iepsr"}
194 !19 = !{!"msp"}
195 !20 = !{!"psp"}
196 !21 = !{!"primask"}
197 !22 = !{!"basepri"}
198 !23 = !{!"basepri_max"}
199 !24 = !{!"faultmask"}
200 !25 = !{!"control"}
201 !26 = !{!"msplim"}
202 !27 = !{!"psplim"}
203 !28 = !{!"msp_ns"}
204 !29 = !{!"psp_ns"}
205 !30 = !{!"msplim_ns"}
206 !31 = !{!"psplim_ns"}
207 !32 = !{!"primask_ns"}
208 !33 = !{!"basepri_ns"}
209 !34 = !{!"faultmask_ns"}
210 !35 = !{!"control_ns"}
211 !36 = !{!"sp_ns"}
212 !37 = !{!"basepri_max_ns"}
213
162162 // CHECK-MAINLINE: vlstm r10 @ encoding: [0x2a,0xec,0x00,0x0a]
163163 vlstm r10
164164
165 // New SYSm's
166
167 MRS r1, MSP_NS
168 // CHECK: mrs r1, msp_ns @ encoding: [0xef,0xf3,0x88,0x81]
169 MSR PSP_NS, r2
170 // CHECK: msr psp_ns, r2 @ encoding: [0x82,0xf3,0x89,0x88]
171 MRS r3, PRIMASK_NS
172 // CHECK: mrs r3, primask_ns @ encoding: [0xef,0xf3,0x90,0x83]
173 MSR CONTROL_NS, r4
174 // CHECK: msr control_ns, r4 @ encoding: [0x84,0xf3,0x94,0x88]
175 MRS r5, SP_NS
176 // CHECK: mrs r5, sp_ns @ encoding: [0xef,0xf3,0x98,0x85]
177 MRS r6,MSPLIM
178 // CHECK: mrs r6, msplim @ encoding: [0xef,0xf3,0x0a,0x86]
179 MRS r7,PSPLIM
180 // CHECK: mrs r7, psplim @ encoding: [0xef,0xf3,0x0b,0x87]
181 MSR MSPLIM,r8
182 // CHECK: msr msplim, r8 @ encoding: [0x88,0xf3,0x0a,0x88]
183 MSR PSPLIM,r9
184 // CHECK: msr psplim, r9 @ encoding: [0x89,0xf3,0x0b,0x88]
185
186 MRS r10, MSPLIM_NS
187 // CHECK-MAINLINE: mrs r10, msplim_ns @ encoding: [0xef,0xf3,0x8a,0x8a]
188 // UNDEF-BASELINE: error: invalid operand for instruction
189 MSR PSPLIM_NS, r11
190 // CHECK-MAINLINE: msr psplim_ns, r11 @ encoding: [0x8b,0xf3,0x8b,0x88]
191 // UNDEF-BASELINE: error: invalid operand for instruction
192 MRS r12, BASEPRI_NS
193 // CHECK-MAINLINE: mrs r12, basepri_ns @ encoding: [0xef,0xf3,0x91,0x8c]
194 // UNDEF-BASELINE: error: invalid operand for instruction
195 MRS r12, BASEPRI_MAX_NS
196 // CHECK-MAINLINE: mrs r12, basepri_max_ns @ encoding: [0xef,0xf3,0x92,0x8c]
197 // UNDEF-BASELINE: error: invalid operand for instruction
198 MSR FAULTMASK_NS, r14
199 // CHECK-MAINLINE: msr faultmask_ns, lr @ encoding: [0x8e,0xf3,0x93,0x88]
200 // UNDEF-BASELINE: error: invalid operand for instruction
165201
166202 // Invalid operand tests
167203 // UNDEF: error: invalid operand for instruction
0 # RUN: llvm-mc -triple=thumbv8m.base -disassemble < %s 2>%t | FileCheck %s
1 # RUN: FileCheck < %t %s --check-prefix=CHECK-STDERR
2 # RUN: llvm-mc -triple=thumbv8m.main -disassemble < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MAINLINE
3
4 0xef 0xf3 0x0a 0x83
5 # CHECK: mrs r3, msplim
6 0xef 0xf3 0x0b 0x84
7 # CHECK: mrs r4, psplim
8 0x8b 0xf3 0x0a 0x88
9 # CHECK: msr msplim, r11
10 0x8c 0xf3 0x0b 0x88
11 # CHECK: msr psplim, r12
12
13 0xef 0xf3 0x90 0x86
14 # CHECK: mrs r6, primask_ns
15 0x88 0xf3 0x98 0x88
16 # CHECK: msr sp_ns, r8
17
18 0xef 0xf3 0x8a 0x85
19 # CHECK-STDERR: warning: invalid instruction encoding
20 # CHECK-MAINLINE: mrs r5, msplim_ns
21 0x87 0xf3 0x93 0x88
22 # CHECK-STDERR: warning: invalid instruction encoding
23 # CHECK-MAINLINE: msr faultmask_ns, r7
24