llvm.org GIT mirror llvm / 0a6ea83
Add asserts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129995 91177308-0d34-0410-b5e6-96231b3b80d8 Devang Patel 9 years ago
1 changed file(s) with 2 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
179179 else {
180180 unsigned Reg = MLoc.getReg();
181181 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
182 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
182183 // S registers are described as bit-pieces of a register
183184 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
184185 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
209210 EmitULEB128(0);
210211 }
211212 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
213 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
212214 // Q registers Q0-Q15 are described by composing two D registers together.
213215 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1) DW_OP_piece(8)
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