llvm.org GIT mirror llvm / 0a38cc6
[X86] When lowering uniform shifts, use X86ISD::VZEXT instead of using a ZERO_EXTEND_VECTOR_INREG. If we emit the ZERO_EXTEND_VECTOR_INREG too late it doesn't get lowered properly and makes it through to isel and fails. Fixes PR31593. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291535 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 3 years ago
1 changed file(s) with 4 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
1841718417 ShAmt = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(ShAmt), MVT::v2i64, ShAmt);
1841818418 else if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
1841918419 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
18420 SDValue Op0 = ShAmt.getOperand(0);
18421 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
18422 ShAmt = DAG.getZeroExtendVectorInReg(Op0, SDLoc(Op0), MVT::v2i64);
18420 ShAmt = ShAmt.getOperand(0);
18421 ShAmt = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(ShAmt), MVT::v8i16, ShAmt);
18422 ShAmt = DAG.getNode(X86ISD::VZEXT, SDLoc(ShAmt), MVT::v2i64, ShAmt);
1842318423 } else if (Subtarget.hasSSE41() &&
1842418424 ShAmt.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1842518425 ShAmt = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(ShAmt), MVT::v4i32, ShAmt);
18426 ShAmt = DAG.getZeroExtendVectorInReg(ShAmt, SDLoc(ShAmt), MVT::v2i64);
18426 ShAmt = DAG.getNode(X86ISD::VZEXT, SDLoc(ShAmt), MVT::v2i64, ShAmt);
1842718427 } else {
1842818428 SmallVector ShOps = {ShAmt, DAG.getConstant(0, dl, SVT),
1842918429 DAG.getUNDEF(SVT), DAG.getUNDEF(SVT)};