llvm.org GIT mirror llvm / 09e4606
Completely eliminate def&use operands. Now a register operand is EITHER a def operand or a use operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30109 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 13 years ago
10 changed file(s) with 78 addition(s) and 106 deletion(s). Raw diff Collapse all Expand all
3737 // Representation of each machine instruction operand.
3838 //
3939 struct MachineOperand {
40 private:
41 // Bit fields of the flags variable used for different operand properties
42 enum {
43 DEFFLAG = 0x01, // this is a def of the operand
44 USEFLAG = 0x02 // this is a use of the operand
45 };
46
47 public:
48 // UseType - This enum describes how the machine operand is used by
49 // the instruction. Note that the MachineInstr/Operator class
50 // currently uses bool arguments to represent this information
51 // instead of an enum. Eventually this should change over to use
52 // this _easier to read_ representation instead.
53 //
54 enum UseType {
55 Use = USEFLAG, /// only read
56 Def = DEFFLAG, /// only written
57 UseAndDef = Use | Def /// read AND written
58 };
59
6040 enum MachineOperandType {
6141 MO_Register, // Register operand.
6242 MO_Immediate, // Immediate Operand
7757 int64_t immedVal; // For MO_Immediate and MO_*Index.
7858 } contents;
7959
80 char flags; // see bit field definitions above
81 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
60 MachineOperandType opType:8; // Discriminate the union.
61 bool IsDef : 1; // True if this is a def, false if this is a use.
8262
8363 /// offset - Offset to address of global or external, only valid for
8464 /// MO_GlobalAddress, MO_ExternalSym and MO_ConstantPoolIndex
9474
9575 const MachineOperand &operator=(const MachineOperand &MO) {
9676 contents = MO.contents;
97 flags = MO.flags;
77 IsDef = MO.IsDef;
9878 opType = MO.opType;
9979 offset = MO.offset;
10080 return *this;
10383 /// getType - Returns the MachineOperandType for this operand.
10484 ///
10585 MachineOperandType getType() const { return opType; }
106
107 /// getUseType - Returns the MachineOperandUseType of this operand.
108 ///
109 UseType getUseType() const { return UseType(flags & (USEFLAG|DEFFLAG)); }
11086
11187 /// Accessors that tell you what kind of MachineOperand you're looking at.
11288 ///
166142 return contents.SymbolName;
167143 }
168144
169 /// MachineOperand methods for testing that work on any kind of
170 /// MachineOperand...
171 ///
172 bool isUse() const { return flags & USEFLAG; }
173 bool isDef() const { return flags & DEFFLAG; }
174 MachineOperand &setUse() { flags |= USEFLAG; return *this; }
175 MachineOperand &setDef() { flags |= DEFFLAG; return *this; }
145 bool isUse() const { return !IsDef; }
146 bool isDef() const { return IsDef; }
147 void setIsUse() { IsDef = false; }
148 void setIsDef() { IsDef = true; }
176149
177150 /// getReg - Returns the register number.
178151 ///
215188 /// ChangeToRegister - Replace this operand with a new register operand of
216189 /// the specified value. If an operand is known to be an register already,
217190 /// the setReg method should be used.
218 void ChangeToRegister(unsigned Reg) {
191 void ChangeToRegister(unsigned Reg, bool isDef) {
219192 opType = MO_Register;
220193 contents.RegNo = Reg;
194 IsDef = isDef;
221195 }
222196
223197 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
306280
307281 /// addRegOperand - Add a register operand.
308282 ///
309 void addRegOperand(unsigned Reg,
310 MachineOperand::UseType UTy = MachineOperand::Use) {
283 void addRegOperand(unsigned Reg, bool IsDef) {
311284 MachineOperand &Op = AddNewOperand();
312285 Op.opType = MachineOperand::MO_Register;
313 Op.flags = UTy;
286 Op.IsDef = IsDef;
314287 Op.contents.RegNo = Reg;
315288 Op.offset = 0;
316289 }
321294 void addImmOperand(int64_t Val) {
322295 MachineOperand &Op = AddNewOperand();
323296 Op.opType = MachineOperand::MO_Immediate;
324 Op.flags = 0;
325297 Op.contents.immedVal = Val;
326298 Op.offset = 0;
327299 }
329301 void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
330302 MachineOperand &Op = AddNewOperand();
331303 Op.opType = MachineOperand::MO_MachineBasicBlock;
332 Op.flags = 0;
333304 Op.contents.MBB = MBB;
334305 Op.offset = 0;
335306 }
339310 void addFrameIndexOperand(unsigned Idx) {
340311 MachineOperand &Op = AddNewOperand();
341312 Op.opType = MachineOperand::MO_FrameIndex;
342 Op.flags = 0;
343313 Op.contents.immedVal = Idx;
344314 Op.offset = 0;
345315 }
350320 void addConstantPoolIndexOperand(unsigned Idx, int Offset) {
351321 MachineOperand &Op = AddNewOperand();
352322 Op.opType = MachineOperand::MO_ConstantPoolIndex;
353 Op.flags = 0;
354323 Op.contents.immedVal = Idx;
355324 Op.offset = Offset;
356325 }
361330 void addJumpTableIndexOperand(unsigned Idx) {
362331 MachineOperand &Op = AddNewOperand();
363332 Op.opType = MachineOperand::MO_JumpTableIndex;
364 Op.flags = 0;
365333 Op.contents.immedVal = Idx;
366334 Op.offset = 0;
367335 }
369337 void addGlobalAddressOperand(GlobalValue *GV, int Offset) {
370338 MachineOperand &Op = AddNewOperand();
371339 Op.opType = MachineOperand::MO_GlobalAddress;
372 Op.flags = 0;
373340 Op.contents.GV = GV;
374341 Op.offset = Offset;
375342 }
379346 void addExternalSymbolOperand(const char *SymName) {
380347 MachineOperand &Op = AddNewOperand();
381348 Op.opType = MachineOperand::MO_ExternalSymbol;
382 Op.flags = 0;
383349 Op.contents.SymbolName = SymName;
384350 Op.offset = 0;
385351 }
3232
3333 /// addReg - Add a new virtual register operand...
3434 ///
35 const MachineInstrBuilder &addReg(
36 int RegNo,
37 MachineOperand::UseType Ty = MachineOperand::Use) const {
38 MI->addRegOperand(RegNo, Ty);
35 const MachineInstrBuilder &addReg(int RegNo, bool isDef = false) const {
36 MI->addRegOperand(RegNo, isDef);
3937 return *this;
4038 }
4139
9189 /// destination virtual register. NumOperands is the number of additional add*
9290 /// calls that are expected, not including the destination register.
9391 ///
94 inline MachineInstrBuilder BuildMI(
95 int Opcode, unsigned NumOperands,
96 unsigned DestReg,
97 MachineOperand::UseType useType = MachineOperand::Def) {
92 inline MachineInstrBuilder
93 BuildMI(int Opcode, unsigned NumOperands, unsigned DestReg) {
9894 return MachineInstrBuilder(new MachineInstr(Opcode, NumOperands+1))
99 .addReg(DestReg, useType);
95 .addReg(DestReg, true);
10096 }
10197
10298 /// BuildMI - This version of the builder inserts the newly-built
111107 unsigned DestReg) {
112108 MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1);
113109 BB.insert(I, MI);
114 return MachineInstrBuilder(MI).addReg(DestReg, MachineOperand::Def);
110 return MachineInstrBuilder(MI).addReg(DestReg, true);
115111 }
116112
117113 /// BuildMI - This version of the builder inserts the newly-built
254254 // the machine instruction.
255255 unsigned ResultReg =
256256 RegMap->createVirtualRegister(getInstrOperandRegClass(MRI, TII, &II, 0));
257 MI->addRegOperand(ResultReg, MachineOperand::Def);
257 MI->addRegOperand(ResultReg, true);
258258 for (unsigned i = 1; i != NumResults; ++i) {
259259 const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
260260 assert(RC && "Isn't a register operand!");
261 MI->addRegOperand(RegMap->createVirtualRegister(RC), MachineOperand::Def);
261 MI->addRegOperand(RegMap->createVirtualRegister(RC), true);
262262 }
263263 return ResultReg;
264264 }
290290
291291 // Get/emit the operand.
292292 unsigned VReg = getVR(Op, VRBaseMap);
293 MI->addRegOperand(VReg, MachineOperand::Use);
293 MI->addRegOperand(VReg, false);
294294
295295 // Verify that it is right.
296296 assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
306306 MI->addImmOperand(C->getValue());
307307 } else if (RegisterSDNode*R =
308308 dyn_cast(Op)) {
309 MI->addRegOperand(R->getReg(), MachineOperand::Use);
309 MI->addRegOperand(R->getReg(), false);
310310 } else if (GlobalAddressSDNode *TGA =
311311 dyn_cast(Op)) {
312312 MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset());
348348 Op.getValueType() != MVT::Flag &&
349349 "Chain and flag operands should occur at end of operand list!");
350350 unsigned VReg = getVR(Op, VRBaseMap);
351 MI->addRegOperand(VReg, MachineOperand::Use);
351 MI->addRegOperand(VReg, false);
352352
353353 // Verify that it is right.
354354 assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
401401 unsigned Reg = cast(Use->getOperand(1))->getReg();
402402 if (MRegisterInfo::isVirtualRegister(Reg)) {
403403 VRBase = Reg;
404 MI->addRegOperand(Reg, MachineOperand::Def);
404 MI->addRegOperand(Reg, true);
405405 break;
406406 }
407407 }
528528 case 1: // Use of register.
529529 for (; NumVals; --NumVals, ++i) {
530530 unsigned Reg = cast(Node->getOperand(i))->getReg();
531 MI->addRegOperand(Reg, MachineOperand::Use);
531 MI->addRegOperand(Reg, false);
532532 }
533533 break;
534534 case 2: // Def of register.
535535 for (; NumVals; --NumVals, ++i) {
536536 unsigned Reg = cast(Node->getOperand(i))->getReg();
537 MI->addRegOperand(Reg, MachineOperand::Def);
537 MI->addRegOperand(Reg, true);
538538 }
539539 break;
540540 case 3: { // Immediate.
35463546 MachineInstr *PHI = PHINodesToUpdate[i].first;
35473547 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
35483548 "This is not a machine PHI node that we are updating!");
3549 PHI->addRegOperand(PHINodesToUpdate[i].second);
3549 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
35503550 PHI->addMachineBasicBlockOperand(BB);
35513551 }
35523552 return;
35753575 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
35763576 "This is not a machine PHI node that we are updating!");
35773577 if (PHIBB == JT.Default) {
3578 PHI->addRegOperand(PHINodesToUpdate[pi].second);
3578 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
35793579 PHI->addMachineBasicBlockOperand(RangeBB);
35803580 }
35813581 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
3582 PHI->addRegOperand(PHINodesToUpdate[pi].second);
3582 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
35833583 PHI->addMachineBasicBlockOperand(BB);
35843584 }
35853585 }
36093609 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
36103610 "This is not a machine PHI node that we are updating!");
36113611 if (PHIBB == SwitchCases[i].LHSBB || PHIBB == SwitchCases[i].RHSBB) {
3612 PHI->addRegOperand(PHINodesToUpdate[pi].second);
3612 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
36133613 PHI->addMachineBasicBlockOperand(BB);
36143614 }
36153615 }
106106 assert (Offset >= 0);
107107 if (Offset < 4096) {
108108 // Replace the FrameIndex with r13
109 MI.getOperand(FrameIdx).ChangeToRegister(ARM::R13);
109 MI.getOperand(FrameIdx).ChangeToRegister(ARM::R13, false);
110110 // Replace the ldr offset with Offset
111111 MI.getOperand(OffIdx).ChangeToImmediate(Offset);
112112 } else {
116116 BuildMI(*MBB2, II, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
117117
118118 // Replace the FrameIndex with r12
119 MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12);
119 MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12, false);
120120 }
121121 }
122122
6666 MachineBasicBlock::iterator MI,
6767 unsigned SrcReg, int FrameIdx,
6868 const TargetRegisterClass *RC) const {
69 //std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n";
69 //std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
70 //<< FrameIdx << "\n";
7071 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
7172 if (RC == Alpha::F4RCRegisterClass)
72 BuildMI(MBB, MI, Alpha::STS, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
73 BuildMI(MBB, MI, Alpha::STS, 3)
74 .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
7375 else if (RC == Alpha::F8RCRegisterClass)
74 BuildMI(MBB, MI, Alpha::STT, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
76 BuildMI(MBB, MI, Alpha::STT, 3)
77 .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
7578 else if (RC == Alpha::GPRCRegisterClass)
76 BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
79 BuildMI(MBB, MI, Alpha::STQ, 3)
80 .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
7781 else
7882 abort();
7983 }
8387 MachineBasicBlock::iterator MI,
8488 unsigned DestReg, int FrameIdx,
8589 const TargetRegisterClass *RC) const {
86 //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n";
90 //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to "
91 //<< FrameIdx << "\n";
8792 if (RC == Alpha::F4RCRegisterClass)
88 BuildMI(MBB, MI, Alpha::LDS, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
93 BuildMI(MBB, MI, Alpha::LDS, 2, DestReg)
94 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
8995 else if (RC == Alpha::F8RCRegisterClass)
90 BuildMI(MBB, MI, Alpha::LDT, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
96 BuildMI(MBB, MI, Alpha::LDT, 2, DestReg)
97 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
9198 else if (RC == Alpha::GPRCRegisterClass)
92 BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
99 BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg)
100 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
93101 else
94102 abort();
95103 }
242250 int FrameIndex = MI.getOperand(i).getFrameIndex();
243251
244252 // Add the base register of R30 (SP) or R15 (FP).
245 MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30);
253 MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false);
246254
247255 // Now add the frame object offset to the offset from the virtual frame index.
248256 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
255263 " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n");
256264
257265 if (Offset > IMM_HIGH || Offset < IMM_LOW) {
258 DEBUG(std::cerr << "Unconditionally using R28 for evil purposes Offset: " << Offset << "\n");
259 //so in this case, we need to use a temporary register, and move the original
260 //inst off the SP/FP
266 DEBUG(std::cerr << "Unconditionally using R28 for evil purposes Offset: "
267 << Offset << "\n");
268 //so in this case, we need to use a temporary register, and move the
269 //original inst off the SP/FP
261270 //fix up the old:
262 MI.getOperand(i + 1).ChangeToRegister(Alpha::R28);
271 MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
263272 MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
264273 //insert the new
265274 MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28)
334343 //now if we need to, save the old FP and set the new
335344 if (FP)
336345 {
337 BuildMI(MBB, MBBI, Alpha::STQ, 3).addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
346 BuildMI(MBB, MBBI, Alpha::STQ, 3)
347 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
338348 //this must be the last instr in the prolog
339 BuildMI(MBB, MBBI, Alpha::BIS, 2, Alpha::R15).addReg(Alpha::R30).addReg(Alpha::R30);
349 BuildMI(MBB, MBBI, Alpha::BIS, 2, Alpha::R15)
350 .addReg(Alpha::R30).addReg(Alpha::R30);
340351 }
341352
342353 }
345356 MachineBasicBlock &MBB) const {
346357 const MachineFrameInfo *MFI = MF.getFrameInfo();
347358 MachineBasicBlock::iterator MBBI = prior(MBB.end());
348 assert(MBBI->getOpcode() == Alpha::RETDAG || MBBI->getOpcode() == Alpha::RETDAGp
359 assert(MBBI->getOpcode() == Alpha::RETDAG ||
360 MBBI->getOpcode() == Alpha::RETDAGp
349361 && "Can only insert epilog into returning blocks");
350362
351363 bool FP = hasFP(MF);
8484
8585 if(RC == IA64::PRRegisterClass ) // if a bool, we use pseudocode
8686 // (SrcReg) DestReg = cmp.eq.unc(r0, r0)
87 BuildMI(MBB, MI, IA64::PCMPEQUNC, 3, DestReg).addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
87 BuildMI(MBB, MI, IA64::PCMPEQUNC, 3, DestReg)
88 .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
8889 else // otherwise, MOV works (for both gen. regs and FP regs)
8990 BuildMI(MBB, MI, IA64::MOV, 1, DestReg).addReg(SrcReg);
9091 }
151152 MBB.erase(I);
152153 }
153154
154 void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
155 void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II)const{
155156 unsigned i = 0;
156157 MachineInstr &MI = *II;
157158 MachineBasicBlock &MBB = *MI.getParent();
169170 // choose a base register: ( hasFP? framepointer : stack pointer )
170171 unsigned BaseRegister = FP ? IA64::r5 : IA64::r12;
171172 // Add the base register
172 MI.getOperand(i).ChangeToRegister(BaseRegister);
173 MI.getOperand(i).ChangeToRegister(BaseRegister, false);
173174
174175 // Now add the frame object offset to the offset from r1.
175176 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
180181 Offset += MF.getFrameInfo()->getStackSize();
181182
182183 // XXX: we use 'r22' as another hack+slash temporary register here :(
183 if ( Offset <= 8191 && Offset >= -8192) { // smallish offset
184 //fix up the old:
185 MI.getOperand(i).ChangeToRegister(IA64::r22);
186 MI.getOperand(i).setUse(); // mark r22 as being used
187 // (the bundler wants to know this)
184 if (Offset <= 8191 && Offset >= -8192) { // smallish offset
185 // Fix up the old:
186 MI.getOperand(i).ChangeToRegister(IA64::r22, false);
188187 //insert the new
189188 MachineInstr* nMI=BuildMI(IA64::ADDIMM22, 2, IA64::r22)
190189 .addReg(BaseRegister).addImm(Offset);
191190 MBB.insert(II, nMI);
192191 } else { // it's big
193192 //fix up the old:
194 MI.getOperand(i).ChangeToRegister(IA64::r22);
195 MI.getOperand(i).setUse(); // mark r22 as being used
196 // (the bundler wants to know this)
193 MI.getOperand(i).ChangeToRegister(IA64::r22, false);
197194 MachineInstr* nMI;
198195 nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(Offset);
199196 MBB.insert(II, nMI);
241238
242239 unsigned numOutRegsUsed=MF.getInfo()->outRegsUsed;
243240
244 // XXX FIXME : this code should be a bit more reliable (in case there _isn't_ a pseudo_alloc in the MBB)
241 // XXX FIXME : this code should be a bit more reliable (in case there _isn't_
242 // a pseudo_alloc in the MBB)
245243 unsigned dstRegOfPseudoAlloc;
246244 for(MBBI = MBB.begin(); /*MBBI->getOpcode() != IA64::PSEUDO_ALLOC*/; ++MBBI) {
247245 assert(MBBI != MBB.end());
283281
284282 // adjust stack pointer: r12 -= numbytes
285283 if (NumBytes <= 8191) {
286 MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(-NumBytes);
284 MI=BuildMI(IA64::ADDIMM22,2,IA64::r12).addReg(IA64::r12).addImm(-NumBytes);
287285 MBB.insert(MBBI, MI);
288286 } else { // we use r22 as a scratch register here
289287 MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(-NumBytes);
331329 if (NumBytes != 0)
332330 {
333331 if (NumBytes <= 8191) {
334 MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(NumBytes);
332 MI=BuildMI(IA64::ADDIMM22,2,IA64::r12).addReg(IA64::r12).addImm(NumBytes);
335333 MBB.insert(MBBI, MI);
336334 } else {
337335 MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(NumBytes);
420420 int FrameIndex = MI.getOperand(i).getFrameIndex();
421421
422422 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
423 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1);
423 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, false);
424424
425425 // Take into account whether it's an add or mem instruction
426426 unsigned OffIdx = (i == 2) ? 1 : 2;
465465 "No indexed form of load or store available!");
466466 unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
467467 MI.setOpcode(NewOpcode);
468 MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg());
469 MI.getOperand(2).ChangeToRegister(PPC::R0);
468 MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg(), false);
469 MI.getOperand(2).ChangeToRegister(PPC::R0, false);
470470 } else {
471471 if (isIXAddr) {
472472 assert((Offset & 3) == 0 && "Invalid frame offset!");
146146 if (Offset >= -4096 && Offset <= 4095) {
147147 // If the offset is small enough to fit in the immediate field, directly
148148 // encode it.
149 MI.getOperand(i).ChangeToRegister(SP::I6);
149 MI.getOperand(i).ChangeToRegister(SP::I6, false);
150150 MI.getOperand(i+1).ChangeToImmediate(Offset);
151151 } else {
152152 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
157157 BuildMI(*MI.getParent(), II, SP::ADDrr, 2,
158158 SP::G1).addReg(SP::G1).addReg(SP::I6);
159159 // Insert: G1+%lo(offset) into the user.
160 MI.getOperand(i).ChangeToRegister(SP::G1);
160 MI.getOperand(i).ChangeToRegister(SP::G1, false);
161161 MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
162162 }
163163 }
167167 assert(MO.isReg() && "Expected to fold into reg operand!");
168168 MIB = addFrameReference(MIB, FrameIndex);
169169 } else if (MO.isReg())
170 MIB = MIB.addReg(MO.getReg(), MO.getUseType());
170 MIB = MIB.addReg(MO.getReg(), MO.isDef());
171171 else if (MO.isImm())
172172 MIB = MIB.addImm(MO.getImm());
173173 else if (MO.isGlobalAddress())
794794
795795 // This must be part of a four operand memory reference. Replace the
796796 // FrameIndex with base register with EBP. Add add an offset to the offset.
797 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? X86::EBP : X86::ESP);
797 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? X86::EBP : X86::ESP, false);
798798
799799 // Now add the frame object offset to the offset from EBP.
800800 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +