llvm.org GIT mirror llvm / 09c0ea5
Untabify. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248264 91177308-0d34-0410-b5e6-96231b3b80d8 NAKAMURA Takumi 5 years ago
33 changed file(s) with 117 addition(s) and 127 deletion(s). Raw diff Collapse all Expand all
4848 INITIALIZE_PASS_DEPENDENCY(AssumptionCacheTracker)
4949 INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
5050 INITIALIZE_PASS_END(DemandedBits, "demanded-bits", "Demanded bits analysis",
51 false, false)
51 false, false)
5252
5353 DemandedBits::DemandedBits() : FunctionPass(ID) {
5454 initializeDemandedBitsPass(*PassRegistry::getPassRegistry());
6666 I->isEHPad() || I->mayHaveSideEffects();
6767 }
6868
69 void
70 DemandedBits::determineLiveOperandBits(const Instruction *UserI,
71 const Instruction *I, unsigned OperandNo,
72 const APInt &AOut, APInt &AB,
73 APInt &KnownZero, APInt &KnownOne,
74 APInt &KnownZero2, APInt &KnownOne2) {
69 void DemandedBits::determineLiveOperandBits(
70 const Instruction *UserI, const Instruction *I, unsigned OperandNo,
71 const APInt &AOut, APInt &AB, APInt &KnownZero, APInt &KnownOne,
72 APInt &KnownZero2, APInt &KnownOne2) {
7573 unsigned BitWidth = AB.getBitWidth();
7674
7775 // We're called once per operand, but for some instructions, we need to
17851785 DebugLoc InlinedAtDL(InlinedAt);
17861786 if (InlinedAtDL && MF) {
17871787 OS << " inlined @[ ";
1788 InlinedAtDL.print(OS);
1788 InlinedAtDL.print(OS);
17891789 OS << " ]";
17901790 }
17911791 }
204204
205205 // Use the target specific return value for comparions lib calls.
206206 EVT RetVT = getCmpLibcallReturnType();
207 SDValue Ops[2] = { NewLHS, NewRHS };
208 NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/,
209 dl).first;
207 SDValue Ops[2] = {NewLHS, NewRHS};
208 NewLHS =
209 makeLibCall(DAG, LC1, RetVT, Ops, 2, false /*sign irrelevant*/, dl).first;
210210 NewRHS = DAG.getConstant(0, dl, RetVT);
211211
212212 CCCode = getCmpLibcallCC(LC1);
732732 ".tls$", COFF::IMAGE_SCN_CNT_INITIALIZED_DATA | COFF::IMAGE_SCN_MEM_READ |
733733 COFF::IMAGE_SCN_MEM_WRITE,
734734 SectionKind::getDataRel());
735
735
736736 StackMapSection = Ctx->getCOFFSection(".llvm_stackmaps",
737737 COFF::IMAGE_SCN_CNT_INITIALIZED_DATA |
738738 COFF::IMAGE_SCN_MEM_READ,
739 SectionKind::getReadOnly());
739 SectionKind::getReadOnly());
740740 }
741741
742742 void MCObjectFileInfo::InitMCObjectFileInfo(const Triple &TheTriple,
455455 if (Section.getType() != MachO::S_NON_LAZY_SYMBOL_POINTERS &&
456456 Section.getType() != MachO::S_LAZY_SYMBOL_POINTERS &&
457457 Section.getType() != MachO::S_SYMBOL_STUBS) {
458 MCSymbol &Symbol = *it->Symbol;
459 report_fatal_error("indirect symbol '" + Symbol.getName() +
460 "' not in a symbol pointer or stub section");
458 MCSymbol &Symbol = *it->Symbol;
459 report_fatal_error("indirect symbol '" + Symbol.getName() +
460 "' not in a symbol pointer or stub section");
461461 }
462462 }
463463
7676
7777 template
7878 static void printWithSpacePadding(raw_fd_ostream &OS, T Data, unsigned Size,
79 bool MayTruncate = false) {
79 bool MayTruncate = false) {
8080 uint64_t OldPos = OS.tell();
8181 OS << Data;
8282 unsigned SizeSoFar = OS.tell() - OldPos;
11311131 }
11321132
11331133 Triple MachOObjectFile::getArch(uint32_t CPUType, uint32_t CPUSubType,
1134 const char **McpuDefault,
1135 Triple *ThumbTriple) {
1134 const char **McpuDefault, Triple *ThumbTriple) {
11361135 Triple T = MachOObjectFile::getArch(CPUType, CPUSubType, McpuDefault);
11371136 *ThumbTriple = MachOObjectFile::getThumbArch(CPUType, CPUSubType,
11381137 McpuDefault);
4949 return PROT_READ | PROT_WRITE;
5050 case llvm::sys::Memory::MF_READ|llvm::sys::Memory::MF_EXEC:
5151 return PROT_READ | PROT_EXEC;
52 case llvm::sys::Memory::MF_READ |
53 llvm::sys::Memory::MF_WRITE |
54 llvm::sys::Memory::MF_EXEC:
52 case llvm::sys::Memory::MF_READ | llvm::sys::Memory::MF_WRITE |
53 llvm::sys::Memory::MF_EXEC:
5554 return PROT_READ | PROT_WRITE | PROT_EXEC;
5655 case llvm::sys::Memory::MF_EXEC:
5756 #if defined(__FreeBSD__)
8989 }
9090
9191 bool AArch64MCExpr::evaluateAsRelocatableImpl(MCValue &Res,
92 const MCAsmLayout *Layout,
93 const MCFixup *Fixup) const {
92 const MCAsmLayout *Layout,
93 const MCFixup *Fixup) const {
9494 if (!getSubExpr()->evaluateAsRelocatable(Res, Layout, Fixup))
9595 return false;
9696
150150
151151 MCSection *findAssociatedSection() const override;
152152
153 bool evaluateAsRelocatableImpl(MCValue &Res,
154 const MCAsmLayout *Layout,
155 const MCFixup *Fixup) const override;
153 bool evaluateAsRelocatableImpl(MCValue &Res, const MCAsmLayout *Layout,
154 const MCFixup *Fixup) const override;
156155
157156 void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override;
158157
282282 }
283283 unsigned reg = MO.getReg();
284284 if (reg == AMDGPU::VCC || reg == AMDGPU::VCC_LO ||
285 reg == AMDGPU::VCC_HI) {
285 reg == AMDGPU::VCC_HI) {
286286 VCCUsed = true;
287287 continue;
288288 } else if (reg == AMDGPU::FLAT_SCR ||
11111111
11121112 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
11131113 SDValue &VAddr, SDValue &SOffset,
1114 SDValue &Offset,
1115 SDValue &SLC) const {
1114 SDValue &Offset,
1115 SDValue &SLC) const {
11161116 SLC = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i1);
11171117 SDValue GLC, TFE;
11181118
591591 } else {
592592 unsigned Stream = (SImm16 >> 8) & 0x3;
593593 if (Op == 1)
594 O << "cut";
594 O << "cut";
595595 else if (Op == 2)
596 O << "emit";
596 O << "emit";
597597 else if (Op == 3)
598 O << "emit-cut";
598 O << "emit-cut";
599599 O << " stream " << Stream;
600600 }
601601 O << "), [m0] ";
8080
8181 MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII,
8282 const MCRegisterInfo &MRI,
83 MCContext &Ctx) {
83 MCContext &Ctx) {
8484 return new R600MCCodeEmitter(MCII, MRI);
8585 }
8686
8585 const int *Sets = getRegClassPressureSets(*I);
8686 assert(Sets);
8787 for (unsigned i = 0; Sets[i] != -1; ++i) {
88 if (Sets[i] == (int)Idx)
88 if (Sets[i] == (int)Idx)
8989 return Limit;
9090 }
9191 }
105105 if (TT.isOSNetBSD())
106106 TargetABI = ARMBaseTargetMachine::ARM_ABI_APCS;
107107 else
108 TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
108 TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
109109 break;
110110 }
111111 }
233233
234234 // Adjust FP so it point to the stack slot that contains the previous FP.
235235 if (HasFP) {
236 FramePtrOffsetInBlock += MFI->getObjectOffset(FramePtrSpillFI)
237 + GPRCS1Size + ArgRegsSaveSize;
236 FramePtrOffsetInBlock +=
237 MFI->getObjectOffset(FramePtrSpillFI) + GPRCS1Size + ArgRegsSaveSize;
238238 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
239239 .addReg(ARM::SP).addImm(FramePtrOffsetInBlock / 4)
240240 .setMIFlags(MachineInstr::FrameSetup));
304304 break;
305305 case MCSymbolRefExpr::VK_GOT:
306306 Type = ELF::R_PPC64_GOT16_DS;
307 break;
307 break;
308308 case MCSymbolRefExpr::VK_PPC_GOT_LO:
309309 Type = ELF::R_PPC64_GOT16_LO_DS;
310310 break;
311311 case MCSymbolRefExpr::VK_PPC_TOC:
312312 Type = ELF::R_PPC64_TOC16_DS;
313 break;
313 break;
314314 case MCSymbolRefExpr::VK_PPC_TOC_LO:
315315 Type = ELF::R_PPC64_TOC16_LO_DS;
316316 break;
371371 break;
372372 case MCSymbolRefExpr::VK_None:
373373 Type = ELF::R_PPC64_ADDR64;
374 break;
374 break;
375375 case MCSymbolRefExpr::VK_PPC_DTPMOD:
376376 Type = ELF::R_PPC64_DTPMOD64;
377 break;
377 break;
378378 case MCSymbolRefExpr::VK_PPC_TPREL:
379379 Type = ELF::R_PPC64_TPREL64;
380 break;
380 break;
381381 case MCSymbolRefExpr::VK_PPC_DTPREL:
382382 Type = ELF::R_PPC64_DTPREL64;
383 break;
383 break;
384384 }
385385 break;
386386 case FK_Data_4:
295295 }
296296 case 'U': // Print 'u' for update form.
297297 case 'X': // Print 'x' for indexed form.
298 {
299 // FIXME: Currently for PowerPC memory operands are always loaded
300 // into a register, so we never get an update or indexed form.
301 // This is bad even for offset forms, since even if we know we
302 // have a value in -16(r1), we will generate a load into r
303 // and then load from 0(r). Until that issue is fixed,
304 // tolerate 'U' and 'X' but don't output anything.
305 assert(MI->getOperand(OpNo).isReg());
306 return false;
307 }
298 {
299 // FIXME: Currently for PowerPC memory operands are always loaded
300 // into a register, so we never get an update or indexed form.
301 // This is bad even for offset forms, since even if we know we
302 // have a value in -16(r1), we will generate a load into r
303 // and then load from 0(r). Until that issue is fixed,
304 // tolerate 'U' and 'X' but don't output anything.
305 assert(MI->getOperand(OpNo).isReg());
306 return false;
307 }
308308 }
309309 }
310310
10841084
10851085 if (!Subtarget->isPPC64()) {
10861086 const PPCFunctionInfo *PPCFI = MF->getInfo();
1087 if (PPCFI->usesPICBase()) {
1087 if (PPCFI->usesPICBase()) {
10881088 MCSymbol *RelocSymbol = PPCFI->getPICOffsetSymbol();
10891089 MCSymbol *PICBase = MF->getPICBaseSymbol();
10901090 OutStreamer->EmitLabel(RelocSymbol);
241241 // If we have a call to ppc_is_decremented_ctr_nonzero, or ppc_mtctr
242242 // we're definitely using CTR.
243243 case Intrinsic::ppc_is_decremented_ctr_nonzero:
244 case Intrinsic::ppc_mtctr:
245 return true;
244 case Intrinsic::ppc_mtctr:
245 return true;
246246
247247 // VisualStudio defines setjmp as _setjmp
248248 #if defined(_MSC_VER) && defined(setjmp) && \
53525352 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
53535353 FPOp, true, TailCallArguments);
53545354
5355 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint,
5356 hasNest, DAG, RegsToPass, InFlag, Chain, CallSeqStart,
5357 Callee, SPDiff, NumBytes, Ins, InVals, CS);
5355 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, hasNest,
5356 DAG, RegsToPass, InFlag, Chain, CallSeqStart, Callee,
5357 SPDiff, NumBytes, Ins, InVals, CS);
53585358 }
53595359
53605360 SDValue
609609
610610 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
611611 getCRFromCRBit(DestReg))
612 .addReg(RegO, RegState::Kill)
613 // Make sure we have a use dependency all the way through this
614 // sequence of instructions. We can't have the other bits in the CR
615 // modified in between the mfocrf and the mtocrf.
616 .addReg(getCRFromCRBit(DestReg), RegState::Implicit);
612 .addReg(RegO, RegState::Kill)
613 // Make sure we have a use dependency all the way through this
614 // sequence of instructions. We can't have the other bits in the CR
615 // modified in between the mfocrf and the mtocrf.
616 .addReg(getCRFromCRBit(DestReg), RegState::Implicit);
617617
618618 // Discard the pseudo instruction.
619619 MBB.erase(II);
672672 MBB.erase(II);
673673 }
674674
675 bool
676 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
677 unsigned Reg, int &FrameIdx) const {
675 bool PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
676 unsigned Reg, int &FrameIdx) const {
678677 const PPCSubtarget &Subtarget = MF.getSubtarget();
679678 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
680679 // ABI, return true to prevent allocating an additional frame slot.
114114 unsigned FrameIndex) const;
115115
116116 bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
117 int &FrameIdx) const override;
118 void eliminateFrameIndex(MachineBasicBlock::iterator II,
119 int SPAdj, unsigned FIOperandNum,
117 int &FrameIdx) const override;
118 void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
119 unsigned FIOperandNum,
120120 RegScavenger *RS = nullptr) const override;
121121
122122 // Support for virtual base registers.
148148 return PPCTargetMachine::PPC_ABI_ELFv2;
149149
150150 assert(Options.MCOptions.getABIName().empty() &&
151 "Unknown target-abi option!");
151 "Unknown target-abi option!");
152152
153153 if (!TT.isMacOSX()) {
154154 switch (TT.getArch()) {
185185 if (!KilledProdOp)
186186 continue;
187187
188 // If the addend copy is used only by this MI, then the addend source
189 // register is likely not live here. This could be fixed (based on the
190 // legality checks above, the live range for the addend source register
191 // could be extended), but it seems likely that such a trivial copy can
192 // be coalesced away later, and thus is not worth the effort.
193 if (TargetRegisterInfo::isVirtualRegister(AddendSrcReg) &&
188 // If the addend copy is used only by this MI, then the addend source
189 // register is likely not live here. This could be fixed (based on the
190 // legality checks above, the live range for the addend source register
191 // could be extended), but it seems likely that such a trivial copy can
192 // be coalesced away later, and thus is not worth the effort.
193 if (TargetRegisterInfo::isVirtualRegister(AddendSrcReg) &&
194194 !LIS->getInterval(AddendSrcReg).liveAt(FMAIdx))
195195 continue;
196196
225225
226226 // Register the MCCodeEmitter.
227227 TargetRegistry::RegisterMCCodeEmitter(TheSystemZTarget,
228 createSystemZMCCodeEmitter);
228 createSystemZMCCodeEmitter);
229229
230230 // Register the MCInstrInfo.
231231 TargetRegistry::RegisterMCInstrInfo(TheSystemZTarget,
24992499 }
25002500
25012501 SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
2502 SelectionDAG &DAG) const {
2502 SelectionDAG &DAG) const {
25032503 if (DAG.getTarget().Options.EmulatedTLS)
25042504 return LowerToTLSEmulatedModel(Node, DAG);
25052505 SDLoc DL(Node);
26342634 SDValue Result;
26352635 if (CP->isMachineConstantPoolEntry())
26362636 Result = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2637 CP->getAlignment());
2637 CP->getAlignment());
26382638 else
26392639 Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2640 CP->getAlignment(), CP->getOffset());
2640 CP->getAlignment(), CP->getOffset());
26412641
26422642 // Use LARL to load the address of the constant pool entry.
26432643 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
32533253 if (Op->getNumValues() == 1)
32543254 return CC;
32553255 assert(Op->getNumValues() == 2 && "Expected a CC and non-CC result");
3256 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), Op->getVTList(),
3257 Glued, CC);
3256 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), Op->getVTList(), Glued,
3257 CC);
32583258 }
32593259
32603260 unsigned Id = cast(Op.getOperand(0))->getZExtValue();
42104210
42114211 SDValue
42124212 SystemZTargetLowering::lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG,
4213 unsigned UnpackHigh) const {
4213 unsigned UnpackHigh) const {
42144214 SDValue PackedOp = Op.getOperand(0);
42154215 EVT OutVT = Op.getValueType();
42164216 EVT InVT = PackedOp.getValueType();
45724572 }
45734573 return Op;
45744574 } else if ((Opcode == ISD::SIGN_EXTEND_VECTOR_INREG ||
4575 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG ||
4576 Opcode == ISD::ANY_EXTEND_VECTOR_INREG) &&
4577 canTreatAsByteVector(Op.getValueType()) &&
4575 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG ||
4576 Opcode == ISD::ANY_EXTEND_VECTOR_INREG) &&
4577 canTreatAsByteVector(Op.getValueType()) &&
45784578 canTreatAsByteVector(Op.getOperand(0).getValueType())) {
45794579 // Make sure that only the unextended bits are significant.
45804580 EVT ExtVT = Op.getValueType();
45854585 unsigned SubByte = Byte % ExtBytesPerElement;
45864586 unsigned MinSubByte = ExtBytesPerElement - OpBytesPerElement;
45874587 if (SubByte < MinSubByte ||
4588 SubByte + BytesPerElement > ExtBytesPerElement)
4589 break;
4588 SubByte + BytesPerElement > ExtBytesPerElement)
4589 break;
45904590 // Get the byte offset of the unextended element
45914591 Byte = Byte / ExtBytesPerElement * OpBytesPerElement;
45924592 // ...then add the byte offset relative to that element.
45934593 Byte += SubByte - MinSubByte;
45944594 if (Byte % BytesPerElement != 0)
4595 break;
4595 break;
45964596 Op = Op.getOperand(0);
45974597 Index = Byte / BytesPerElement;
45984598 Force = true;
480480 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
481481 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
482482 SDValue lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG,
483 unsigned UnpackHigh) const;
483 unsigned UnpackHigh) const;
484484 SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;
485485
486486 SDValue combineExtract(SDLoc DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
547547 return false;
548548 }
549549
550 void
551 SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
552 MachineBasicBlock::iterator MBBI, DebugLoc DL,
553 unsigned DestReg, unsigned SrcReg,
554 bool KillSrc) const {
550 void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
551 MachineBasicBlock::iterator MBBI,
552 DebugLoc DL, unsigned DestReg,
553 unsigned SrcReg, bool KillSrc) const {
555554 // Split 128-bit GPR moves into two 64-bit moves. This handles ADDR128 too.
556555 if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
557556 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
589588 .addReg(SrcReg, getKillRegState(KillSrc));
590589 }
591590
592 void
593 SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
594 MachineBasicBlock::iterator MBBI,
595 unsigned SrcReg, bool isKill,
596 int FrameIdx,
597 const TargetRegisterClass *RC,
598 const TargetRegisterInfo *TRI) const {
591 void SystemZInstrInfo::storeRegToStackSlot(
592 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg,
593 bool isKill, int FrameIdx, const TargetRegisterClass *RC,
594 const TargetRegisterInfo *TRI) const {
599595 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
600596
601597 // Callers may expect a single instruction, so keep 128-bit moves
603599 unsigned LoadOpcode, StoreOpcode;
604600 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
605601 addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
606 .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
607 }
608
609 void
610 SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
611 MachineBasicBlock::iterator MBBI,
612 unsigned DestReg, int FrameIdx,
613 const TargetRegisterClass *RC,
614 const TargetRegisterInfo *TRI) const {
602 .addReg(SrcReg, getKillRegState(isKill)),
603 FrameIdx);
604 }
605
606 void SystemZInstrInfo::loadRegFromStackSlot(
607 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg,
608 int FrameIdx, const TargetRegisterClass *RC,
609 const TargetRegisterInfo *TRI) const {
615610 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
616611
617612 // Callers may expect a single instruction, so keep 128-bit moves
855855 MCContext &Ctx,
856856 MCStreamer &Out) override;
857857 void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
858 MCStreamer &Out) override;
858 MCStreamer &Out) override;
859859
860860 private:
861861 void EmitAdjustRSP(MCContext &Ctx, MCStreamer &Out, long Offset) {
12461246 getContext().getDirectionalLocalSymbol(IntVal, IDVal == "b");
12471247 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
12481248 const MCExpr *Val =
1249 MCSymbolRefExpr::create(Sym, Variant, getContext());
1249 MCSymbolRefExpr::create(Sym, Variant, getContext());
12501250 if (IDVal == "b" && Sym->isUndefined())
12511251 return Error(Loc, "invalid reference to undefined symbol");
12521252 StringRef Identifier = Sym->getName();
19941994 }
19951995
19961996 // Validate the scale amount.
1997 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
1997 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
19981998 ScaleVal != 1) {
19991999 Error(Loc, "scale factor in 16-bit address must be 1");
20002000 return nullptr;
2001 }
2002 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
2001 }
2002 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 &&
2003 ScaleVal != 8) {
20032004 Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
20042005 return nullptr;
20052006 }
2287022870 InputVector.getOpcode() == ISD::BITCAST &&
2287122871 dyn_cast(InputVector.getOperand(0))) {
2287222872 uint64_t ExtractedElt =
22873 cast(N->getOperand(1))->getZExtValue();
22873 cast(N->getOperand(1))->getZExtValue();
2287422874 uint64_t InputValue =
22875 cast(InputVector.getOperand(0))->getZExtValue();
22875 cast(InputVector.getOperand(0))->getZExtValue();
2287622876 uint64_t Res = (InputValue >> ExtractedElt) & 1;
2287722877 return DAG.getConstant(Res, dl, MVT::i1);
2287822878 }
2481324813 ShuffleVec[i] = i * SizeRatio;
2481424814
2481524815 // Can't shuffle using an illegal type.
24816 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
24817 && "WideVecVT should be legal");
24816 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
24817 "WideVecVT should be legal");
2481824818 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
2481924819 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
2482024820 }
2490524905 ShuffleVec[i] = i * SizeRatio;
2490624906
2490724907 // Can't shuffle using an illegal type.
24908 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
24909 && "WideVecVT should be legal");
24908 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
24909 "WideVecVT should be legal");
2491024910
2491124911 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
2491224912 DAG.getUNDEF(WideVecVT),
231231 if (Instruction *OI = dyn_cast(O)) {
232232 // Unify def-use chains if they interfere.
233233 ECs.unionSets(I, OI);
234 if (SeenInsts.find(I)->second != badRange())
234 if (SeenInsts.find(I)->second != badRange())
235235 Worklist.push_back(OI);
236236 } else if (!isa(O)) {
237237 // Not an instruction or ConstantFP? we can't do anything.
303303 for (Value *O : I->operands()) {
304304 if (Instruction *OI = dyn_cast(O)) {
305305 assert(SeenInsts.find(OI) != SeenInsts.end() &&
306 "def not seen before use!");
306 "def not seen before use!");
307307 OpRanges.push_back(SeenInsts.find(OI)->second);
308308 } else if (ConstantFP *CF = dyn_cast(O)) {
309309 // Work out if the floating point number can be losslessly represented
322322 // we're in fast math mode.
323323 if (!F.isFinite() ||
324324 (F.isZero() && F.isNegative() && isa(I) &&
325 !I->hasNoSignedZeros())) {
325 !I->hasNoSignedZeros())) {
326326 seen(I, badRange());
327327 Abort = true;
328328 break;