llvm.org GIT mirror llvm / 095734c
[C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206254 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 6 years ago
19 changed file(s) with 95 addition(s) and 95 deletion(s). Raw diff Collapse all Expand all
14851485 }
14861486
14871487 void addValue(const RecordVal &RV) {
1488 assert(getValue(RV.getNameInit()) == 0 && "Value already added!");
1488 assert(getValue(RV.getNameInit()) == nullptr && "Value already added!");
14891489 Values.push_back(RV);
14901490 if (Values.size() > 1)
14911491 // Keep NAME at the end of the list. It makes record dumps a
305305 /// Register record if this token is singleton register.
306306 Record *SingletonReg;
307307
308 explicit AsmOperand(StringRef T) : Token(T), Class(0), SubOpIdx(-1),
309 SingletonReg(0) {}
308 explicit AsmOperand(StringRef T) : Token(T), Class(nullptr), SubOpIdx(-1),
309 SingletonReg(nullptr) {}
310310 };
311311
312312 /// ResOperand - This represents a single operand in the result instruction
665665 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
666666 std::map::const_iterator I =
667667 SubtargetFeatures.find(Def);
668 return I == SubtargetFeatures.end() ? 0 : I->second;
668 return I == SubtargetFeatures.end() ? nullptr : I->second;
669669 }
670670
671671 RecordKeeper &getRecords() const {
10171017 // RegisterOperand may have an associated ParserMatchClass. If it does,
10181018 // use it, else just fall back to the underlying register class.
10191019 const RecordVal *R = Rec->getValue("ParserMatchClass");
1020 if (R == 0 || R->getValue() == 0)
1020 if (!R || !R->getValue())
10211021 PrintFatalError("Record `" + Rec->getName() +
10221022 "' does not have a ParserMatchClass!\n");
10231023
18961896 }
18971897 case MatchableInfo::ResOperand::RegOperand: {
18981898 std::string Reg, Name;
1899 if (OpInfo.Register == 0) {
1899 if (!OpInfo.Register) {
19001900 Name = "reg0";
19011901 Reg = "0";
19021902 } else {
23182318 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
23192319 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
23202320
2321 if (F == 0)
2321 if (!F)
23222322 PrintFatalError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
23232323 "' is not marked as an AssemblerPredicate!");
23242324
151151
152152 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) {
153153 const AsmWriterInst *Inst = getAsmWriterInstByID(i);
154 if (Inst == 0)
154 if (!Inst)
155155 continue; // PHI, INLINEASM, CFI_INSTRUCTION, etc.
156156
157157 std::string Command;
300300 // representation.
301301 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) {
302302 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions->at(i)];
303 if (AWI != 0 &&
303 if (AWI &&
304304 AWI->Operands[0].OperandType ==
305305 AsmWriterOperand::isLiteralTextOperand &&
306306 !AWI->Operands[0].Str.empty()) {
316316 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) {
317317 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions->at(i)];
318318 unsigned Idx;
319 if (AWI == 0) {
319 if (!AWI) {
320320 // Something not handled by the asmwriter printer.
321321 Idx = ~0U;
322322 } else if (AWI->Operands[0].OperandType !=
845845 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
846846 // FIXME: We may need to handle these situations.
847847 delete IAP;
848 IAP = 0;
848 IAP = nullptr;
849849 CantHandle = true;
850850 break;
851851 }
8282 return false;
8383
8484 for (unsigned i = 0, e = LegalTypes.size(); i != e; ++i)
85 if (Pred == 0 || Pred(LegalTypes[i]))
85 if (!Pred || Pred(LegalTypes[i]))
8686 TypeVec.push_back(LegalTypes[i]);
8787
8888 // If we have nothing that matches the predicate, bail out.
975975
976976 // Both RegisterClass and RegisterOperand operands derive their types from a
977977 // register class def.
978 Record *RC = 0;
978 Record *RC = nullptr;
979979 if (Operand->isSubClassOf("RegisterClass"))
980980 RC = Operand;
981981 else if (Operand->isSubClassOf("RegisterOperand"))
10931093
10941094 // Get the result tree.
10951095 DagInit *Tree = Operator->getValueAsDag("Fragment");
1096 Record *Op = 0;
1096 Record *Op = nullptr;
10971097 if (Tree)
10981098 if (DefInit *DI = dyn_cast(Tree->getOperator()))
10991099 Op = DI->getDef();
12551255 /// PatFrag references.
12561256 TreePatternNode *TreePatternNode::InlinePatternFragments(TreePattern &TP) {
12571257 if (TP.hasError())
1258 return 0;
1258 return nullptr;
12591259
12601260 if (isLeaf())
12611261 return this; // nothing to do.
12841284 if (Frag->getNumArgs() != Children.size()) {
12851285 TP.error("'" + Op->getName() + "' fragment requires " +
12861286 utostr(Frag->getNumArgs()) + " operands!");
1287 return 0;
1287 return nullptr;
12881288 }
12891289
12901290 TreePatternNode *FragTree = Frag->getOnlyTree()->clone();
14341434 if (getOperator() != CDP.get_intrinsic_void_sdnode() &&
14351435 getOperator() != CDP.get_intrinsic_w_chain_sdnode() &&
14361436 getOperator() != CDP.get_intrinsic_wo_chain_sdnode())
1437 return 0;
1437 return nullptr;
14381438
14391439 unsigned IID = cast(getChild(0)->getLeafValue())->getValue();
14401440 return &CDP.getIntrinsicInfo(IID);
14441444 /// return the ComplexPattern information, otherwise return null.
14451445 const ComplexPattern *
14461446 TreePatternNode::getComplexPatternInfo(const CodeGenDAGPatterns &CGP) const {
1447 if (!isLeaf()) return 0;
1447 if (!isLeaf()) return nullptr;
14481448
14491449 DefInit *DI = dyn_cast(getLeafValue());
14501450 if (DI && DI->getDef()->isSubClassOf("ComplexPattern"))
14511451 return &CGP.getComplexPattern(DI->getDef());
1452 return 0;
1452 return nullptr;
14531453 }
14541454
14551455 /// NodeHasProperty - Return true if this node has the specified property.
18871887 if (BitsInit *BI = dyn_cast(TheInit)) {
18881888 // Turn this into an IntInit.
18891889 Init *II = BI->convertInitializerTo(IntRecTy::get());
1890 if (II == 0 || !isa(II))
1890 if (!II || !isa(II))
18911891 error("Bits value must be constants!");
18921892 return ParseTreePattern(II, OpName);
18931893 }
27382738
27392739 // Check that all of the results occur first in the list.
27402740 std::vector Results;
2741 TreePatternNode *Res0Node = 0;
2741 TreePatternNode *Res0Node = nullptr;
27422742 for (unsigned i = 0; i != NumResults; ++i) {
27432743 if (i == CGI.Operands.size())
27442744 I->error("'" + InstResults.begin()->first +
27472747
27482748 // Check that it exists in InstResults.
27492749 TreePatternNode *RNode = InstResults[OpName];
2750 if (RNode == 0)
2750 if (!RNode)
27512751 I->error("Operand $" + OpName + " does not exist in operand list!");
27522752
27532753 if (i == 0)
27542754 Res0Node = RNode;
27552755 Record *R = cast(RNode->getLeafValue())->getDef();
2756 if (R == 0)
2756 if (!R)
27572757 I->error("Operand $" + OpName + " should be a set destination: all "
27582758 "outputs must occur before inputs in operand list!");
27592759
28102810
28112811 // Promote the xform function to be an explicit node if set.
28122812 if (Record *Xform = OpNode->getTransformFn()) {
2813 OpNode->setTransformFn(0);
2813 OpNode->setTransformFn(nullptr);
28142814 std::vector Children;
28152815 Children.push_back(OpNode);
28162816 OpNode = new TreePatternNode(Xform, Children, OpNode->getNumTypes());
28542854 std::vector Instrs = Records.getAllDerivedDefinitions("Instruction");
28552855
28562856 for (unsigned i = 0, e = Instrs.size(); i != e; ++i) {
2857 ListInit *LI = 0;
2857 ListInit *LI = nullptr;
28582858
28592859 if (isa(Instrs[i]->getValueInit("Pattern")))
28602860 LI = Instrs[i]->getValueAsListInit("Pattern");
28892889 // Create and insert the instruction.
28902890 std::vector ImpResults;
28912891 Instructions.insert(std::make_pair(Instrs[i],
2892 DAGInstruction(0, Results, Operands, ImpResults)));
2892 DAGInstruction(nullptr, Results, Operands, ImpResults)));
28932893 continue; // no pattern.
28942894 }
28952895
29062906 E = Instructions.end(); II != E; ++II) {
29072907 DAGInstruction &TheInst = II->second;
29082908 TreePattern *I = TheInst.getPattern();
2909 if (I == 0) continue; // No pattern.
2909 if (!I) continue; // No pattern.
29102910
29112911 // FIXME: Assume only the first tree is the pattern. The others are clobber
29122912 // nodes.
29822982 // they don't exist in the input pattern.
29832983 for (std::map::iterator
29842984 I = DstNames.begin(), E = DstNames.end(); I != E; ++I) {
2985 if (SrcNames[I->first].first == 0)
2985 if (SrcNames[I->first].first == nullptr)
29862986 Pattern->error("Pattern has input without matching name in output: $" +
29872987 I->first);
29882988 }
29912991 // name isn't used in the dest, and isn't used to tie two values together.
29922992 for (std::map::iterator
29932993 I = SrcNames.begin(), E = SrcNames.end(); I != E; ++I)
2994 if (DstNames[I->first].first == 0 && SrcNames[I->first].second == 1)
2994 if (DstNames[I->first].first == nullptr && SrcNames[I->first].second == 1)
29952995 Pattern->error("Pattern has dead named input: $" + I->first);
29962996
29972997 PatternsToMatch.push_back(PTM);
32793279 for (unsigned ii = 0, ee = DstPattern->getNumChildren(); ii != ee; ++ii) {
32803280 TreePatternNode *OpNode = DstPattern->getChild(ii);
32813281 if (Record *Xform = OpNode->getTransformFn()) {
3282 OpNode->setTransformFn(0);
3282 OpNode->setTransformFn(nullptr);
32833283 std::vector Children;
32843284 Children.push_back(OpNode);
32853285 OpNode = new TreePatternNode(Xform, Children, OpNode->getNumTypes());
6868 std::string EncoderMethod;
6969 std::string OperandType = "OPERAND_UNKNOWN";
7070 unsigned NumOps = 1;
71 DagInit *MIOpInfo = 0;
71 DagInit *MIOpInfo = nullptr;
7272 if (Rec->isSubClassOf("RegisterOperand")) {
7373 PrintMethod = Rec->getValueAsString("PrintMethod");
7474 } else if (Rec->isSubClassOf("Operand")) {
181181
182182 // Find the suboperand number involved.
183183 DagInit *MIOpInfo = OperandList[OpIdx].MIOperandInfo;
184 if (MIOpInfo == 0)
184 if (!MIOpInfo)
185185 PrintFatalError(TheDef->getName() + ": unknown suboperand name in '" + Op + "'");
186186
187187 // Find the operand with the right name.
289289 //===----------------------------------------------------------------------===//
290290
291291 CodeGenInstruction::CodeGenInstruction(Record *R)
292 : TheDef(R), Operands(R), InferredFrom(0) {
292 : TheDef(R), Operands(R), InferredFrom(nullptr) {
293293 Namespace = R->getValueAsString("Namespace");
294294 AsmString = R->getValueAsString("AsmString");
295295
435435 ResultOperand &ResOp) {
436436 Init *Arg = Result->getArg(AliasOpNo);
437437 DefInit *ADI = dyn_cast(Arg);
438 Record *ResultRecord = ADI ? ADI->getDef() : 0;
438 Record *ResultRecord = ADI ? ADI->getDef() : nullptr;
439439
440440 if (ADI && ADI->getDef() == InstOpRec) {
441441 // If the operand is a record, it must have a name, and the record type
503503 // throw TGError(Loc, "reg0 used for result that is not an "
504504 // "OptionalDefOperand!");
505505
506 ResOp = ResultOperand(static_cast(0));
506 ResOp = ResultOperand(static_cast(nullptr));
507507 return true;
508508 }
509509
541541
542542 // Verify that the root of the result is an instruction.
543543 DefInit *DI = dyn_cast(Result->getOperator());
544 if (DI == 0 || !DI->getDef()->isSubClassOf("Instruction"))
544 if (!DI || !DI->getDef()->isSubClassOf("Instruction"))
545545 PrintFatalError(R->getLoc(),
546546 "result of inst alias should be an instruction");
547547
325325 const std::vector &RelatedInstrVec = RowInstrMap[KeyValue];
326326
327327 ListInit *ColFields = InstrMapDesc.getColFields();
328 Record *MatchInstr = NULL;
328 Record *MatchInstr = nullptr;
329329
330330 for (unsigned i = 0, e = RelatedInstrVec.size(); i < e; i++) {
331331 bool MatchFound = true;
377377 unsigned RelExists = 0;
378378 if (ColInstrs.size()) {
379379 for (unsigned j = 0; j < NumCol; j++) {
380 if (ColInstrs[j] != NULL) {
380 if (ColInstrs[j] != nullptr) {
381381 RelExists = 1;
382382 OutStr += ", ";
383383 OutStr += TargetName;
4040
4141 CodeGenSubRegIndex::CodeGenSubRegIndex(StringRef N, StringRef Nspace,
4242 unsigned Enum)
43 : TheDef(0), Name(N), Namespace(Nspace), Size(-1), Offset(-1),
43 : TheDef(nullptr), Name(N), Namespace(Nspace), Size(-1), Offset(-1),
4444 EnumValue(Enum), LaneMask(0), AllSuperRegsCovered(true) {
4545 }
4646
724724 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank,
725725 StringRef Name, Key Props)
726726 : Members(*Props.Members),
727 TheDef(0),
727 TheDef(nullptr),
728728 Name(Name),
729729 TopoSigs(RegBank.getNumTopoSigs()),
730730 EnumValue(-1),
13111311 E = UberSets.end(); I != E; ++I) {
13121312
13131313 // Initialize all unit weights in this set, and remember the max units/reg.
1314 const CodeGenRegister *Reg = 0;
1314 const CodeGenRegister *Reg = nullptr;
13151315 unsigned MaxWeight = 0, Weight = 0;
13161316 for (RegUnitIterator UnitI(I->Regs); UnitI.isValid(); ++UnitI) {
13171317 if (Reg != UnitI.getReg()) {
19221922 CodeGenRegBank::getRegClassForRegister(Record *R) {
19231923 const CodeGenRegister *Reg = getReg(R);
19241924 ArrayRef RCs = getRegClasses();
1925 const CodeGenRegisterClass *FoundRC = 0;
1925 const CodeGenRegisterClass *FoundRC = nullptr;
19261926 for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
19271927 const CodeGenRegisterClass &RC = *RCs[i];
19281928 if (!RC.contains(Reg))
19371937
19381938 // If a register's classes have different types, return null.
19391939 if (RC.getValueTypes() != FoundRC->getValueTypes())
1940 return 0;
1940 return nullptr;
19411941
19421942 // Check to see if the previously found class that contains
19431943 // the register is a subclass of the current class. If so,
19551955
19561956 // Multiple classes, and neither is a superclass of the other.
19571957 // Return null.
1958 return 0;
1958 return nullptr;
19591959 }
19601960 return FoundRC;
19611961 }
428428 const CodeGenProcModel &ProcModel) const {
429429
430430 const CodeGenSchedRW &SchedWrite = getSchedRW(RWIdx, IsRead);
431 Record *AliasDef = 0;
431 Record *AliasDef = nullptr;
432432 for (RecIter AI = SchedWrite.Aliases.begin(), AE = SchedWrite.Aliases.end();
433433 AI != AE; ++AI) {
434434 const CodeGenSchedRW &AliasRW = getSchedRW((*AI)->getValueAsDef("AliasRW"));
13141314 IdxVec ProcIndices(I->ProcIndices.begin(), I->ProcIndices.end());
13151315 CodeGenSchedTransition SCTrans;
13161316 SCTrans.ToClassIdx =
1317 SchedModels.addSchedClass(/*ItinClassDef=*/0, OperWritesVariant,
1317 SchedModels.addSchedClass(/*ItinClassDef=*/nullptr, OperWritesVariant,
13181318 OperReadsVariant, ProcIndices);
13191319 SCTrans.ProcIndices = ProcIndices;
13201320 // The final PredTerm is unique set of predicates guarding the transition.
16201620 if (ProcResKind->isSubClassOf("ProcResourceUnits"))
16211621 return ProcResKind;
16221622
1623 Record *ProcUnitDef = 0;
1623 Record *ProcUnitDef = nullptr;
16241624 RecVec ProcResourceDefs =
16251625 Records.getAllDerivedDefinitions("ProcResourceUnits");
16261626
132132 /// getTarget - Return the current instance of the Target class.
133133 ///
134134 CodeGenTarget::CodeGenTarget(RecordKeeper &records)
135 : Records(records), RegBank(0), SchedModels(0) {
135 : Records(records), RegBank(nullptr), SchedModels(nullptr) {
136136 std::vector Targets = Records.getAllDerivedDefinitions("Target");
137137 if (Targets.size() == 0)
138138 PrintFatalError("ERROR: No 'Target' subclasses defined!");
225225 const StringMap &Regs = getRegBank().getRegistersByName();
226226 StringMap::const_iterator I = Regs.find(Name);
227227 if (I == Regs.end())
228 return 0;
228 return nullptr;
229229 return I->second;
230230 }
231231
286286
287287 DenseMap::const_iterator
288288 I = Insts.find(Rec);
289 if (Rec == 0 || I == Insts.end())
289 if (!Rec || I == Insts.end())
290290 PrintFatalError(Twine("Could not find '") + Name + "' instruction!");
291291 return I->second;
292292 }
300300 "GC_LABEL", "KILL", "EXTRACT_SUBREG", "INSERT_SUBREG",
301301 "IMPLICIT_DEF", "SUBREG_TO_REG", "COPY_TO_REGCLASS", "DBG_VALUE",
302302 "REG_SEQUENCE", "COPY", "BUNDLE", "LIFETIME_START",
303 "LIFETIME_END", "STACKMAP", "PATCHPOINT", 0};
303 "LIFETIME_END", "STACKMAP", "PATCHPOINT", nullptr};
304304 const DenseMap &Insts = getInstructions();
305305 for (const char *const *p = FixedInstrs; *p; ++p) {
306306 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records);
4242 for (; Cur && Cur->getNext() != Other; Cur = Cur->getNext())
4343 /*empty*/;
4444
45 if (Cur == 0) return 0;
45 if (!Cur) return nullptr;
4646 Cur->takeNext();
4747 Cur->setNext(Other->takeNext());
4848 return this;
107107 void ScopeMatcher::printImpl(raw_ostream &OS, unsigned indent) const {
108108 OS.indent(indent) << "Scope\n";
109109 for (unsigned i = 0, e = getNumChildren(); i != e; ++i) {
110 if (getChild(i) == 0)
110 if (!getChild(i))
111111 OS.indent(indent+1) << "NULL POINTER\n";
112112 else
113113 getChild(i)->print(OS, indent+2);
141141 switch (N->getKind()) {
142142 case Matcher::Scope: {
143143 const ScopeMatcher *SM = cast(N);
144 assert(SM->getNext() == 0 && "Shouldn't have next after scope");
144 assert(SM->getNext() == nullptr && "Shouldn't have next after scope");
145145
146146 unsigned StartIdx = CurrentIdx;
147147
724724 }
725725
726726 static void BuildHistogram(const Matcher *M, std::vector &OpcodeFreq){
727 for (; M != 0; M = M->getNext()) {
727 for (; M != nullptr; M = M->getNext()) {
728728 // Count this node.
729729 if (unsigned(M->getKind()) >= OpcodeFreq.size())
730730 OpcodeFreq.resize(M->getKind()+1);
143143 MatcherGen::MatcherGen(const PatternToMatch &pattern,
144144 const CodeGenDAGPatterns &cgp)
145145 : Pattern(pattern), CGP(cgp), NextRecordedOperandNo(0),
146 TheMatcher(0), CurPredicate(0) {
146 TheMatcher(nullptr), CurPredicate(nullptr) {
147147 // We need to produce the matcher tree for the patterns source pattern. To do
148148 // this we need to match the structure as well as the types. To do the type
149149 // matching, we want to figure out the fewest number of type checks we need to
181181
182182 /// AddMatcher - Add a matcher node to the current graph we're building.
183183 void MatcherGen::AddMatcher(Matcher *NewNode) {
184 if (CurPredicate != 0)
184 if (CurPredicate)
185185 CurPredicate->setNext(NewNode);
186186 else
187187 TheMatcher = NewNode;
217217 }
218218
219219 DefInit *DI = dyn_cast(N->getLeafValue());
220 if (DI == 0) {
220 if (!DI) {
221221 errs() << "Unknown leaf kind: " << *N << "\n";
222222 abort();
223223 }
599599 }
600600
601601 if (Def->getName() == "zero_reg") {
602 AddMatcher(new EmitRegisterMatcher(0, N->getType(0)));
602 AddMatcher(new EmitRegisterMatcher(nullptr, N->getType(0)));
603603 ResultOps.push_back(NextRecordedOperandNo++);
604604 return;
605605 }
641641 else if (/*isRoot*/ N == Pattern.getDstPattern())
642642 InstPatNode = Pattern.getSrcPattern();
643643 else
644 return 0;
644 return nullptr;
645645
646646 if (InstPatNode && !InstPatNode->isLeaf() &&
647647 InstPatNode->getOperator()->getName() == "set")
805805 if (isRoot && !Pattern.getDstRegs().empty()) {
806806 // If the root came from an implicit def in the instruction handling stuff,
807807 // don't re-add it.
808 Record *HandledReg = 0;
808 Record *HandledReg = nullptr;
809809 if (II.HasOneImplicitDefWithKnownVT(CGT) != MVT::Other)
810810 HandledReg = II.ImplicitDefs[0];
811811
923923 if (!Pattern.getDstRegs().empty()) {
924924 // If the root came from an implicit def in the instruction handling stuff,
925925 // don't re-add it.
926 Record *HandledReg = 0;
926 Record *HandledReg = nullptr;
927927 const TreePatternNode *DstPat = Pattern.getDstPattern();
928928 if (!DstPat->isLeaf() &&DstPat->getOperator()->isSubClassOf("Instruction")){
929929 const CodeGenTarget &CGT = CGP.getTargetInfo();
961961
962962 // Generate the code for the matcher.
963963 if (Gen.EmitMatcherCode(Variant))
964 return 0;
964 return nullptr;
965965
966966 // FIXME2: Kill extra MoveParent commands at the end of the matcher sequence.
967967 // FIXME2: Split result code out to another table, and make the matcher end
2525 const CodeGenDAGPatterns &CGP) {
2626 // If we reached the end of the chain, we're done.
2727 Matcher *N = MatcherPtr.get();
28 if (N == 0) return;
28 if (!N) return;
2929
3030 // If we have a scope node, walk down all of the children.
3131 if (ScopeMatcher *Scope = dyn_cast(N)) {
4040 // If we found a movechild node with a node that comes in a 'foochild' form,
4141 // transform it.
4242 if (MoveChildMatcher *MC = dyn_cast(N)) {
43 Matcher *New = 0;
43 Matcher *New = nullptr;
4444 if (RecordMatcher *RM = dyn_cast(MC->getNext()))
4545 if (MC->getChildNo() < 8) // Only have RecordChild0...7
4646 New = new RecordChildMatcher(MC->getChildNo(), RM->getWhatFor(),
190190 // Recursively scan for a PatternPredicate.
191191 // If we reached the end of the chain, we're done.
192192 Matcher *N = MatcherPtr.get();
193 if (N == 0) return;
193 if (!N) return;
194194
195195 // Walk down all members of a scope node.
196196 if (ScopeMatcher *Scope = dyn_cast(N)) {
205205 // If this node isn't a CheckPatternPredicateMatcher we keep scanning until
206206 // we find one.
207207 CheckPatternPredicateMatcher *CPPM =dyn_cast(N);
208 if (CPPM == 0)
208 if (!CPPM)
209209 return SinkPatternPredicates(N->getNextPtr());
210210
211211 // Ok, we found one, lets try to sink it. Check if we can sink it past the
235235 for (; M; M = M->getNext())
236236 if (M->getKind() == Kind)
237237 return M;
238 return 0;
238 return nullptr;
239239 }
240240
241241
254254 static void FactorNodes(std::unique_ptr &MatcherPtr) {
255255 // If we reached the end of the chain, we're done.
256256 Matcher *N = MatcherPtr.get();
257 if (N == 0) return;
257 if (!N) return;
258258
259259 // If this is not a push node, just scan for one.
260260 ScopeMatcher *Scope = dyn_cast(N);
261 if (Scope == 0)
261 if (!Scope)
262262 return FactorNodes(N->getNextPtr());
263263
264264 // Okay, pull together the children of the scope node into a vector so we can
334334 // or the same as what we're looking for. If so, reorder it.
335335 if (Optn->isSimplePredicateOrRecordNode()) {
336336 Matcher *M2 = FindNodeWithKind(ScanMatcher, Optn->getKind());
337 if (M2 != 0 && M2 != ScanMatcher &&
337 if (M2 && M2 != ScanMatcher &&
338338 M2->canMoveBefore(ScanMatcher) &&
339339 (M2->isEqual(Optn) || M2->isContradictory(Optn))) {
340340 Matcher *MatcherWithoutM2 = ScanMatcher->unlinkNode(M2);
398398 }
399399
400400 if (NewOptionsToMatch.empty()) {
401 MatcherPtr.reset(0);
401 MatcherPtr.reset(nullptr);
402402 return;
403403 }
404404
426426 CheckTypeMatcher *CTM =
427427 cast_or_null(FindNodeWithKind(NewOptionsToMatch[i],
428428 Matcher::CheckType));
429 if (CTM == 0 ||
429 if (!CTM ||
430430 // iPTR checks could alias any other case without us knowing, don't
431431 // bother with them.
432432 CTM->getType() == MVT::iPTR ||
160160 stateNum(currentStateNum++), isInitial(S.isInitial),
161161 stateInfo(S.stateInfo) {}
162162
163 DFA::DFA(): currentState(NULL) {}
163 DFA::DFA(): currentState(nullptr) {}
164164
165165 DFA::~DFA() {
166166 DeleteContainerPointers(states);
485485 //
486486 if (!current->hasTransition(InsnClass) &&
487487 current->canAddInsnClass(InsnClass)) {
488 State *NewState = NULL;
488 State *NewState = nullptr;
489489 current->AddInsnClass(InsnClass, NewStateResources);
490490 assert(NewStateResources.size() && "New states must be generated");
491491
187187 return true;
188188 }
189189
190 const CodeGenRegisterClass *DstRC = 0;
190 const CodeGenRegisterClass *DstRC = nullptr;
191191
192192 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
193193 TreePatternNode *Op = InstPatNode->getChild(i);
251251 Record *OpLeafRec = OpDI->getDef();
252252
253253 // For now, the only other thing we accept is register operands.
254 const CodeGenRegisterClass *RC = 0;
254 const CodeGenRegisterClass *RC = nullptr;
255255 if (OpLeafRec->isSubClassOf("RegisterOperand"))
256256 OpLeafRec = OpLeafRec->getValueAsDef("RegClass");
257257 if (OpLeafRec->isSubClassOf("RegisterClass"))
458458
459459 // For now, ignore instructions where the first operand is not an
460460 // output register.
461 const CodeGenRegisterClass *DstRC = 0;
461 const CodeGenRegisterClass *DstRC = nullptr;
462462 std::string SubRegNo;
463463 if (Op->getName() != "EXTRACT_SUBREG") {
464464 Record *Op0Rec = II.Operands[0].Rec;
346346 unsigned BW,
347347 const FixedLenDecoderEmitter *E)
348348 : AllInstructions(Insts), Opcodes(IDs), Operands(Ops), Filters(),
349 Parent(NULL), BestIndex(-1), BitWidth(BW), Emitter(E) {
349 Parent(nullptr), BestIndex(-1), BitWidth(BW), Emitter(E) {
350350 for (unsigned i = 0; i < BitWidth; ++i)
351351 FilterBitValues.push_back(BIT_UNFILTERED);
352352
17751775 // Determine if Vals[i] actually contributes to the Inst encoding.
17761776 unsigned bi = 0;
17771777 for (; bi < Bits.getNumBits(); ++bi) {
1778 VarInit *Var = 0;
1778 VarInit *Var = nullptr;
17791779 VarBitInit *BI = dyn_cast(Bits.getBit(bi));
17801780 if (BI)
17811781 Var = dyn_cast(BI->getBitVar());
17971797 // Get the bit range for this operand:
17981798 unsigned bitStart = bi++, bitWidth = 1;
17991799 for (; bi < Bits.getNumBits(); ++bi) {
1800 VarInit *Var = 0;
1800 VarInit *Var = nullptr;
18011801 VarBitInit *BI = dyn_cast(Bits.getBit(bi));
18021802 if (BI)
18031803 Var = dyn_cast(BI->getBitVar());
18361836
18371837 RecordVal *DecoderString = TypeRecord->getValue("DecoderMethod");
18381838 StringInit *String = DecoderString ?
1839 dyn_cast(DecoderString->getValue()) : 0;
1839 dyn_cast(DecoderString->getValue()) : nullptr;
18401840 if (String && String->getValue() != "")
18411841 Decoder = String->getValue();
18421842
18651865
18661866 DecoderString = TypeRecord->getValue("DecoderMethod");
18671867 String = DecoderString ?
1868 dyn_cast(DecoderString->getValue()) : 0;
1868 dyn_cast(DecoderString->getValue()) : nullptr;
18691869 if (!isReg && String && String->getValue() != "")
18701870 Decoder = String->getValue();
18711871
19371937
19381938 RecordVal *DecoderString = TypeRecord->getValue("DecoderMethod");
19391939 StringInit *String = DecoderString ?
1940 dyn_cast(DecoderString->getValue()) : 0;
1940 dyn_cast(DecoderString->getValue()) : nullptr;
19411941 if (!isReg && String && String->getValue() != "")
19421942 Decoder = String->getValue();
19431943
19471947 unsigned Offset = 0;
19481948
19491949 for (unsigned bi = 0; bi < Bits.getNumBits(); ++bi) {
1950 VarInit *Var = 0;
1950 VarInit *Var = nullptr;
19511951 VarBitInit *BI = dyn_cast(Bits.getBit(bi));
19521952 if (BI)
19531953 Var = dyn_cast(BI->getBitVar());
317317 }
318318
319319 // Set is not expandable.
320 return 0;
321 }
322
320 return nullptr;
321 }
322
630630 for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) {
631631 Record *PRDef = ProcModel.ProcResourceDefs[i];
632632
633 Record *SuperDef = 0;
633 Record *SuperDef = nullptr;
634634 unsigned SuperIdx = 0;
635635 unsigned NumUnits = 0;
636636 int BufferSize = PRDef->getValueAsInt("BufferSize");
675675 if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes"))
676676 return SchedWrite.TheDef;
677677
678 Record *AliasDef = 0;
678 Record *AliasDef = nullptr;
679679 for (RecIter AI = SchedWrite.Aliases.begin(), AE = SchedWrite.Aliases.end();
680680 AI != AE; ++AI) {
681681 const CodeGenSchedRW &AliasRW =
695695 return AliasDef;
696696
697697 // Check this processor's list of write resources.
698 Record *ResDef = 0;
698 Record *ResDef = nullptr;
699699 for (RecIter WRI = ProcModel.WriteResDefs.begin(),
700700 WRE = ProcModel.WriteResDefs.end(); WRI != WRE; ++WRI) {
701701 if (!(*WRI)->isSubClassOf("WriteRes"))
729729 return SchedRead.TheDef;
730730
731731 // Check this processor's list of aliases for SchedRead.
732 Record *AliasDef = 0;
732 Record *AliasDef = nullptr;
733733 for (RecIter AI = SchedRead.Aliases.begin(), AE = SchedRead.Aliases.end();
734734 AI != AE; ++AI) {
735735 const CodeGenSchedRW &AliasRW =
749749 return AliasDef;
750750
751751 // Check this processor's ReadAdvanceList.
752 Record *ResDef = 0;
752 Record *ResDef = nullptr;
753753 for (RecIter RAI = ProcModel.ReadAdvanceDefs.begin(),
754754 RAE = ProcModel.ReadAdvanceDefs.end(); RAI != RAE; ++RAI) {
755755 if (!(*RAI)->isSubClassOf("ReadAdvance"))
883883 if (!SCI->InstRWs.empty()) {
884884 // This class has a default ReadWrite list which can be overriden by
885885 // InstRW definitions.
886 Record *RWDef = 0;
886 Record *RWDef = nullptr;
887887 for (RecIter RWI = SCI->InstRWs.begin(), RWE = SCI->InstRWs.end();
888888 RWI != RWE; ++RWI) {
889889 Record *RWModelDef = (*RWI)->getValueAsDef("SchedModel");
787787
788788 OpcodeType opcodeType = (OpcodeType)-1;
789789
790 ModRMFilter* filter = NULL;
790 ModRMFilter* filter = nullptr;
791791 uint8_t opcodeToSet = 0;
792792
793793 switch (OpMap) {