llvm.org GIT mirror llvm / 08f0ec7
[TargetLowering] SimplifyDemandedBits - Cleanup ANY_EXTEND handling Match SIGN_EXTEND + ZERO_EXTEND handling - will be adding ANY_EXTEND_VECTOR_INREG support in a future patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363716 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 4 months ago
1 changed file(s) with 8 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
14391439 break;
14401440 }
14411441 case ISD::ANY_EXTEND: {
1442 // TODO: Add ISD::ANY_EXTEND_VECTOR_INREG support.
14421443 SDValue Src = Op.getOperand(0);
1443 unsigned InBits = Src.getScalarValueSizeInBits();
1444 EVT SrcVT = Src.getValueType();
1445 unsigned InBits = SrcVT.getScalarSizeInBits();
1446 unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1;
14441447 APInt InDemandedBits = DemandedBits.trunc(InBits);
1445 if (SimplifyDemandedBits(Src, InDemandedBits, Known, TLO, Depth + 1))
1448 APInt InDemandedElts = DemandedElts.zextOrSelf(InElts);
1449 if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO,
1450 Depth + 1))
14461451 return true;
14471452 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1453 assert(Known.getBitWidth() == InBits && "Src width has changed?");
14481454 Known = Known.zext(BitWidth, false /* => any extend */);
14491455 break;
14501456 }