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[DAGCombiner] Added SMAX/SMIN/UMAX/UMIN constant folding We still need to add constant folding of vector comparisons to fold the tests for targets that don't support the respective min/max nodes I needed to update 2011-12-06-AVXVectorExtractCombine to load a vector instead of using a constant vector to prevent it folding Differential Revision: http://reviews.llvm.org/D12118 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245503 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 4 years ago
6 changed file(s) with 258 addition(s) and 592 deletion(s). Raw diff Collapse all Expand all
686686 SDValue N3, SDValue N4);
687687 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
688688 SDValue N3, SDValue N4, SDValue N5);
689
689
690690 // Specialize again based on number of operands for nodes with a VTList
691691 // rather than a single VT.
692692 SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs);
10711071 // target info.
10721072 switch (Opcode) {
10731073 case ISD::ADD:
1074 case ISD::SMIN:
1075 case ISD::SMAX:
1076 case ISD::UMIN:
1077 case ISD::UMAX:
10741078 case ISD::MUL:
10751079 case ISD::MULHU:
10761080 case ISD::MULHS:
244244 SDValue visitUMULO(SDNode *N);
245245 SDValue visitSDIVREM(SDNode *N);
246246 SDValue visitUDIVREM(SDNode *N);
247 SDValue visitIMINMAX(SDNode *N);
247248 SDValue visitAND(SDNode *N);
248249 SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *LocReference);
249250 SDValue visitOR(SDNode *N);
13401341 case ISD::UMULO: return visitUMULO(N);
13411342 case ISD::SDIVREM: return visitSDIVREM(N);
13421343 case ISD::UDIVREM: return visitUDIVREM(N);
1344 case ISD::SMIN:
1345 case ISD::SMAX:
1346 case ISD::UMIN:
1347 case ISD::UMAX: return visitIMINMAX(N);
13431348 case ISD::AND: return visitAND(N);
13441349 case ISD::OR: return visitOR(N);
13451350 case ISD::XOR: return visitXOR(N);
26232628 return SDValue();
26242629 }
26252630
2631 SDValue DAGCombiner::visitIMINMAX(SDNode *N) {
2632 SDValue N0 = N->getOperand(0);
2633 SDValue N1 = N->getOperand(1);
2634 EVT VT = N0.getValueType();
2635
2636 // fold vector ops
2637 if (VT.isVector())
2638 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2639 return FoldedVOp;
2640
2641 // fold (add c1, c2) -> c1+c2
2642 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
2643 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
2644 if (N0C && N1C)
2645 return DAG.FoldConstantArithmetic(N->getOpcode(), SDLoc(N), VT, N0C, N1C);
2646
2647 // canonicalize constant to RHS
2648 if (isConstantIntBuildVectorOrConstantInt(N0) &&
2649 !isConstantIntBuildVectorOrConstantInt(N1))
2650 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0);
2651
2652 return SDValue();
2653 }
2654
26262655 /// If this is a binary operator with two operands of the same opcode, try to
26272656 /// simplify it.
26282657 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
31813181 case ISD::SRA: return std::make_pair(C1.ashr(C2), true);
31823182 case ISD::ROTL: return std::make_pair(C1.rotl(C2), true);
31833183 case ISD::ROTR: return std::make_pair(C1.rotr(C2), true);
3184 case ISD::SMIN: return std::make_pair(C1.sle(C2) ? C1 : C2, true);
3185 case ISD::SMAX: return std::make_pair(C1.sge(C2) ? C1 : C2, true);
3186 case ISD::UMIN: return std::make_pair(C1.ule(C2) ? C1 : C2, true);
3187 case ISD::UMAX: return std::make_pair(C1.uge(C2) ? C1 : C2, true);
31843188 case ISD::UDIV:
31853189 if (!C2.getBoolValue())
31863190 break;
33553359 case ISD::MUL:
33563360 case ISD::SDIV:
33573361 case ISD::SREM:
3362 case ISD::SMIN:
3363 case ISD::SMAX:
3364 case ISD::UMIN:
3365 case ISD::UMAX:
33583366 assert(VT.isInteger() && "This operator does not apply to FP types!");
33593367 assert(N1.getValueType() == N2.getValueType() &&
33603368 N1.getValueType() == VT && "Binary operator types must match!");
52725280 cast(E)->refineAlignment(MMO);
52735281 return SDValue(E, 0);
52745282 }
5275 MaskedGatherSDNode *N =
5283 MaskedGatherSDNode *N =
52765284 new (NodeAllocator) MaskedGatherSDNode(dl.getIROrder(), dl.getDebugLoc(),
52775285 Ops, VTs, VT, MMO);
52785286 CSEMap.InsertNode(N, IP);
33 define void @test(<4 x i32>* nocapture %p) nounwind {
44 ; CHECK-LABEL: test:
55 ; CHECK: vpxor %xmm0, %xmm0, %xmm0
6 ; CHECK-NEXT: vpmaxsd {{.*}}, %xmm0, %xmm0
7 ; CHECK-NEXT: vmovdqu %xmm0, (%rdi)
6 ; CHECK-NEXT: vpmaxsd (%rdi), %xmm0, %xmm0
7 ; CHECK-NEXT: vmovdqu %xmm0, (%rdi)
88 ; CHECK-NEXT: ret
9 %a = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> , <4 x i32> zeroinitializer) nounwind
10 %b = shufflevector <4 x i32> %a, <4 x i32> undef, <8 x i32>
11 %c = shufflevector <8 x i32> %b, <8 x i32> undef, <4 x i32>
12 store <4 x i32> %c, <4 x i32>* %p, align 1
9 %a = load <4 x i32>, <4 x i32>* %p, align 1
10 %b = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %a, <4 x i32> zeroinitializer) nounwind
11 %c = shufflevector <4 x i32> %b, <4 x i32> undef, <8 x i32>
12 %d = shufflevector <8 x i32> %c, <8 x i32> undef, <4 x i32>
13 store <4 x i32> %d, <4 x i32>* %p, align 1
1314 ret void
1415 }
1516
18061806 ;
18071807 ; SSE41-LABEL: max_gt_v4i32c:
18081808 ; SSE41: # BB#0:
1809 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
1810 ; SSE41-NEXT: pmaxsd {{.*}}(%rip), %xmm0
1809 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
18111810 ; SSE41-NEXT: retq
18121811 ;
18131812 ; SSE42-LABEL: max_gt_v4i32c:
18141813 ; SSE42: # BB#0:
1815 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
1816 ; SSE42-NEXT: pmaxsd {{.*}}(%rip), %xmm0
1814 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
18171815 ; SSE42-NEXT: retq
18181816 ;
18191817 ; AVX-LABEL: max_gt_v4i32c:
18201818 ; AVX: # BB#0:
1821 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
1822 ; AVX-NEXT: vpmaxsd {{.*}}(%rip), %xmm0, %xmm0
1819 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
18231820 ; AVX-NEXT: retq
18241821 %1 = insertelement <4 x i32> , i32 -7, i32 0
18251822 %2 = insertelement <4 x i32> , i32 -1, i32 0
18491846 ;
18501847 ; SSE41-LABEL: max_gt_v8i32c:
18511848 ; SSE41: # BB#0:
1852 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
1853 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
1854 ; SSE41-NEXT: pmaxsd {{.*}}(%rip), %xmm0
1855 ; SSE41-NEXT: pmaxsd {{.*}}(%rip), %xmm1
1849 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
1850 ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
18561851 ; SSE41-NEXT: retq
18571852 ;
18581853 ; SSE42-LABEL: max_gt_v8i32c:
18591854 ; SSE42: # BB#0:
1860 ; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
1861 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
1862 ; SSE42-NEXT: pmaxsd {{.*}}(%rip), %xmm0
1863 ; SSE42-NEXT: pmaxsd {{.*}}(%rip), %xmm1
1864 ; SSE42-NEXT: retq
1865 ;
1866 ; AVX1-LABEL: max_gt_v8i32c:
1867 ; AVX1: # BB#0:
1868 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
1869 ; AVX1-NEXT: vpmaxsd {{.*}}(%rip), %xmm0, %xmm0
1870 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,3,5,7]
1871 ; AVX1-NEXT: vpmaxsd {{.*}}(%rip), %xmm1, %xmm1
1872 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
1873 ; AVX1-NEXT: retq
1874 ;
1875 ; AVX2-LABEL: max_gt_v8i32c:
1876 ; AVX2: # BB#0:
1877 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
1878 ; AVX2-NEXT: vpmaxsd {{.*}}(%rip), %ymm0, %ymm0
1879 ; AVX2-NEXT: retq
1880 ;
1881 ; AVX512-LABEL: max_gt_v8i32c:
1882 ; AVX512: # BB#0:
1883 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
1884 ; AVX512-NEXT: vpmaxsd {{.*}}(%rip), %ymm0, %ymm0
1885 ; AVX512-NEXT: retq
1855 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
1856 ; SSE42-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
1857 ; SSE42-NEXT: retq
1858 ;
1859 ; AVX-LABEL: max_gt_v8i32c:
1860 ; AVX: # BB#0:
1861 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
1862 ; AVX-NEXT: retq
18861863 %1 = insertelement <8 x i32> , i32 -7, i32 0
18871864 %2 = insertelement <8 x i32> , i32 -1, i32 0
18881865 %3 = icmp sgt <8 x i32> %1, %2
18931870 define <8 x i16> @max_gt_v8i16c() {
18941871 ; SSE-LABEL: max_gt_v8i16c:
18951872 ; SSE: # BB#0:
1896 ; SSE-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
1897 ; SSE-NEXT: pmaxsw {{.*}}(%rip), %xmm0
1873 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
18981874 ; SSE-NEXT: retq
18991875 ;
19001876 ; AVX-LABEL: max_gt_v8i16c:
19011877 ; AVX: # BB#0:
1902 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
1903 ; AVX-NEXT: vpmaxsw {{.*}}(%rip), %xmm0, %xmm0
1878 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
19041879 ; AVX-NEXT: retq
19051880 %1 = insertelement <8 x i16> , i16 -7, i32 0
19061881 %2 = insertelement <8 x i16> , i16 -1, i32 0
19121887 define <16 x i16> @max_gt_v16i16c() {
19131888 ; SSE-LABEL: max_gt_v16i16c:
19141889 ; SSE: # BB#0:
1915 ; SSE-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
1916 ; SSE-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
1917 ; SSE-NEXT: pmaxsw {{.*}}(%rip), %xmm0
1918 ; SSE-NEXT: pmaxsw {{.*}}(%rip), %xmm1
1890 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0]
1891 ; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8]
19191892 ; SSE-NEXT: retq
19201893 ;
1921 ; AVX1-LABEL: max_gt_v16i16c:
1922 ; AVX1: # BB#0:
1923 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
1924 ; AVX1-NEXT: vpmaxsw {{.*}}(%rip), %xmm0, %xmm0
1925 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
1926 ; AVX1-NEXT: vpmaxsw {{.*}}(%rip), %xmm1, %xmm1
1927 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
1928 ; AVX1-NEXT: retq
1929 ;
1930 ; AVX2-LABEL: max_gt_v16i16c:
1931 ; AVX2: # BB#0:
1932 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
1933 ; AVX2-NEXT: vpmaxsw {{.*}}(%rip), %ymm0, %ymm0
1934 ; AVX2-NEXT: retq
1935 ;
1936 ; AVX512-LABEL: max_gt_v16i16c:
1937 ; AVX512: # BB#0:
1938 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
1939 ; AVX512-NEXT: vpmaxsw {{.*}}(%rip), %ymm0, %ymm0
1940 ; AVX512-NEXT: retq
1894 ; AVX-LABEL: max_gt_v16i16c:
1895 ; AVX: # BB#0:
1896 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65535,65534,65533,65532,65533,65534,65535,0,7,6,5,4,5,6,7,8]
1897 ; AVX-NEXT: retq
19411898 %1 = insertelement <16 x i16> , i16 -7, i32 0
19421899 %2 = insertelement <16 x i16> , i16 -1, i32 0
19431900 %3 = icmp sgt <16 x i16> %1, %2
19591916 ;
19601917 ; SSE41-LABEL: max_gt_v16i8c:
19611918 ; SSE41: # BB#0:
1962 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
1963 ; SSE41-NEXT: pmaxsb {{.*}}(%rip), %xmm0
1919 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
19641920 ; SSE41-NEXT: retq
19651921 ;
19661922 ; SSE42-LABEL: max_gt_v16i8c:
19671923 ; SSE42: # BB#0:
1968 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
1969 ; SSE42-NEXT: pmaxsb {{.*}}(%rip), %xmm0
1924 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
19701925 ; SSE42-NEXT: retq
19711926 ;
19721927 ; AVX-LABEL: max_gt_v16i8c:
19731928 ; AVX: # BB#0:
1974 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
1975 ; AVX-NEXT: vpmaxsb {{.*}}(%rip), %xmm0, %xmm0
1929 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
19761930 ; AVX-NEXT: retq
19771931 %1 = insertelement <16 x i8> , i8 -7, i32 0
19781932 %2 = insertelement <16 x i8> , i8 -1, i32 0
22122166 ;
22132167 ; SSE41-LABEL: max_ge_v4i32c:
22142168 ; SSE41: # BB#0:
2215 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
2216 ; SSE41-NEXT: pmaxsd {{.*}}(%rip), %xmm0
2169 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
22172170 ; SSE41-NEXT: retq
22182171 ;
22192172 ; SSE42-LABEL: max_ge_v4i32c:
22202173 ; SSE42: # BB#0:
2221 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
2222 ; SSE42-NEXT: pmaxsd {{.*}}(%rip), %xmm0
2174 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
22232175 ; SSE42-NEXT: retq
22242176 ;
22252177 ; AVX-LABEL: max_ge_v4i32c:
22262178 ; AVX: # BB#0:
2227 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
2228 ; AVX-NEXT: vpmaxsd {{.*}}(%rip), %xmm0, %xmm0
2179 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
22292180 ; AVX-NEXT: retq
22302181 %1 = insertelement <4 x i32> , i32 -7, i32 0
22312182 %2 = insertelement <4 x i32> , i32 -1, i32 0
22592210 ;
22602211 ; SSE41-LABEL: max_ge_v8i32c:
22612212 ; SSE41: # BB#0:
2262 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
2263 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
2264 ; SSE41-NEXT: pmaxsd {{.*}}(%rip), %xmm0
2265 ; SSE41-NEXT: pmaxsd {{.*}}(%rip), %xmm1
2213 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
2214 ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
22662215 ; SSE41-NEXT: retq
22672216 ;
22682217 ; SSE42-LABEL: max_ge_v8i32c:
22692218 ; SSE42: # BB#0:
2270 ; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
2271 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
2272 ; SSE42-NEXT: pmaxsd {{.*}}(%rip), %xmm0
2273 ; SSE42-NEXT: pmaxsd {{.*}}(%rip), %xmm1
2274 ; SSE42-NEXT: retq
2275 ;
2276 ; AVX1-LABEL: max_ge_v8i32c:
2277 ; AVX1: # BB#0:
2278 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
2279 ; AVX1-NEXT: vpmaxsd {{.*}}(%rip), %xmm0, %xmm0
2280 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,3,5,7]
2281 ; AVX1-NEXT: vpmaxsd {{.*}}(%rip), %xmm1, %xmm1
2282 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
2283 ; AVX1-NEXT: retq
2284 ;
2285 ; AVX2-LABEL: max_ge_v8i32c:
2286 ; AVX2: # BB#0:
2287 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
2288 ; AVX2-NEXT: vpmaxsd {{.*}}(%rip), %ymm0, %ymm0
2289 ; AVX2-NEXT: retq
2290 ;
2291 ; AVX512-LABEL: max_ge_v8i32c:
2292 ; AVX512: # BB#0:
2293 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
2294 ; AVX512-NEXT: vpmaxsd {{.*}}(%rip), %ymm0, %ymm0
2295 ; AVX512-NEXT: retq
2219 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
2220 ; SSE42-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
2221 ; SSE42-NEXT: retq
2222 ;
2223 ; AVX-LABEL: max_ge_v8i32c:
2224 ; AVX: # BB#0:
2225 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
2226 ; AVX-NEXT: retq
22962227 %1 = insertelement <8 x i32> , i32 -7, i32 0
22972228 %2 = insertelement <8 x i32> , i32 -1, i32 0
22982229 %3 = icmp sge <8 x i32> %1, %2
23032234 define <8 x i16> @max_ge_v8i16c() {
23042235 ; SSE-LABEL: max_ge_v8i16c:
23052236 ; SSE: # BB#0:
2306 ; SSE-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
2307 ; SSE-NEXT: pmaxsw {{.*}}(%rip), %xmm0
2237 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
23082238 ; SSE-NEXT: retq
23092239 ;
23102240 ; AVX-LABEL: max_ge_v8i16c:
23112241 ; AVX: # BB#0:
2312 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
2313 ; AVX-NEXT: vpmaxsw {{.*}}(%rip), %xmm0, %xmm0
2242 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
23142243 ; AVX-NEXT: retq
23152244 %1 = insertelement <8 x i16> , i16 -7, i32 0
23162245 %2 = insertelement <8 x i16> , i16 -1, i32 0
23222251 define <16 x i16> @max_ge_v16i16c() {
23232252 ; SSE-LABEL: max_ge_v16i16c:
23242253 ; SSE: # BB#0:
2325 ; SSE-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
2326 ; SSE-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
2327 ; SSE-NEXT: pmaxsw {{.*}}(%rip), %xmm0
2328 ; SSE-NEXT: pmaxsw {{.*}}(%rip), %xmm1
2254 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0]
2255 ; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8]
23292256 ; SSE-NEXT: retq
23302257 ;
2331 ; AVX1-LABEL: max_ge_v16i16c:
2332 ; AVX1: # BB#0:
2333 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
2334 ; AVX1-NEXT: vpmaxsw {{.*}}(%rip), %xmm0, %xmm0
2335 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
2336 ; AVX1-NEXT: vpmaxsw {{.*}}(%rip), %xmm1, %xmm1
2337 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
2338 ; AVX1-NEXT: retq
2339 ;
2340 ; AVX2-LABEL: max_ge_v16i16c:
2341 ; AVX2: # BB#0:
2342 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
2343 ; AVX2-NEXT: vpmaxsw {{.*}}(%rip), %ymm0, %ymm0
2344 ; AVX2-NEXT: retq
2345 ;
2346 ; AVX512-LABEL: max_ge_v16i16c:
2347 ; AVX512: # BB#0:
2348 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
2349 ; AVX512-NEXT: vpmaxsw {{.*}}(%rip), %ymm0, %ymm0
2350 ; AVX512-NEXT: retq
2258 ; AVX-LABEL: max_ge_v16i16c:
2259 ; AVX: # BB#0:
2260 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65535,65534,65533,65532,65533,65534,65535,0,7,6,5,4,5,6,7,8]
2261 ; AVX-NEXT: retq
23512262 %1 = insertelement <16 x i16> , i16 -7, i32 0
23522263 %2 = insertelement <16 x i16> , i16 -1, i32 0
23532264 %3 = icmp sge <16 x i16> %1, %2
23712282 ;
23722283 ; SSE41-LABEL: max_ge_v16i8c:
23732284 ; SSE41: # BB#0:
2374 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
2375 ; SSE41-NEXT: pmaxsb {{.*}}(%rip), %xmm0
2285 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
23762286 ; SSE41-NEXT: retq
23772287 ;
23782288 ; SSE42-LABEL: max_ge_v16i8c:
23792289 ; SSE42: # BB#0:
2380 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
2381 ; SSE42-NEXT: pmaxsb {{.*}}(%rip), %xmm0
2290 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
23822291 ; SSE42-NEXT: retq
23832292 ;
23842293 ; AVX-LABEL: max_ge_v16i8c:
23852294 ; AVX: # BB#0:
2386 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
2387 ; AVX-NEXT: vpmaxsb {{.*}}(%rip), %xmm0, %xmm0
2295 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
23882296 ; AVX-NEXT: retq
23892297 %1 = insertelement <16 x i8> , i8 -7, i32 0
23902298 %2 = insertelement <16 x i8> , i8 -1, i32 0
26002508 ;
26012509 ; SSE41-LABEL: min_lt_v4i32c:
26022510 ; SSE41: # BB#0:
2603 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
2604 ; SSE41-NEXT: pminsd {{.*}}(%rip), %xmm0
2511 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
26052512 ; SSE41-NEXT: retq
26062513 ;
26072514 ; SSE42-LABEL: min_lt_v4i32c:
26082515 ; SSE42: # BB#0:
2609 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
2610 ; SSE42-NEXT: pminsd {{.*}}(%rip), %xmm0
2516 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
26112517 ; SSE42-NEXT: retq
26122518 ;
26132519 ; AVX-LABEL: min_lt_v4i32c:
26142520 ; AVX: # BB#0:
2615 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
2616 ; AVX-NEXT: vpminsd {{.*}}(%rip), %xmm0, %xmm0
2521 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
26172522 ; AVX-NEXT: retq
26182523 %1 = insertelement <4 x i32> , i32 -7, i32 0
26192524 %2 = insertelement <4 x i32> , i32 -1, i32 0
26432548 ;
26442549 ; SSE41-LABEL: min_lt_v8i32c:
26452550 ; SSE41: # BB#0:
2646 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
2647 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
2648 ; SSE41-NEXT: pminsd {{.*}}(%rip), %xmm0
2649 ; SSE41-NEXT: pminsd {{.*}}(%rip), %xmm1
2551 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
2552 ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
26502553 ; SSE41-NEXT: retq
26512554 ;
26522555 ; SSE42-LABEL: min_lt_v8i32c:
26532556 ; SSE42: # BB#0:
2654 ; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
2655 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
2656 ; SSE42-NEXT: pminsd {{.*}}(%rip), %xmm0
2657 ; SSE42-NEXT: pminsd {{.*}}(%rip), %xmm1
2658 ; SSE42-NEXT: retq
2659 ;
2660 ; AVX1-LABEL: min_lt_v8i32c:
2661 ; AVX1: # BB#0:
2662 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
2663 ; AVX1-NEXT: vpminsd {{.*}}(%rip), %xmm0, %xmm0
2664 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,3,5,7]
2665 ; AVX1-NEXT: vpminsd {{.*}}(%rip), %xmm1, %xmm1
2666 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
2667 ; AVX1-NEXT: retq
2668 ;
2669 ; AVX2-LABEL: min_lt_v8i32c:
2670 ; AVX2: # BB#0:
2671 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
2672 ; AVX2-NEXT: vpminsd {{.*}}(%rip), %ymm0, %ymm0
2673 ; AVX2-NEXT: retq
2674 ;
2675 ; AVX512-LABEL: min_lt_v8i32c:
2676 ; AVX512: # BB#0:
2677 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
2678 ; AVX512-NEXT: vpminsd {{.*}}(%rip), %ymm0, %ymm0
2679 ; AVX512-NEXT: retq
2557 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
2558 ; SSE42-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
2559 ; SSE42-NEXT: retq
2560 ;
2561 ; AVX-LABEL: min_lt_v8i32c:
2562 ; AVX: # BB#0:
2563 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
2564 ; AVX-NEXT: retq
26802565 %1 = insertelement <8 x i32> , i32 -7, i32 0
26812566 %2 = insertelement <8 x i32> , i32 -1, i32 0
26822567 %3 = icmp slt <8 x i32> %1, %2
26872572 define <8 x i16> @min_lt_v8i16c() {
26882573 ; SSE-LABEL: min_lt_v8i16c:
26892574 ; SSE: # BB#0:
2690 ; SSE-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
2691 ; SSE-NEXT: pminsw {{.*}}(%rip), %xmm0
2575 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
26922576 ; SSE-NEXT: retq
26932577 ;
26942578 ; AVX-LABEL: min_lt_v8i16c:
26952579 ; AVX: # BB#0:
2696 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
2697 ; AVX-NEXT: vpminsw {{.*}}(%rip), %xmm0, %xmm0
2580 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
26982581 ; AVX-NEXT: retq
26992582 %1 = insertelement <8 x i16> , i16 -7, i32 0
27002583 %2 = insertelement <8 x i16> , i16 -1, i32 0
27062589 define <16 x i16> @min_lt_v16i16c() {
27072590 ; SSE-LABEL: min_lt_v16i16c:
27082591 ; SSE: # BB#0:
2709 ; SSE-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
2710 ; SSE-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
2711 ; SSE-NEXT: pminsw {{.*}}(%rip), %xmm0
2712 ; SSE-NEXT: pminsw {{.*}}(%rip), %xmm1
2592 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65529,65530,65531,65532,65531,65530,65529,0]
2593 ; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0]
27132594 ; SSE-NEXT: retq
27142595 ;
2715 ; AVX1-LABEL: min_lt_v16i16c:
2716 ; AVX1: # BB#0:
2717 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
2718 ; AVX1-NEXT: vpminsw {{.*}}(%rip), %xmm0, %xmm0
2719 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
2720 ; AVX1-NEXT: vpminsw {{.*}}(%rip), %xmm1, %xmm1
2721 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
2722 ; AVX1-NEXT: retq
2723 ;
2724 ; AVX2-LABEL: min_lt_v16i16c:
2725 ; AVX2: # BB#0:
2726 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
2727 ; AVX2-NEXT: vpminsw {{.*}}(%rip), %ymm0, %ymm0
2728 ; AVX2-NEXT: retq
2729 ;
2730 ; AVX512-LABEL: min_lt_v16i16c:
2731 ; AVX512: # BB#0:
2732 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
2733 ; AVX512-NEXT: vpminsw {{.*}}(%rip), %ymm0, %ymm0
2734 ; AVX512-NEXT: retq
2596 ; AVX-LABEL: min_lt_v16i16c:
2597 ; AVX: # BB#0:
2598 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65529,65530,65531,65532,65531,65530,65529,0,1,2,3,4,3,2,1,0]
2599 ; AVX-NEXT: retq
27352600 %1 = insertelement <16 x i16> , i16 -7, i32 0
27362601 %2 = insertelement <16 x i16> , i16 -1, i32 0
27372602 %3 = icmp slt <16 x i16> %1, %2
27532618 ;
27542619 ; SSE41-LABEL: min_lt_v16i8c:
27552620 ; SSE41: # BB#0:
2756 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
2757 ; SSE41-NEXT: pminsb {{.*}}(%rip), %xmm0
2621 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
27582622 ; SSE41-NEXT: retq
27592623 ;
27602624 ; SSE42-LABEL: min_lt_v16i8c:
27612625 ; SSE42: # BB#0:
2762 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
2763 ; SSE42-NEXT: pminsb {{.*}}(%rip), %xmm0
2626 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
27642627 ; SSE42-NEXT: retq
27652628 ;
27662629 ; AVX-LABEL: min_lt_v16i8c:
27672630 ; AVX: # BB#0:
2768 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
2769 ; AVX-NEXT: vpminsb {{.*}}(%rip), %xmm0, %xmm0
2631 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
27702632 ; AVX-NEXT: retq
27712633 %1 = insertelement <16 x i8> , i8 -7, i32 0
27722634 %2 = insertelement <16 x i8> , i8 -1, i32 0
30062868 ;
30072869 ; SSE41-LABEL: min_le_v4i32c:
30082870 ; SSE41: # BB#0:
3009 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
3010 ; SSE41-NEXT: pminsd {{.*}}(%rip), %xmm0
2871 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
30112872 ; SSE41-NEXT: retq
30122873 ;
30132874 ; SSE42-LABEL: min_le_v4i32c:
30142875 ; SSE42: # BB#0:
3015 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
3016 ; SSE42-NEXT: pminsd {{.*}}(%rip), %xmm0
2876 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
30172877 ; SSE42-NEXT: retq
30182878 ;
30192879 ; AVX-LABEL: min_le_v4i32c:
30202880 ; AVX: # BB#0:
3021 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
3022 ; AVX-NEXT: vpminsd {{.*}}(%rip), %xmm0, %xmm0
2881 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
30232882 ; AVX-NEXT: retq
30242883 %1 = insertelement <4 x i32> , i32 -7, i32 0
30252884 %2 = insertelement <4 x i32> , i32 -1, i32 0
30532912 ;
30542913 ; SSE41-LABEL: min_le_v8i32c:
30552914 ; SSE41: # BB#0:
3056 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
3057 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
3058 ; SSE41-NEXT: pminsd {{.*}}(%rip), %xmm0
3059 ; SSE41-NEXT: pminsd {{.*}}(%rip), %xmm1
2915 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
2916 ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
30602917 ; SSE41-NEXT: retq
30612918 ;
30622919 ; SSE42-LABEL: min_le_v8i32c:
30632920 ; SSE42: # BB#0:
3064 ; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
3065 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
3066 ; SSE42-NEXT: pminsd {{.*}}(%rip), %xmm0
3067 ; SSE42-NEXT: pminsd {{.*}}(%rip), %xmm1
3068 ; SSE42-NEXT: retq
3069 ;
3070 ; AVX1-LABEL: min_le_v8i32c:
3071 ; AVX1: # BB#0:
3072 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
3073 ; AVX1-NEXT: vpminsd {{.*}}(%rip), %xmm0, %xmm0
3074 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,3,5,7]
3075 ; AVX1-NEXT: vpminsd {{.*}}(%rip), %xmm1, %xmm1
3076 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
3077 ; AVX1-NEXT: retq
3078 ;
3079 ; AVX2-LABEL: min_le_v8i32c:
3080 ; AVX2: # BB#0:
3081 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
3082 ; AVX2-NEXT: vpminsd {{.*}}(%rip), %ymm0, %ymm0
3083 ; AVX2-NEXT: retq
3084 ;
3085 ; AVX512-LABEL: min_le_v8i32c:
3086 ; AVX512: # BB#0:
3087 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
3088 ; AVX512-NEXT: vpminsd {{.*}}(%rip), %ymm0, %ymm0
3089 ; AVX512-NEXT: retq
2921 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
2922 ; SSE42-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
2923 ; SSE42-NEXT: retq
2924 ;
2925 ; AVX-LABEL: min_le_v8i32c:
2926 ; AVX: # BB#0:
2927 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
2928 ; AVX-NEXT: retq
30902929 %1 = insertelement <8 x i32> , i32 -7, i32 0
30912930 %2 = insertelement <8 x i32> , i32 -1, i32 0
30922931 %3 = icmp sle <8 x i32> %1, %2
30972936 define <8 x i16> @min_le_v8i16c() {
30982937 ; SSE-LABEL: min_le_v8i16c:
30992938 ; SSE: # BB#0:
3100 ; SSE-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
3101 ; SSE-NEXT: pminsw {{.*}}(%rip), %xmm0
2939 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
31022940 ; SSE-NEXT: retq
31032941 ;
31042942 ; AVX-LABEL: min_le_v8i16c:
31052943 ; AVX: # BB#0:
3106 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
3107 ; AVX-NEXT: vpminsw {{.*}}(%rip), %xmm0, %xmm0
2944 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
31082945 ; AVX-NEXT: retq
31092946 %1 = insertelement <8 x i16> , i16 -7, i32 0
31102947 %2 = insertelement <8 x i16> , i16 -1, i32 0
31162953 define <16 x i16> @min_le_v16i16c() {
31172954 ; SSE-LABEL: min_le_v16i16c:
31182955 ; SSE: # BB#0:
3119 ; SSE-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
3120 ; SSE-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
3121 ; SSE-NEXT: pminsw {{.*}}(%rip), %xmm0
3122 ; SSE-NEXT: pminsw {{.*}}(%rip), %xmm1
2956 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65529,65530,65531,65532,65531,65530,65529,0]
2957 ; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0]
31232958 ; SSE-NEXT: retq
31242959 ;
3125 ; AVX1-LABEL: min_le_v16i16c:
3126 ; AVX1: # BB#0:
3127 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
3128 ; AVX1-NEXT: vpminsw {{.*}}(%rip), %xmm0, %xmm0
3129 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
3130 ; AVX1-NEXT: vpminsw {{.*}}(%rip), %xmm1, %xmm1
3131 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
3132 ; AVX1-NEXT: retq
3133 ;
3134 ; AVX2-LABEL: min_le_v16i16c:
3135 ; AVX2: # BB#0:
3136 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
3137 ; AVX2-NEXT: vpminsw {{.*}}(%rip), %ymm0, %ymm0
3138 ; AVX2-NEXT: retq
3139 ;
3140 ; AVX512-LABEL: min_le_v16i16c:
3141 ; AVX512: # BB#0:
3142 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
3143 ; AVX512-NEXT: vpminsw {{.*}}(%rip), %ymm0, %ymm0
3144 ; AVX512-NEXT: retq
2960 ; AVX-LABEL: min_le_v16i16c:
2961 ; AVX: # BB#0:
2962 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65529,65530,65531,65532,65531,65530,65529,0,1,2,3,4,3,2,1,0]
2963 ; AVX-NEXT: retq
31452964 %1 = insertelement <16 x i16> , i16 -7, i32 0
31462965 %2 = insertelement <16 x i16> , i16 -1, i32 0
31472966 %3 = icmp sle <16 x i16> %1, %2
31652984 ;
31662985 ; SSE41-LABEL: min_le_v16i8c:
31672986 ; SSE41: # BB#0:
3168 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
3169 ; SSE41-NEXT: pminsb {{.*}}(%rip), %xmm0
2987 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
31702988 ; SSE41-NEXT: retq
31712989 ;
31722990 ; SSE42-LABEL: min_le_v16i8c:
31732991 ; SSE42: # BB#0:
3174 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
3175 ; SSE42-NEXT: pminsb {{.*}}(%rip), %xmm0
2992 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
31762993 ; SSE42-NEXT: retq
31772994 ;
31782995 ; AVX-LABEL: min_le_v16i8c:
31792996 ; AVX: # BB#0:
3180 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
3181 ; AVX-NEXT: vpminsb {{.*}}(%rip), %xmm0, %xmm0
2997 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
31822998 ; AVX-NEXT: retq
31832999 %1 = insertelement <16 x i8> , i8 -7, i32 0
31843000 %2 = insertelement <16 x i8> , i8 -1, i32 0
19411941 ;
19421942 ; SSE41-LABEL: max_gt_v4i32c:
19431943 ; SSE41: # BB#0:
1944 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
1945 ; SSE41-NEXT: pmaxud {{.*}}(%rip), %xmm0
1944 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
19461945 ; SSE41-NEXT: retq
19471946 ;
19481947 ; SSE42-LABEL: max_gt_v4i32c:
19491948 ; SSE42: # BB#0:
1950 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
1951 ; SSE42-NEXT: pmaxud {{.*}}(%rip), %xmm0
1949 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
19521950 ; SSE42-NEXT: retq
19531951 ;
19541952 ; AVX-LABEL: max_gt_v4i32c:
19551953 ; AVX: # BB#0:
1956 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
1957 ; AVX-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0
1954 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
19581955 ; AVX-NEXT: retq
19591956 %1 = insertelement <4 x i32> , i32 -7, i32 0
19601957 %2 = insertelement <4 x i32> , i32 -1, i32 0
19821979 ;
19831980 ; SSE41-LABEL: max_gt_v8i32c:
19841981 ; SSE41: # BB#0:
1985 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
1986 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
1987 ; SSE41-NEXT: pmaxud {{.*}}(%rip), %xmm0
1988 ; SSE41-NEXT: pmaxud {{.*}}(%rip), %xmm1
1982 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
1983 ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
19891984 ; SSE41-NEXT: retq
19901985 ;
19911986 ; SSE42-LABEL: max_gt_v8i32c:
19921987 ; SSE42: # BB#0:
1993 ; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
1994 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
1995 ; SSE42-NEXT: pmaxud {{.*}}(%rip), %xmm0
1996 ; SSE42-NEXT: pmaxud {{.*}}(%rip), %xmm1
1997 ; SSE42-NEXT: retq
1998 ;
1999 ; AVX1-LABEL: max_gt_v8i32c:
2000 ; AVX1: # BB#0:
2001 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
2002 ; AVX1-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0
2003 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,3,5,7]
2004 ; AVX1-NEXT: vpmaxud {{.*}}(%rip), %xmm1, %xmm1
2005 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
2006 ; AVX1-NEXT: retq
2007 ;
2008 ; AVX2-LABEL: max_gt_v8i32c:
2009 ; AVX2: # BB#0:
2010 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
2011 ; AVX2-NEXT: vpmaxud {{.*}}(%rip), %ymm0, %ymm0
2012 ; AVX2-NEXT: retq
2013 ;
2014 ; AVX512-LABEL: max_gt_v8i32c:
2015 ; AVX512: # BB#0:
2016 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
2017 ; AVX512-NEXT: vpmaxud {{.*}}(%rip), %ymm0, %ymm0
2018 ; AVX512-NEXT: retq
1988 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
1989 ; SSE42-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
1990 ; SSE42-NEXT: retq
1991 ;
1992 ; AVX-LABEL: max_gt_v8i32c:
1993 ; AVX: # BB#0:
1994 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
1995 ; AVX-NEXT: retq
20191996 %1 = insertelement <8 x i32> , i32 -7, i32 0
20201997 %2 = insertelement <8 x i32> , i32 -1, i32 0
20211998 %3 = icmp ugt <8 x i32> %1, %2
20362013 ;
20372014 ; SSE41-LABEL: max_gt_v8i16c:
20382015 ; SSE41: # BB#0:
2039 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
2040 ; SSE41-NEXT: pmaxuw {{.*}}(%rip), %xmm0
2016 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
20412017 ; SSE41-NEXT: retq
20422018 ;
20432019 ; SSE42-LABEL: max_gt_v8i16c:
20442020 ; SSE42: # BB#0:
2045 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
2046 ; SSE42-NEXT: pmaxuw {{.*}}(%rip), %xmm0
2021 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
20472022 ; SSE42-NEXT: retq
20482023 ;
20492024 ; AVX-LABEL: max_gt_v8i16c:
20502025 ; AVX: # BB#0:
2051 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
2052 ; AVX-NEXT: vpmaxuw {{.*}}(%rip), %xmm0, %xmm0
2026 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
20532027 ; AVX-NEXT: retq
20542028 %1 = insertelement <8 x i16> , i16 -7, i32 0
20552029 %2 = insertelement <8 x i16> , i16 -1, i32 0
20772051 ;
20782052 ; SSE41-LABEL: max_gt_v16i16c:
20792053 ; SSE41: # BB#0:
2080 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
2081 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
2082 ; SSE41-NEXT: pmaxuw {{.*}}(%rip), %xmm0
2083 ; SSE41-NEXT: pmaxuw {{.*}}(%rip), %xmm1
2054 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0]
2055 ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8]
20842056 ; SSE41-NEXT: retq
20852057 ;
20862058 ; SSE42-LABEL: max_gt_v16i16c:
20872059 ; SSE42: # BB#0:
2088 ; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
2089 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
2090 ; SSE42-NEXT: pmaxuw {{.*}}(%rip), %xmm0
2091 ; SSE42-NEXT: pmaxuw {{.*}}(%rip), %xmm1
2092 ; SSE42-NEXT: retq
2093 ;
2094 ; AVX1-LABEL: max_gt_v16i16c:
2095 ; AVX1: # BB#0:
2096 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
2097 ; AVX1-NEXT: vpmaxuw {{.*}}(%rip), %xmm0, %xmm0
2098 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
2099 ; AVX1-NEXT: vpmaxuw {{.*}}(%rip), %xmm1, %xmm1
2100 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
2101 ; AVX1-NEXT: retq
2102 ;
2103 ; AVX2-LABEL: max_gt_v16i16c:
2104 ; AVX2: # BB#0:
2105 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
2106 ; AVX2-NEXT: vpmaxuw {{.*}}(%rip), %ymm0, %ymm0
2107 ; AVX2-NEXT: retq
2108 ;
2109 ; AVX512-LABEL: max_gt_v16i16c:
2110 ; AVX512: # BB#0:
2111 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
2112 ; AVX512-NEXT: vpmaxuw {{.*}}(%rip), %ymm0, %ymm0
2113 ; AVX512-NEXT: retq
2060 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0]
2061 ; SSE42-NEXT: movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8]
2062 ; SSE42-NEXT: retq
2063 ;
2064 ; AVX-LABEL: max_gt_v16i16c:
2065 ; AVX: # BB#0:
2066 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65535,65534,65533,65532,65533,65534,65535,0,7,6,5,4,5,6,7,8]
2067 ; AVX-NEXT: retq
21142068 %1 = insertelement <16 x i16> , i16 -7, i32 0
21152069 %2 = insertelement <16 x i16> , i16 -1, i32 0
21162070 %3 = icmp ugt <16 x i16> %1, %2
21212075 define <16 x i8> @max_gt_v16i8c() {
21222076 ; SSE-LABEL: max_gt_v16i8c:
21232077 ; SSE: # BB#0:
2124 ; SSE-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
2125 ; SSE-NEXT: pmaxub {{.*}}(%rip), %xmm0
2078 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
21262079 ; SSE-NEXT: retq
21272080 ;
21282081 ; AVX-LABEL: max_gt_v16i8c:
21292082 ; AVX: # BB#0:
2130 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
2131 ; AVX-NEXT: vpmaxub {{.*}}(%rip), %xmm0, %xmm0
2083 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
21322084 ; AVX-NEXT: retq
21332085 %1 = insertelement <16 x i8> , i8 -7, i32 0
21342086 %2 = insertelement <16 x i8> , i8 -1, i32 0
23632315 ;
23642316 ; SSE41-LABEL: max_ge_v4i32c:
23652317 ; SSE41: # BB#0:
2366 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
2367 ; SSE41-NEXT: pmaxud {{.*}}(%rip), %xmm0
2318 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
23682319 ; SSE41-NEXT: retq
23692320 ;
23702321 ; SSE42-LABEL: max_ge_v4i32c:
23712322 ; SSE42: # BB#0:
2372 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
2373 ; SSE42-NEXT: pmaxud {{.*}}(%rip), %xmm0
2323 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
23742324 ; SSE42-NEXT: retq
23752325 ;
23762326 ; AVX-LABEL: max_ge_v4i32c:
23772327 ; AVX: # BB#0:
2378 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
2379 ; AVX-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0
2328 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
23802329 ; AVX-NEXT: retq
23812330 %1 = insertelement <4 x i32> , i32 -7, i32 0
23822331 %2 = insertelement <4 x i32> , i32 -1, i32 0
24062355 ;
24072356 ; SSE41-LABEL: max_ge_v8i32c:
24082357 ; SSE41: # BB#0:
2409 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
2410 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
2411 ; SSE41-NEXT: pmaxud {{.*}}(%rip), %xmm0
2412 ; SSE41-NEXT: pmaxud {{.*}}(%rip), %xmm1
2358 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
2359 ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
24132360 ; SSE41-NEXT: retq
24142361 ;
24152362 ; SSE42-LABEL: max_ge_v8i32c:
24162363 ; SSE42: # BB#0:
2417 ; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
2418 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
2419 ; SSE42-NEXT: pmaxud {{.*}}(%rip), %xmm0
2420 ; SSE42-NEXT: pmaxud {{.*}}(%rip), %xmm1
2421 ; SSE42-NEXT: retq
2422 ;
2423 ; AVX1-LABEL: max_ge_v8i32c:
2424 ; AVX1: # BB#0:
2425 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
2426 ; AVX1-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0
2427 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,3,5,7]
2428 ; AVX1-NEXT: vpmaxud {{.*}}(%rip), %xmm1, %xmm1
2429 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
2430 ; AVX1-NEXT: retq
2431 ;
2432 ; AVX2-LABEL: max_ge_v8i32c:
2433 ; AVX2: # BB#0:
2434 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
2435 ; AVX2-NEXT: vpmaxud {{.*}}(%rip), %ymm0, %ymm0
2436 ; AVX2-NEXT: retq
2437 ;
2438 ; AVX512-LABEL: max_ge_v8i32c:
2439 ; AVX512: # BB#0:
2440 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
2441 ; AVX512-NEXT: vpmaxud {{.*}}(%rip), %ymm0, %ymm0
2442 ; AVX512-NEXT: retq
2364 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
2365 ; SSE42-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
2366 ; SSE42-NEXT: retq
2367 ;
2368 ; AVX-LABEL: max_ge_v8i32c:
2369 ; AVX: # BB#0:
2370 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
2371 ; AVX-NEXT: retq
24432372 %1 = insertelement <8 x i32> , i32 -7, i32 0
24442373 %2 = insertelement <8 x i32> , i32 -1, i32 0
24452374 %3 = icmp uge <8 x i32> %1, %2
24632392 ;
24642393 ; SSE41-LABEL: max_ge_v8i16c:
24652394 ; SSE41: # BB#0:
2466 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
2467 ; SSE41-NEXT: pmaxuw {{.*}}(%rip), %xmm0
2395 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
24682396 ; SSE41-NEXT: retq
24692397 ;
24702398 ; SSE42-LABEL: max_ge_v8i16c:
24712399 ; SSE42: # BB#0:
2472 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
2473 ; SSE42-NEXT: pmaxuw {{.*}}(%rip), %xmm0
2400 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
24742401 ; SSE42-NEXT: retq
24752402 ;
24762403 ; AVX-LABEL: max_ge_v8i16c:
24772404 ; AVX: # BB#0:
2478 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
2479 ; AVX-NEXT: vpmaxuw {{.*}}(%rip), %xmm0, %xmm0
2405 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
24802406 ; AVX-NEXT: retq
24812407 %1 = insertelement <8 x i16> , i16 -7, i32 0
24822408 %2 = insertelement <8 x i16> , i16 -1, i32 0
25092435 ;
25102436 ; SSE41-LABEL: max_ge_v16i16c:
25112437 ; SSE41: # BB#0:
2512 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
2513 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
2514 ; SSE41-NEXT: pmaxuw {{.*}}(%rip), %xmm0
2515 ; SSE41-NEXT: pmaxuw {{.*}}(%rip), %xmm1
2438 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0]
2439 ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8]
25162440 ; SSE41-NEXT: retq
25172441 ;
25182442 ; SSE42-LABEL: max_ge_v16i16c:
25192443 ; SSE42: # BB#0:
2520 ; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
2521 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
2522 ; SSE42-NEXT: pmaxuw {{.*}}(%rip), %xmm0
2523 ; SSE42-NEXT: pmaxuw {{.*}}(%rip), %xmm1
2524 ; SSE42-NEXT: retq
2525 ;
2526 ; AVX1-LABEL: max_ge_v16i16c:
2527 ; AVX1: # BB#0:
2528 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
2529 ; AVX1-NEXT: vpmaxuw {{.*}}(%rip), %xmm0, %xmm0
2530 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
2531 ; AVX1-NEXT: vpmaxuw {{.*}}(%rip), %xmm1, %xmm1
2532 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
2533 ; AVX1-NEXT: retq
2534 ;
2535 ; AVX2-LABEL: max_ge_v16i16c:
2536 ; AVX2: # BB#0:
2537 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
2538 ; AVX2-NEXT: vpmaxuw {{.*}}(%rip), %ymm0, %ymm0
2539 ; AVX2-NEXT: retq
2540 ;
2541 ; AVX512-LABEL: max_ge_v16i16c:
2542 ; AVX512: # BB#0:
2543 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
2544 ; AVX512-NEXT: vpmaxuw {{.*}}(%rip), %ymm0, %ymm0
2545 ; AVX512-NEXT: retq
2444 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0]
2445 ; SSE42-NEXT: movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8]
2446 ; SSE42-NEXT: retq
2447 ;
2448 ; AVX-LABEL: max_ge_v16i16c:
2449 ; AVX: # BB#0:
2450 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65535,65534,65533,65532,65533,65534,65535,0,7,6,5,4,5,6,7,8]
2451 ; AVX-NEXT: retq
25462452 %1 = insertelement <16 x i16> , i16 -7, i32 0
25472453 %2 = insertelement <16 x i16> , i16 -1, i32 0
25482454 %3 = icmp uge <16 x i16> %1, %2
25532459 define <16 x i8> @max_ge_v16i8c() {
25542460 ; SSE-LABEL: max_ge_v16i8c:
25552461 ; SSE: # BB#0:
2556 ; SSE-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
2557 ; SSE-NEXT: pmaxub {{.*}}(%rip), %xmm0
2462 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
25582463 ; SSE-NEXT: retq
25592464 ;
25602465 ; AVX-LABEL: max_ge_v16i8c:
25612466 ; AVX: # BB#0:
2562 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
2563 ; AVX-NEXT: vpmaxub {{.*}}(%rip), %xmm0, %xmm0
2467 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
25642468 ; AVX-NEXT: retq
25652469 %1 = insertelement <16 x i8> , i8 -7, i32 0
25662470 %2 = insertelement <16 x i8> , i8 -1, i32 0
27722676 ;
27732677 ; SSE41-LABEL: min_lt_v4i32c:
27742678 ; SSE41: # BB#0:
2775 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
2776 ; SSE41-NEXT: pminud {{.*}}(%rip), %xmm0
2679 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
27772680 ; SSE41-NEXT: retq
27782681 ;
27792682 ; SSE42-LABEL: min_lt_v4i32c:
27802683 ; SSE42: # BB#0:
2781 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
2782 ; SSE42-NEXT: pminud {{.*}}(%rip), %xmm0
2684 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
27832685 ; SSE42-NEXT: retq
27842686 ;
27852687 ; AVX-LABEL: min_lt_v4i32c:
27862688 ; AVX: # BB#0:
2787 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
2788 ; AVX-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
2689 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
27892690 ; AVX-NEXT: retq
27902691 %1 = insertelement <4 x i32> , i32 -7, i32 0
27912692 %2 = insertelement <4 x i32> , i32 -1, i32 0
28132714 ;
28142715 ; SSE41-LABEL: min_lt_v8i32c:
28152716 ; SSE41: # BB#0:
2816 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
2817 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
2818 ; SSE41-NEXT: pminud {{.*}}(%rip), %xmm0
2819 ; SSE41-NEXT: pminud {{.*}}(%rip), %xmm1
2717 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
2718 ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
28202719 ; SSE41-NEXT: retq
28212720 ;
28222721 ; SSE42-LABEL: min_lt_v8i32c:
28232722 ; SSE42: # BB#0:
2824 ; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
2825 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
2826 ; SSE42-NEXT: pminud {{.*}}(%rip), %xmm0
2827 ; SSE42-NEXT: pminud {{.*}}(%rip), %xmm1
2828 ; SSE42-NEXT: retq
2829 ;
2830 ; AVX1-LABEL: min_lt_v8i32c:
2831 ; AVX1: # BB#0:
2832 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
2833 ; AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
2834 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,3,5,7]
2835 ; AVX1-NEXT: vpminud {{.*}}(%rip), %xmm1, %xmm1
2836 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
2837 ; AVX1-NEXT: retq
2838 ;
2839 ; AVX2-LABEL: min_lt_v8i32c:
2840 ; AVX2: # BB#0:
2841 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
2842 ; AVX2-NEXT: vpminud {{.*}}(%rip), %ymm0, %ymm0
2843 ; AVX2-NEXT: retq
2844 ;
2845 ; AVX512-LABEL: min_lt_v8i32c:
2846 ; AVX512: # BB#0:
2847 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
2848 ; AVX512-NEXT: vpminud {{.*}}(%rip), %ymm0, %ymm0
2849 ; AVX512-NEXT: retq
2723 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
2724 ; SSE42-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
2725 ; SSE42-NEXT: retq
2726 ;
2727 ; AVX-LABEL: min_lt_v8i32c:
2728 ; AVX: # BB#0:
2729 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
2730 ; AVX-NEXT: retq
28502731 %1 = insertelement <8 x i32> , i32 -7, i32 0
28512732 %2 = insertelement <8 x i32> , i32 -1, i32 0
28522733 %3 = icmp ult <8 x i32> %1, %2
28692750 ;
28702751 ; SSE41-LABEL: min_lt_v8i16c:
28712752 ; SSE41: # BB#0:
2872 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
2873 ; SSE41-NEXT: pminuw {{.*}}(%rip), %xmm0
2753 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [1,65531,65531,65529,1,3,3,1]
28742754 ; SSE41-NEXT: retq
28752755 ;
28762756 ; SSE42-LABEL: min_lt_v8i16c:
28772757 ; SSE42: # BB#0:
2878 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
2879 ; SSE42-NEXT: pminuw {{.*}}(%rip), %xmm0
2758 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [1,65531,65531,65529,1,3,3,1]
28802759 ; SSE42-NEXT: retq
28812760 ;
28822761 ; AVX-LABEL: min_lt_v8i16c:
28832762 ; AVX: # BB#0:
2884 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
2885 ; AVX-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0
2763 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1,65531,65531,65529,1,3,3,1]
28862764 ; AVX-NEXT: retq
28872765 %1 = insertelement <8 x i16> , i16 -7, i32 0
28882766 %2 = insertelement <8 x i16> , i16 1, i32 0
29102788 ;
29112789 ; SSE41-LABEL: min_lt_v16i16c:
29122790 ; SSE41: # BB#0:
2913 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
2914 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
2915 ; SSE41-NEXT: pminuw {{.*}}(%rip), %xmm0
2916 ; SSE41-NEXT: pminuw {{.*}}(%rip), %xmm1
2791 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [1,65530,65531,65532,65531,65530,65529,0]
2792 ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0]
29172793 ; SSE41-NEXT: retq
29182794 ;
29192795 ; SSE42-LABEL: min_lt_v16i16c:
29202796 ; SSE42: # BB#0:
2921 ; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
2922 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
2923 ; SSE42-NEXT: pminuw {{.*}}(%rip), %xmm0
2924 ; SSE42-NEXT: pminuw {{.*}}(%rip), %xmm1
2925 ; SSE42-NEXT: retq
2926 ;
2927 ; AVX1-LABEL: min_lt_v16i16c:
2928 ; AVX1: # BB#0:
2929 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
2930 ; AVX1-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0
2931 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
2932 ; AVX1-NEXT: vpminuw {{.*}}(%rip), %xmm1, %xmm1
2933 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
2934 ; AVX1-NEXT: retq
2935 ;
2936 ; AVX2-LABEL: min_lt_v16i16c:
2937 ; AVX2: # BB#0:
2938 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
2939 ; AVX2-NEXT: vpminuw {{.*}}(%rip), %ymm0, %ymm0
2940 ; AVX2-NEXT: retq
2941 ;
2942 ; AVX512-LABEL: min_lt_v16i16c:
2943 ; AVX512: # BB#0:
2944 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
2945 ; AVX512-NEXT: vpminuw {{.*}}(%rip), %ymm0, %ymm0
2946 ; AVX512-NEXT: retq
2797 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [1,65530,65531,65532,65531,65530,65529,0]
2798 ; SSE42-NEXT: movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0]
2799 ; SSE42-NEXT: retq
2800 ;
2801 ; AVX-LABEL: min_lt_v16i16c:
2802 ; AVX: # BB#0:
2803 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [1,65530,65531,65532,65531,65530,65529,0,1,2,3,4,3,2,1,0]
2804 ; AVX-NEXT: retq
29472805 %1 = insertelement <16 x i16> , i16 -7, i32 0
29482806 %2 = insertelement <16 x i16> , i16 1, i32 0
29492807 %3 = icmp ult <16 x i16> %1, %2
29542812 define <16 x i8> @min_lt_v16i8c() {
29552813 ; SSE-LABEL: min_lt_v16i8c:
29562814 ; SSE: # BB#0:
2957 ; SSE-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
2958 ; SSE-NEXT: pminub {{.*}}(%rip), %xmm0
2815 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [1,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
29592816 ; SSE-NEXT: retq
29602817 ;
29612818 ; AVX-LABEL: min_lt_v16i8c:
29622819 ; AVX: # BB#0:
2963 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
2964 ; AVX-NEXT: vpminub {{.*}}(%rip), %xmm0, %xmm0
2820 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
29652821 ; AVX-NEXT: retq
29662822 %1 = insertelement <16 x i8> , i8 -7, i32 0
29672823 %2 = insertelement <16 x i8> , i8 1, i32 0
31963052 ;
31973053 ; SSE41-LABEL: min_le_v4i32c:
31983054 ; SSE41: # BB#0:
3199 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
3200 ; SSE41-NEXT: pminud {{.*}}(%rip), %xmm0
3055 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
32013056 ; SSE41-NEXT: retq
32023057 ;
32033058 ; SSE42-LABEL: min_le_v4i32c:
32043059 ; SSE42: # BB#0:
3205 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
3206 ; SSE42-NEXT: pminud {{.*}}(%rip), %xmm0
3060 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
32073061 ; SSE42-NEXT: retq
32083062 ;
32093063 ; AVX-LABEL: min_le_v4i32c:
32103064 ; AVX: # BB#0:
3211 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
3212 ; AVX-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
3065 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
32133066 ; AVX-NEXT: retq
32143067 %1 = insertelement <4 x i32> , i32 -7, i32 0
32153068 %2 = insertelement <4 x i32> , i32 -1, i32 0
32393092 ;
32403093 ; SSE41-LABEL: min_le_v8i32c:
32413094 ; SSE41: # BB#0:
3242 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
3243 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
3244 ; SSE41-NEXT: pminud {{.*}}(%rip), %xmm0
3245 ; SSE41-NEXT: pminud {{.*}}(%rip), %xmm1
3095 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
3096 ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
32463097 ; SSE41-NEXT: retq
32473098 ;
32483099 ; SSE42-LABEL: min_le_v8i32c:
32493100 ; SSE42: # BB#0:
3250 ; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
3251 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
3252 ; SSE42-NEXT: pminud {{.*}}(%rip), %xmm0
3253 ; SSE42-NEXT: pminud {{.*}}(%rip), %xmm1
3254 ; SSE42-NEXT: retq
3255 ;
3256 ; AVX1-LABEL: min_le_v8i32c:
3257 ; AVX1: # BB#0:
3258 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
3259 ; AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
3260 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,3,5,7]
3261 ; AVX1-NEXT: vpminud {{.*}}(%rip), %xmm1, %xmm1
3262 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
3263 ; AVX1-NEXT: retq
3264 ;
3265 ; AVX2-LABEL: min_le_v8i32c:
3266 ; AVX2: # BB#0:
3267 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
3268 ; AVX2-NEXT: vpminud {{.*}}(%rip), %ymm0, %ymm0
3269 ; AVX2-NEXT: retq
3270 ;
3271 ; AVX512-LABEL: min_le_v8i32c:
3272 ; AVX512: # BB#0:
3273 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
3274 ; AVX512-NEXT: vpminud {{.*}}(%rip), %ymm0, %ymm0
3275 ; AVX512-NEXT: retq
3101 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
3102 ; SSE42-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
3103 ; SSE42-NEXT: retq
3104 ;
3105 ; AVX-LABEL: min_le_v8i32c:
3106 ; AVX: # BB#0:
3107 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
3108 ; AVX-NEXT: retq
32763109 %1 = insertelement <8 x i32> , i32 -7, i32 0
32773110 %2 = insertelement <8 x i32> , i32 -1, i32 0
32783111 %3 = icmp ule <8 x i32> %1, %2
32963129 ;
32973130 ; SSE41-LABEL: min_le_v8i16c:
32983131 ; SSE41: # BB#0:
3299 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
3300 ; SSE41-NEXT: pminuw {{.*}}(%rip), %xmm0
3132 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
33013133 ; SSE41-NEXT: retq
33023134 ;
33033135 ; SSE42-LABEL: min_le_v8i16c:
33043136 ; SSE42: # BB#0:
3305 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
3306 ; SSE42-NEXT: pminuw {{.*}}(%rip), %xmm0
3137 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
33073138 ; SSE42-NEXT: retq
33083139 ;
33093140 ; AVX-LABEL: min_le_v8i16c:
33103141 ; AVX: # BB#0:
3311 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
3312 ; AVX-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0
3142 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
33133143 ; AVX-NEXT: retq
33143144 %1 = insertelement <8 x i16> , i16 -7, i32 0
33153145 %2 = insertelement <8 x i16> , i16 -1, i32 0
33423172 ;
33433173 ; SSE41-LABEL: min_le_v16i16c:
33443174 ; SSE41: # BB#0:
3345 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
3346 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
3347 ; SSE41-NEXT: pminuw {{.*}}(%rip), %xmm0
3348 ; SSE41-NEXT: pminuw {{.*}}(%rip), %xmm1
3175 ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [65529,65530,65531,65532,65531,65530,65529,0]
3176 ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0]
33493177 ; SSE41-NEXT: retq
33503178 ;
33513179 ; SSE42-LABEL: min_le_v16i16c:
33523180 ; SSE42: # BB#0:
3353 ; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
3354 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
3355 ; SSE42-NEXT: pminuw {{.*}}(%rip), %xmm0
3356 ; SSE42-NEXT: pminuw {{.*}}(%rip), %xmm1
3357 ; SSE42-NEXT: retq
3358 ;
3359 ; AVX1-LABEL: min_le_v16i16c:
3360 ; AVX1: # BB#0:
3361 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
3362 ; AVX1-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0
3363 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
3364 ; AVX1-NEXT: vpminuw {{.*}}(%rip), %xmm1, %xmm1
3365 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
3366 ; AVX1-NEXT: retq
3367 ;
3368 ; AVX2-LABEL: min_le_v16i16c:
3369 ; AVX2: # BB#0:
3370 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
3371 ; AVX2-NEXT: vpminuw {{.*}}(%rip), %ymm0, %ymm0
3372 ; AVX2-NEXT: retq
3373 ;
3374 ; AVX512-LABEL: min_le_v16i16c:
3375 ; AVX512: # BB#0:
3376 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
3377 ; AVX512-NEXT: vpminuw {{.*}}(%rip), %ymm0, %ymm0
3378 ; AVX512-NEXT: retq
3181 ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [65529,65530,65531,65532,65531,65530,65529,0]
3182 ; SSE42-NEXT: movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0]
3183 ; SSE42-NEXT: retq
3184 ;
3185 ; AVX-LABEL: min_le_v16i16c:
3186 ; AVX: # BB#0:
3187 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65529,65530,65531,65532,65531,65530,65529,0,1,2,3,4,3,2,1,0]
3188 ; AVX-NEXT: retq
33793189 %1 = insertelement <16 x i16> , i16 -7, i32 0
33803190 %2 = insertelement <16 x i16> , i16 -1, i32 0
33813191 %3 = icmp ule <16 x i16> %1, %2
33863196 define <16 x i8> @min_le_v16i8c() {
33873197 ; SSE-LABEL: min_le_v16i8c:
33883198 ; SSE: # BB#0:
3389 ; SSE-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
3390 ; SSE-NEXT: pminub {{.*}}(%rip), %xmm0
3199 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
33913200 ; SSE-NEXT: retq
33923201 ;
33933202 ; AVX-LABEL: min_le_v16i8c:
33943203 ; AVX: # BB#0:
3395 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
3396 ; AVX-NEXT: vpminub {{.*}}(%rip), %xmm0, %xmm0
3204 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
33973205 ; AVX-NEXT: retq
33983206 %1 = insertelement <16 x i8> , i8 -7, i32 0
33993207 %2 = insertelement <16 x i8> , i8 -1, i32 0