llvm.org GIT mirror llvm / 0877fdf
Fix a bug in DAGCombine for the optimization of BUILD_VECTOR. We cant generate a shuffle node from two vectors of different types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150383 91177308-0d34-0410-b5e6-96231b3b80d8 Nadav Rotem 8 years ago
2 changed file(s) with 22 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
73847384 // If VecIn2 is unused then change it to undef.
73857385 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
73867386
7387 // Check that we were able to transform all incoming values to the same type.
7388 if (VecIn2.getValueType() != VecIn1.getValueType() ||
7389 VecIn1.getValueType() != VT)
7390 return SDValue();
7391
73877392 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes.
7388 if (!isTypeLegal(VT) || !isTypeLegal(VecIn1.getValueType()) ||
7389 !isTypeLegal(VecIn2.getValueType()))
7393 if (!isTypeLegal(VT))
73907394 return SDValue();
73917395
73927396 // Return the new VECTOR_SHUFFLE node.
0 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx
1 target triple = "x86_64-unknown-linux-gnu"
2 ; Make sure we are not crashing on this one
3 define void @dagco_crash() {
4 entry:
5 %srcval.i411.i = load <4 x i64>* undef, align 1
6 %0 = extractelement <4 x i64> %srcval.i411.i, i32 3
7 %srcval.i409.i = load <2 x i64>* undef, align 1
8 %1 = extractelement <2 x i64> %srcval.i409.i, i32 0
9 %2 = insertelement <8 x i64> undef, i64 %0, i32 5
10 %3 = insertelement <8 x i64> %2, i64 %1, i32 6
11 %4 = insertelement <8 x i64> %3, i64 undef, i32 7
12 store <8 x i64> %4, <8 x i64> addrspace(1)* undef, align 64
13 unreachable
14 }
15