llvm.org GIT mirror llvm / 0862928
[ARM] Do not test for CPUs, use SubtargetFeatures. Also remove 1 flag This is a follow-up for r273544. The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods. This commit also removes a command line flag that isn't used in any of the tests: check-vmlx-hazards. It can be replaced easily with the mattr mechanism, since this is now a subtarget feature. There is still some work left regarding FeatureExpandMLx. In the past MLx expansion was enabled for subtargets with hasVFP2(), until r129775 [1] switched from that to isCortexA9, without too much justification. In spite of that, the code performing MLx expansion still contains calls to isSwift/isLikeA9, although the results of those are pretty clear given that we're only enabling it for the A9. We should try to enable it for all targets that have FeatureHasVMLxHazards, as it seems to be closely related to that behaviour, and if that is possible try to clean up the MLx expansion pass from all calls to isWhatever. This will require some performance testing, so it will be done in another patch. [1] http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20110418/119725.html Differential Revision: http://reviews.llvm.org/D21798 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274742 91177308-0d34-0410-b5e6-96231b3b80d8 Diana Picus 4 years ago
4 changed file(s) with 23 addition(s) and 12 deletion(s). Raw diff Collapse all Expand all
149149 "DontWidenVMOVS", "true",
150150 "Don't widen VMOVS to VMOVD">;
151151
152 // Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.
153 def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx", "ExpandMLx", "true",
154 "Expand VFP/NEON MLA/MLS instructions">;
155
156 // Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.
157 def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards",
158 "true", "Has VMLx hazards">;
159
152160 // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
153161 // VFP to NEON, as an execution domain optimization.
154162 def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", "UseNEONForFPMovs",
569577 FeatureHasRetAddrStack,
570578 FeatureTrustZone,
571579 FeatureSlowFPBrcc,
580 FeatureHasVMLxHazards,
572581 FeatureHasSlowFPVMLx,
573582 FeatureVMLxForwarding,
574583 FeatureT2XtPk,
583592 FeatureNonpipelinedVFP,
584593 FeatureTrustZone,
585594 FeatureSlowFPBrcc,
595 FeatureHasVMLxHazards,
586596 FeatureHasSlowFPVMLx,
587597 FeatureVMLxForwarding,
588598 FeatureT2XtPk]>;
590600 def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9,
591601 FeatureHasRetAddrStack,
592602 FeatureTrustZone,
603 FeatureHasVMLxHazards,
593604 FeatureVMLxForwarding,
594605 FeatureT2XtPk,
595606 FeatureFP16,
596607 FeatureAvoidPartialCPSR,
608 FeatureExpandMLx,
597609 FeaturePreferVMOVSR,
598610 FeatureMuxedUnits,
599611 FeatureNEONForFPMovs,
667679 FeatureAvoidPartialCPSR,
668680 FeatureAvoidMOVsShOp,
669681 FeatureHasSlowFPVMLx,
682 FeatureHasVMLxHazards,
670683 FeatureProfUnpredicate,
671684 FeaturePrefISHSTBarrier,
672685 FeatureSlowOddRegister,
4242 cl::desc("Disable isel of shifter-op"),
4343 cl::init(false));
4444
45 static cl::opt
46 CheckVMLxHazard("check-vmlx-hazard", cl::Hidden,
47 cl::desc("Check fp vmla / vmls hazard at isel time"),
48 cl::init(true));
49
5045 //===--------------------------------------------------------------------===//
5146 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
5247 /// instructions for SelectionDAG operations.
426421 if (OptLevel == CodeGenOpt::None)
427422 return true;
428423
429 if (!CheckVMLxHazard)
430 return true;
431
432 if (!Subtarget->isCortexA7() && !Subtarget->isCortexA8() &&
433 !Subtarget->isCortexA9() && !Subtarget->isSwift())
424 if (!Subtarget->hasVMLxHazards())
434425 return true;
435426
436427 if (!N->hasOneUse())
261261 /// If true, VMOVS will never be widened to VMOVD
262262 bool DontWidenVMOVS = false;
263263
264 /// If true, run the MLx expansion pass.
265 bool ExpandMLx = false;
266
267 /// If true, VFP/NEON VMLA/VMLS have special RAW hazards.
268 bool HasVMLxHazards = false;
269
264270 /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
265271 bool UseNEONForFPMovs = false;
266272
450456 bool hasSlowVDUP32() const { return HasSlowVDUP32; }
451457 bool preferVMOVSR() const { return PreferVMOVSR; }
452458 bool preferISHSTBarriers() const { return PreferISHST; }
459 bool expandMLx() const { return ExpandMLx; }
460 bool hasVMLxHazards() const { return HasVMLxHazards; }
453461 bool hasSlowOddRegister() const { return SlowOddRegister; }
454462 bool hasSlowLoadDSubregister() const { return SlowLoadDSubregister; }
455463 bool hasMuxedUnits() const { return HasMuxedUnits; }
384384 TRI = Fn.getSubtarget().getRegisterInfo();
385385 MRI = &Fn.getRegInfo();
386386 const ARMSubtarget *STI = &Fn.getSubtarget();
387 // Only run this for CortexA9.
388 if (!STI->isCortexA9())
387 if (!STI->expandMLx())
389388 return false;
390389 isLikeA9 = STI->isLikeA9() || STI->isSwift();
391390 isSwift = STI->isSwift();