llvm.org GIT mirror llvm / 08293d1
[ARM] Add MVE interleaving load/store family. This adds the family of loads and stores with names like VLD20.8 and VST42.32, which load and store parts of multiple q-registers in such a way that executing both VLD20 and VLD21, or all four of VLD40..VLD43, will distribute 2 or 4 vectors' worth of memory data across the lanes of the same number of registers but in a transposed order. In addition to the Tablegen descriptions of the instructions themselves, this patch also adds encode and decode support for the QQPR and QQQQPR register classes (representing the range of loaded or stored vector registers), and tweaks to the parsing system for lists of vector registers to make it return the right format in this case (since, unlike NEON, MVE regards q-registers as primitive, and not just an alias for two d-registers). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364172 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Tatham 1 year, 1 month ago
9 changed file(s) with 809 addition(s) and 33 deletion(s). Raw diff Collapse all Expand all
123123 let ParserMatchClass = pred_restricted_fp_asmoperand;
124124 let DecoderMethod = "DecodeRestrictedFPPredicateOperand";
125125 let EncoderMethod = "getRestrictedCondCodeOpValue";
126 }
127
128 // Register list operands for interleaving load/stores
129 def VecList2QAsmOperand : AsmOperandClass {
130 let Name = "VecListTwoMQ";
131 let ParserMethod = "parseVectorList";
132 let RenderMethod = "addMVEVecListOperands";
133 let DiagnosticString = "operand must be a list of two consecutive "#
134 "q-registers in range [q0,q7]";
135 }
136
137 def VecList2Q : RegisterOperand {
138 let ParserMatchClass = VecList2QAsmOperand;
139 let PrintMethod = "printMVEVectorList<2>";
140 }
141
142 def VecList4QAsmOperand : AsmOperandClass {
143 let Name = "VecListFourMQ";
144 let ParserMethod = "parseVectorList";
145 let RenderMethod = "addMVEVecListOperands";
146 let DiagnosticString = "operand must be a list of four consecutive "#
147 "q-registers in range [q0,q7]";
148 }
149
150 def VecList4Q : RegisterOperand {
151 let ParserMatchClass = VecList4QAsmOperand;
152 let PrintMethod = "printMVEVectorList<4>";
126153 }
127154
128155 class MVE_MI
31103137
31113138 // end of coproc mov
31123139
3140 // start of MVE interleaving load/store
3141
3142 // Base class for the family of interleaving/deinterleaving
3143 // load/stores with names like VLD20.8 and VST43.32.
3144 class MVE_vldst24_base stage, bits<2> size,
3145 bit load, dag Oops, dag loadIops, dag wbIops,
3146 string iname, string ops,
3147 string cstr, list pattern=[]>
3148 : MVE_MI {
3149 bits<4> VQd;
3150 bits<4> Rn;
3151
3152 let Inst{31-22} = 0b1111110010;
3153 let Inst{21} = writeback;
3154 let Inst{20} = load;
3155 let Inst{19-16} = Rn;
3156 let Inst{15-13} = VQd{2-0};
3157 let Inst{12-9} = 0b1111;
3158 let Inst{8-7} = size;
3159 let Inst{6-5} = stage;
3160 let Inst{4-1} = 0b0000;
3161 let Inst{0} = fourregs;
3162
3163 let mayLoad = load;
3164 let mayStore = !eq(load,0);
3165 }
3166
3167 // A parameter class used to encapsulate all the ways the writeback
3168 // variants of VLD20 and friends differ from the non-writeback ones.
3169 class MVE_vldst24_writeback
3170 string sy="", string c="", string n=""> {
3171 bit writeback = b;
3172 dag Oops = Oo;
3173 dag Iops = Io;
3174 string syntax = sy;
3175 string cstr = c;
3176 string id_suffix = n;
3177 }
3178
3179 // Another parameter class that encapsulates the differences between VLD2x
3180 // and VLD4x.
3181 class MVE_vldst24_nvecs s, bit b, RegisterOperand vl> {
3182 int nvecs = n;
3183 list stages = s;
3184 bit bit0 = b;
3185 RegisterOperand VecList = vl;
3186 }
3187
3188 // A third parameter class that distinguishes VLDnn.8 from .16 from .32.
3189 class MVE_vldst24_lanesize b> {
3190 int lanesize = i;
3191 bits<2> sizebits = b;
3192 }
3193
3194 // A base class for each direction of transfer: one for load, one for
3195 // store. I can't make these a fourth independent parametric tuple
3196 // class, because they have to take the nvecs tuple class as a
3197 // parameter, in order to find the right VecList operand type.
3198
3199 class MVE_vld24_base pat, bits<2> size,
3200 MVE_vldst24_writeback wb, string iname,
3201 list pattern=[]>
3202 : MVE_vldst24_base
3203 !con((outs n.VecList:$VQd), wb.Oops),
3204 (ins n.VecList:$VQdSrc), wb.Iops,
3205 iname, "$VQd, $Rn" # wb.syntax,
3206 wb.cstr # ",$VQdSrc = $VQd", pattern>;
3207
3208 class MVE_vst24_base pat, bits<2> size,
3209 MVE_vldst24_writeback wb, string iname,
3210 list pattern=[]>
3211 : MVE_vldst24_base
3212 wb.Oops, (ins n.VecList:$VQd), wb.Iops,
3213 iname, "$VQd, $Rn" # wb.syntax,
3214 wb.cstr, pattern>;
3215
3216 // Actually define all the interleaving loads and stores, by a series
3217 // of nested foreaches over number of vectors (VLD2/VLD4); stage
3218 // within one of those series (VLDx0/VLDx1/VLDx2/VLDx3); size of
3219 // vector lane; writeback or no writeback.
3220 foreach n = [MVE_vldst24_nvecs<2, [0,1], 0, VecList2Q>,
3221 MVE_vldst24_nvecs<4, [0,1,2,3], 1, VecList4Q>] in
3222 foreach stage = n.stages in
3223 foreach s = [MVE_vldst24_lanesize< 8, 0b00>,
3224 MVE_vldst24_lanesize<16, 0b01>,
3225 MVE_vldst24_lanesize<32, 0b10>] in
3226 foreach wb = [MVE_vldst24_writeback<
3227 1, (outs rGPR:$wb), (ins t2_nosp_addr_offset_none:$Rn),
3228 "!", "$Rn.base = $wb", "_wb">,
3229 MVE_vldst24_writeback<0, (outs), (ins t2_addr_offset_none:$Rn)>] in {
3230
3231 // For each case within all of those foreaches, define the actual
3232 // instructions. The def names are made by gluing together pieces
3233 // from all the parameter classes, and will end up being things like
3234 // MVE_VLD20_8 and MVE_VST43_16_wb.
3235
3236 def "MVE_VLD" # n.nvecs # stage # "_" # s.lanesize # wb.id_suffix
3237 : MVE_vld24_base
3238 "vld" # n.nvecs # stage # "." # s.lanesize>;
3239
3240 def "MVE_VST" # n.nvecs # stage # "_" # s.lanesize # wb.id_suffix
3241 : MVE_vst24_base
3242 "vst" # n.nvecs # stage # "." # s.lanesize>;
3243 }
3244
3245 // end of MVE interleaving load/store
3246
31133247 class MVE_VPT size, dag iops, string asm, list pattern=[]>
31143248 : MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm, "", pattern> {
31153249 bits<3> fc;
175175 : AsmOperandClass { let Name = "MemNoOffsetT2NoSp"; }
176176 def t2_nosp_addr_offset_none : MemOperand {
177177 let PrintMethod = "printAddrMode7Operand";
178 let DecoderMethod = "Decodet2rGPRRegisterClass";
178 let DecoderMethod = "DecoderGPRRegisterClass";
179179 let ParserMatchClass = MemNoOffsetT2NoSpAsmOperand;
180 let MIOperandInfo = (ops t2rGPR:$base);
180 let MIOperandInfo = (ops rGPR:$base);
181181 }
182182
183183 // t2addrmode_imm12 := reg + imm12
295295 let DiagnosticType = "rGPR";
296296 }
297297
298 // t2rGPR : All Thumb 2 registers with the exception of SP and PC.
299 def t2rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
300 let AltOrders = [(add LR, t2rGPR), (trunc t2rGPR, 8)];
301 let AltOrderSelect = [{
302 return 1 + MF.getSubtarget().isThumb1Only();
303 }];
304 let DiagnosticType = "rGPR";
305 }
306
307298 // Thumb registers are R0-R7 normally. Some instructions can still use
308299 // the general GPR register class above (MOV, e.g.)
309300 def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)> {
17581758 return VectorList.Count == 1;
17591759 }
17601760
1761 bool isVecListTwoMQ() const {
1762 return isSingleSpacedVectorList() && VectorList.Count == 2 &&
1763 ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1764 VectorList.RegNum);
1765 }
1766
17611767 bool isVecListDPair() const {
17621768 if (!isSingleSpacedVectorList()) return false;
17631769 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
17891795 bool isVecListFourQ() const {
17901796 if (!isDoubleSpacedVectorList()) return false;
17911797 return VectorList.Count == 4;
1798 }
1799
1800 bool isVecListFourMQ() const {
1801 return isSingleSpacedVectorList() && VectorList.Count == 4 &&
1802 ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1803 VectorList.RegNum);
17921804 }
17931805
17941806 bool isSingleSpacedVectorAllLanes() const {
25452557 }
25462558
25472559 void addMemNoOffsetT2Operands(MCInst &Inst, unsigned N) const {
2560 assert(N == 1 && "Invalid number of operands!");
2561 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2562 }
2563
2564 void addMemNoOffsetT2NoSpOperands(MCInst &Inst, unsigned N) const {
25482565 assert(N == 1 && "Invalid number of operands!");
25492566 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
25502567 }
29702987 void addVecListOperands(MCInst &Inst, unsigned N) const {
29712988 assert(N == 1 && "Invalid number of operands!");
29722989 Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2990 }
2991
2992 void addMVEVecListOperands(MCInst &Inst, unsigned N) const {
2993 assert(N == 1 && "Invalid number of operands!");
2994
2995 // When we come here, the VectorList field will identify a range
2996 // of q-registers by its base register and length, and it will
2997 // have already been error-checked to be the expected length of
2998 // range and contain only q-regs in the range q0-q7. So we can
2999 // count on the base register being in the range q0-q6 (for 2
3000 // regs) or q0-q4 (for 4)
3001 //
3002 // The MVE instructions taking a register range of this kind will
3003 // need an operand in the QQPR or QQQQPR class, representing the
3004 // entire range as a unit. So we must translate into that class,
3005 // by finding the index of the base register in the MQPR reg
3006 // class, and returning the super-register at the corresponding
3007 // index in the target class.
3008
3009 const MCRegisterClass *RC_in = &ARMMCRegisterClasses[ARM::MQPRRegClassID];
3010 const MCRegisterClass *RC_out = (VectorList.Count == 2) ?
3011 &ARMMCRegisterClasses[ARM::QQPRRegClassID] :
3012 &ARMMCRegisterClasses[ARM::QQQQPRRegClassID];
3013
3014 unsigned I, E = RC_out->getNumRegs();
3015 for (I = 0; I < E; I++)
3016 if (RC_in->getRegister(I) == VectorList.RegNum)
3017 break;
3018 assert(I < E && "Invalid vector list start register!");
3019
3020 Inst.addOperand(MCOperand::createReg(RC_out->getRegister(I)));
29733021 }
29743022
29753023 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
42564304 // As an extension (to match gas), support a plain D register or Q register
42574305 // (without encosing curly braces) as a single or double entry list,
42584306 // respectively.
4259 if (Parser.getTok().is(AsmToken::Identifier)) {
4307 if (!hasMVE() && Parser.getTok().is(AsmToken::Identifier)) {
42604308 SMLoc E = Parser.getTok().getEndLoc();
42614309 int Reg = tryParseRegister();
42624310 if (Reg == -1)
43244372 unsigned Count = 1;
43254373 int Spacing = 0;
43264374 unsigned FirstReg = Reg;
4375
4376 if (hasMVE() && !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) {
4377 Error(Parser.getTok().getLoc(), "vector register in range Q0-Q7 expected");
4378 return MatchOperand_ParseFail;
4379 }
43274380 // The list is of D registers, but we also allow Q regs and just interpret
43284381 // them as the two D sub-registers.
4329 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4382 else if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
43304383 FirstReg = Reg = getDRegFromQReg(Reg);
43314384 Spacing = 1; // double-spacing requires explicit D registers, otherwise
43324385 // it's ambiguous with four-register single spaced.
43564409 return MatchOperand_ParseFail;
43574410 }
43584411 // Allow Q regs and just interpret them as the two D sub-registers.
4359 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
4412 if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
43604413 EndReg = getDRegFromQReg(EndReg) + 1;
43614414 // If the register is the same as the start reg, there's nothing
43624415 // more to do.
43634416 if (Reg == EndReg)
43644417 continue;
43654418 // The register must be in the same register class as the first.
4366 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
4419 if ((hasMVE() &&
4420 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(EndReg)) ||
4421 (!hasMVE() &&
4422 !ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg))) {
43674423 Error(AfterMinusLoc, "invalid register in register list");
43684424 return MatchOperand_ParseFail;
43694425 }
43964452 Error(RegLoc, "register expected");
43974453 return MatchOperand_ParseFail;
43984454 }
4455
4456 if (hasMVE()) {
4457 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) {
4458 Error(RegLoc, "vector register in range Q0-Q7 expected");
4459 return MatchOperand_ParseFail;
4460 }
4461 Spacing = 1;
4462 }
43994463 // vector register lists must be contiguous.
44004464 // It's OK to use the enumeration values directly here rather, as the
44014465 // VFP register classes have the enum sorted properly.
44024466 //
44034467 // The list is of D registers, but we also allow Q regs and just interpret
44044468 // them as the two D sub-registers.
4405 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4469 else if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
44064470 if (!Spacing)
44074471 Spacing = 1; // Register range implies a single spaced list.
44084472 else if (Spacing == 2) {
44634527
44644528 switch (LaneKind) {
44654529 case NoLanes:
4530 case AllLanes: {
44664531 // Two-register operands have been converted to the
44674532 // composite register classes.
4468 if (Count == 2) {
4533 if (Count == 2 && !hasMVE()) {
44694534 const MCRegisterClass *RC = (Spacing == 1) ?
44704535 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
44714536 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
44724537 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
44734538 }
4474 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
4475 (Spacing == 2), S, E));
4539 auto Create = (LaneKind == NoLanes ? ARMOperand::CreateVectorList :
4540 ARMOperand::CreateVectorListAllLanes);
4541 Operands.push_back(Create(FirstReg, Count, (Spacing == 2), S, E));
44764542 break;
4477 case AllLanes:
4478 // Two-register operands have been converted to the
4479 // composite register classes.
4480 if (Count == 2) {
4481 const MCRegisterClass *RC = (Spacing == 1) ?
4482 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
4483 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
4484 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
4485 }
4486 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
4487 (Spacing == 2),
4488 S, E));
4489 break;
4543 }
44904544 case IndexedLane:
44914545 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
44924546 LaneIndex,
61266180 Mnemonic == "csinc" || Mnemonic == "csinv" || Mnemonic == "csneg" ||
61276181 Mnemonic == "cinc" || Mnemonic == "cinv" || Mnemonic == "cneg" ||
61286182 Mnemonic == "cset" || Mnemonic == "csetm" ||
6129 Mnemonic.startswith("vpt") || Mnemonic.startswith("vpst")) {
6183 Mnemonic.startswith("vpt") || Mnemonic.startswith("vpst") ||
6184 (hasMVE() &&
6185 (Mnemonic.startswith("vst2") || Mnemonic.startswith("vld2") ||
6186 Mnemonic.startswith("vst4") || Mnemonic.startswith("vld4")))) {
61306187 // These mnemonics are never predicable
61316188 CanAcceptPredicationCode = false;
61326189 } else if (!isThumb()) {
63826439 bool ARMAsmParser::shouldOmitVectorPredicateOperand(StringRef Mnemonic,
63836440 OperandVector &Operands) {
63846441 if (!hasMVE() || Operands.size() < 3)
6442 return true;
6443
6444 if (Mnemonic.startswith("vld2") || Mnemonic.startswith("vld4") ||
6445 Mnemonic.startswith("vst2") || Mnemonic.startswith("vst4"))
63856446 return true;
63866447
63876448 if (Mnemonic.startswith("vctp"))
218218 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
219219 uint64_t Address, const void *Decoder);
220220 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
221 uint64_t Address, const void *Decoder);
222 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
223 uint64_t Address, const void *Decoder);
224 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
221225 uint64_t Address, const void *Decoder);
222226 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
223227 uint64_t Address, const void *Decoder);
59395943 return MCDisassembler::Success;
59405944 }
59415945
5946 static const uint16_t QQPRDecoderTable[] = {
5947 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4,
5948 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7
5949 };
5950
5951 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
5952 uint64_t Address,
5953 const void *Decoder) {
5954 if (RegNo > 6)
5955 return MCDisassembler::Fail;
5956
5957 unsigned Register = QQPRDecoderTable[RegNo];
5958 Inst.addOperand(MCOperand::createReg(Register));
5959 return MCDisassembler::Success;
5960 }
5961
5962 static const uint16_t QQQQPRDecoderTable[] = {
5963 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5,
5964 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7
5965 };
5966
5967 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
5968 uint64_t Address,
5969 const void *Decoder) {
5970 if (RegNo > 4)
5971 return MCDisassembler::Fail;
5972
5973 unsigned Register = QQQQPRDecoderTable[RegNo];
5974 Inst.addOperand(MCOperand::createReg(Register));
5975 return MCDisassembler::Success;
5976 }
5977
59425978 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
59435979 uint64_t Address,
59445980 const void *Decoder) {
15871587 O << "}";
15881588 }
15891589
1590 template
1591 void ARMInstPrinter::printMVEVectorList(const MCInst *MI, unsigned OpNum,
1592 const MCSubtargetInfo &STI,
1593 raw_ostream &O) {
1594 unsigned Reg = MI->getOperand(OpNum).getReg();
1595 const char *Prefix = "{";
1596 for (unsigned i = 0; i < NumRegs; i++) {
1597 O << Prefix;
1598 printRegName(O, MRI.getSubReg(Reg, ARM::qsub_0 + i));
1599 Prefix = ", ";
1600 }
1601 O << "}";
1602 }
1603
15901604 template
15911605 void ARMInstPrinter::printComplexRotationOp(const MCInst *MI, unsigned OpNo,
15921606 const MCSubtargetInfo &STI,
242242 const MCSubtargetInfo &STI, raw_ostream &O);
243243 void printVectorListFourSpaced(const MCInst *MI, unsigned OpNum,
244244 const MCSubtargetInfo &STI, raw_ostream &O);
245 template
246 void printMVEVectorList(const MCInst *MI, unsigned OpNum,
247 const MCSubtargetInfo &STI, raw_ostream &O);
245248 template
246249 void printComplexRotationOp(const MCInst *MI, unsigned OpNum,
247250 const MCSubtargetInfo &STI, raw_ostream &O);
0 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s 2> %t \
1 # RUN: | FileCheck --check-prefix=CHECK %s
2 # RUN: FileCheck --check-prefix=ERROR < %t %s
3
4 # CHECK: vld20.8 {q0, q1}, [sp] @ encoding: [0x9d,0xfc,0x00,0x1e]
5 vld20.8 {q0, q1}, [sp]
6
7 # CHECK: vld20.8 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x00,0x1e]
8 vld20.8 {q0, q1}, [r0]
9
10 # CHECK: vld20.8 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x00,0x1e]
11 vld20.8 {q0, q1}, [r0]!
12
13 # CHECK: vld20.8 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x00,0x1e]
14 vld20.8 {q0, q1}, [r11]
15
16 # CHECK: vld20.8 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x00,0xbe]
17 vld20.8 {q5, q6}, [r0]!
18
19 # CHECK: vld21.8 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x20,0x1e]
20 vld21.8 {q0, q1}, [r0]
21
22 # CHECK: vld21.8 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0x20,0x7e]
23 vld21.8 {q3, q4}, [r0]!
24
25 # CHECK: vld20.16 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x80,0x1e]
26 vld20.16 {q0, q1}, [r0]
27
28 # CHECK: vld20.16 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x80,0x1e]
29 vld20.16 {q0, q1}, [r0]!
30
31 # CHECK: vld20.16 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x80,0x1e]
32 vld20.16 {q0, q1}, [r11]
33
34 # CHECK: vld20.16 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x80,0xbe]
35 vld20.16 {q5, q6}, [r0]!
36
37 # CHECK: vld21.16 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0xa0,0x1e]
38 vld21.16 {q0, q1}, [r0]
39
40 # CHECK: vld21.16 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0xa0,0x7e]
41 vld21.16 {q3, q4}, [r0]!
42
43 # CHECK: vld20.32 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x00,0x1f]
44 vld20.32 {q0, q1}, [r0]
45
46 # CHECK: vld20.32 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x00,0x1f]
47 vld20.32 {q0, q1}, [r0]!
48
49 # CHECK: vld20.32 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x00,0x1f]
50 vld20.32 {q0, q1}, [r11]
51
52 # CHECK: vld20.32 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x00,0xbf]
53 vld20.32 {q5, q6}, [r0]!
54
55 # CHECK: vld21.32 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x20,0x1f]
56 vld21.32 {q0, q1}, [r0]
57
58 # CHECK: vld21.32 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0x20,0x7f]
59 vld21.32 {q3, q4}, [r0]!
60
61 # CHECK: vst20.8 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x00,0x1e]
62 vst20.8 {q0, q1}, [r0]
63
64 # CHECK: vst20.8 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x00,0x1e]
65 vst20.8 {q0, q1}, [r0]!
66
67 # CHECK: vst20.8 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x00,0x1e]
68 vst20.8 {q0, q1}, [r11]
69
70 # CHECK: vst20.8 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x00,0xbe]
71 vst20.8 {q5, q6}, [r0]!
72
73 # CHECK: vst21.8 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x20,0x1e]
74 vst21.8 {q0, q1}, [r0]
75
76 # CHECK: vst21.8 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0x20,0x7e]
77 vst21.8 {q3, q4}, [r0]!
78
79 # CHECK: vst20.16 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x80,0x1e]
80 vst20.16 {q0, q1}, [r0]
81
82 # CHECK: vst20.16 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x80,0x1e]
83 vst20.16 {q0, q1}, [r0]!
84
85 # CHECK: vst20.16 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x80,0x1e]
86 vst20.16 {q0, q1}, [r11]
87
88 # CHECK: vst20.16 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x80,0xbe]
89 vst20.16 {q5, q6}, [r0]!
90
91 # CHECK: vst21.16 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0xa0,0x1e]
92 vst21.16 {q0, q1}, [r0]
93
94 # CHECK: vst21.16 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0xa0,0x7e]
95 vst21.16 {q3, q4}, [r0]!
96
97 # CHECK: vst20.32 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x00,0x1f]
98 vst20.32 {q0, q1}, [r0]
99
100 # CHECK: vst20.32 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x00,0x1f]
101 vst20.32 {q0, q1}, [r0]!
102
103 # CHECK: vst20.32 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x00,0x1f]
104 vst20.32 {q0, q1}, [r11]
105
106 # CHECK: vst20.32 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x00,0xbf]
107 vst20.32 {q5, q6}, [r0]!
108
109 # CHECK: vst21.32 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x20,0x1f]
110 vst21.32 {q0, q1}, [r0]
111
112 # CHECK: vst21.32 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0x20,0x7f]
113 vst21.32 {q3, q4}, [r0]!
114
115 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
116 vld20.8 {q0, q1}, [sp]!
117
118 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
119 vld20.64 {q0, q1}, [r0]
120
121 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: non-contiguous register range
122 vld20.32 {q0, q2}, [r0]
123
124 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a list of two consecutive q-registers in range [q0,q7]
125 vld20.32 {q0, q1, q2}, [r0]
126
127 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a list of two consecutive q-registers in range [q0,q7]
128 vld20.32 {q0}, [r0]
129
130 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
131 vld20.32 q0, q1, [r0]
132
133 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector register in range Q0-Q7 expected
134 vld20.32 {q7, q8}, [r0]
135
136 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector register in range Q0-Q7 expected
137 vld20.32 {d0, d1}, [r0]
138
139 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
140 vld22.32 {q0, q1}, [r0]
141
142 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
143 vld20.32 {q0, q1}, [pc]
144
145 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
146 vld20.32 {q0, q1}, [r0, #4]
147
148 # CHECK: vld40.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x01,0x1e]
149 vld40.8 {q0, q1, q2, q3}, [r0]
150
151 # CHECK: vld40.8 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x1e]
152 vld40.8 {q0, q1, q2, q3}, [r0]!
153
154 # CHECK: vld40.8 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x01,0x1e]
155 vld40.8 {q0, q1, q2, q3}, [r11]
156
157 # CHECK: vld40.8 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x7e]
158 vld40.8 {q3, q4, q5, q6}, [r0]!
159
160 # CHECK: vld41.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x21,0x1e]
161 vld41.8 {q0, q1, q2, q3}, [r0]
162
163 # CHECK: vld41.8 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x21,0x9e]
164 vld41.8 {q4, q5, q6, q7}, [r0]!
165
166 # CHECK: vld42.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x41,0x1e]
167 vld42.8 {q0, q1, q2, q3}, [r0]
168
169 # CHECK: vld42.8 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x41,0x1e]
170 vld42.8 {q0, q1, q2, q3}, [r0]!
171
172 # CHECK: vld43.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x61,0x1e]
173 vld43.8 {q0, q1, q2, q3}, [r0]
174
175 # CHECK: vld43.8 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x61,0x9e]
176 vld43.8 {q4, q5, q6, q7}, [r0]!
177
178 # CHECK: vld40.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x81,0x1e]
179 vld40.16 {q0, q1, q2, q3}, [r0]
180
181 # CHECK: vld40.16 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x81,0x1e]
182 vld40.16 {q0, q1, q2, q3}, [r0]!
183
184 # CHECK: vld40.16 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x81,0x1e]
185 vld40.16 {q0, q1, q2, q3}, [r11]
186
187 # CHECK: vld40.16 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x81,0x7e]
188 vld40.16 {q3, q4, q5, q6}, [r0]!
189
190 # CHECK: vld41.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xa1,0x1e]
191 vld41.16 {q0, q1, q2, q3}, [r0]
192
193 # CHECK: vld41.16 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0xa1,0x9e]
194 vld41.16 {q4, q5, q6, q7}, [r0]!
195
196 # CHECK: vld42.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xc1,0x1e]
197 vld42.16 {q0, q1, q2, q3}, [r0]
198
199 # CHECK: vld42.16 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0xc1,0x1e]
200 vld42.16 {q0, q1, q2, q3}, [r0]!
201
202 # CHECK: vld43.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xe1,0x1e]
203 vld43.16 {q0, q1, q2, q3}, [r0]
204
205 # CHECK: vld43.16 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0xe1,0x9e]
206 vld43.16 {q4, q5, q6, q7}, [r0]!
207
208 # CHECK: vld40.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x01,0x1f]
209 vld40.32 {q0, q1, q2, q3}, [r0]
210
211 # CHECK: vld40.32 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x1f]
212 vld40.32 {q0, q1, q2, q3}, [r0]!
213
214 # CHECK: vld40.32 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x01,0x1f]
215 vld40.32 {q0, q1, q2, q3}, [r11]
216
217 # CHECK: vld40.32 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x7f]
218 vld40.32 {q3, q4, q5, q6}, [r0]!
219
220 # CHECK: vld41.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x21,0x1f]
221 vld41.32 {q0, q1, q2, q3}, [r0]
222
223 # CHECK: vld41.32 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x21,0x9f]
224 vld41.32 {q4, q5, q6, q7}, [r0]!
225
226 # CHECK: vld42.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x41,0x1f]
227 vld42.32 {q0, q1, q2, q3}, [r0]
228
229 # CHECK: vld42.32 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x41,0x1f]
230 vld42.32 {q0, q1, q2, q3}, [r0]!
231
232 # CHECK: vld43.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x61,0x1f]
233 vld43.32 {q0, q1, q2, q3}, [r0]
234
235 # CHECK: vld43.32 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x61,0x9f]
236 vld43.32 {q4, q5, q6, q7}, [r0]!
237
238 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
239 vld40.64 {q0, q1, q2, q3}, [r0]
240
241 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: non-contiguous register range
242 vld40.32 {q0, q2, q3, q4}, [r0]
243
244 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a list of four consecutive q-registers in range [q0,q7]
245 vld40.32 {q0, q1, q2, q3, q4}, [r0]
246
247 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a list of four consecutive q-registers in range [q0,q7]
248 vld40.32 {q0, q1}, [r0]
249
250 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a list of four consecutive q-registers in range [q0,q7]
251 vld40.32 {q0, q1, q2}, [r0]
252
253 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
254 vld40.32 q0, q1, q2, q3, [r0]
255
256 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector register in range Q0-Q7 expected
257 vld40.32 {q5, q6, q7, q8}, [r0]
258
259 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector register in range Q0-Q7 expected
260 vld40.32 {d0, d1, d2, d3}, [r0]
261
262 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
263 vld44.32 {q0, q1, q2, q3}, [r0]
264
265 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
266 vld40.32 {q0, q1, q2, q3}, [pc]
267
268 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
269 vld40.32 {q0, q1, q2, q3}, [r0, #4]
0 # RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding %s | FileCheck %s
1 # RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
2 # RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
3
4 # CHECK: vld20.8 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x00,0x1e]
5 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
6 [0x90,0xfc,0x00,0x1e]
7
8 # CHECK: vld20.8 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x00,0x1e]
9 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
10 [0xb0,0xfc,0x00,0x1e]
11
12 # CHECK: vld20.8 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x00,0x1e]
13 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
14 [0x9b,0xfc,0x00,0x1e]
15
16 # CHECK: vld20.8 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x00,0xbe]
17 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
18 [0xb0,0xfc,0x00,0xbe]
19
20 # CHECK: vld21.8 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x20,0x1e]
21 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
22 [0x90,0xfc,0x20,0x1e]
23
24 # CHECK: vld21.8 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0x20,0x7e]
25 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
26 [0xb0,0xfc,0x20,0x7e]
27
28 # CHECK: vld20.16 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x80,0x1e]
29 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
30 [0x90,0xfc,0x80,0x1e]
31
32 # CHECK: vld20.16 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x80,0x1e]
33 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
34 [0xb0,0xfc,0x80,0x1e]
35
36 # CHECK: vld20.16 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x80,0x1e]
37 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
38 [0x9b,0xfc,0x80,0x1e]
39
40 # CHECK: vld20.16 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x80,0xbe]
41 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
42 [0xb0,0xfc,0x80,0xbe]
43
44 # CHECK: vld21.16 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0xa0,0x1e]
45 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
46 [0x90,0xfc,0xa0,0x1e]
47
48 # CHECK: vld21.16 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0xa0,0x7e]
49 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
50 [0xb0,0xfc,0xa0,0x7e]
51
52 # CHECK: vld20.32 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x00,0x1f]
53 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
54 [0x90,0xfc,0x00,0x1f]
55
56 # CHECK: vld20.32 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x00,0x1f]
57 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
58 [0xb0,0xfc,0x00,0x1f]
59
60 # CHECK: vld20.32 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x00,0x1f]
61 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
62 [0x9b,0xfc,0x00,0x1f]
63
64 # CHECK: vld20.32 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x00,0xbf]
65 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
66 [0xb0,0xfc,0x00,0xbf]
67
68 # CHECK: vld21.32 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x20,0x1f]
69 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
70 [0x90,0xfc,0x20,0x1f]
71
72 # CHECK: vld21.32 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0x20,0x7f]
73 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
74 [0xb0,0xfc,0x20,0x7f]
75
76 # CHECK: vst20.8 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x00,0x1e]
77 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
78 [0x80,0xfc,0x00,0x1e]
79
80 # CHECK: vst20.8 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x00,0x1e]
81 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
82 [0xa0,0xfc,0x00,0x1e]
83
84 # CHECK: vst20.8 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x00,0x1e]
85 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
86 [0x8b,0xfc,0x00,0x1e]
87
88 # CHECK: vst20.8 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x00,0xbe]
89 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
90 [0xa0,0xfc,0x00,0xbe]
91
92 # CHECK: vst21.8 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x20,0x1e]
93 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
94 [0x80,0xfc,0x20,0x1e]
95
96 # CHECK: vst21.8 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0x20,0x7e]
97 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
98 [0xa0,0xfc,0x20,0x7e]
99
100 # CHECK: vst20.16 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x80,0x1e]
101 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
102 [0x80,0xfc,0x80,0x1e]
103
104 # CHECK: vst20.16 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x80,0x1e]
105 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
106 [0xa0,0xfc,0x80,0x1e]
107
108 # CHECK: vst20.16 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x80,0x1e]
109 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
110 [0x8b,0xfc,0x80,0x1e]
111
112 # CHECK: vst20.16 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x80,0xbe]
113 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
114 [0xa0,0xfc,0x80,0xbe]
115
116 # CHECK: vst21.16 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0xa0,0x1e]
117 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
118 [0x80,0xfc,0xa0,0x1e]
119
120 # CHECK: vst21.16 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0xa0,0x7e]
121 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
122 [0xa0,0xfc,0xa0,0x7e]
123
124 # CHECK: vst20.32 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x00,0x1f]
125 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
126 [0x80,0xfc,0x00,0x1f]
127
128 # CHECK: vst20.32 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x00,0x1f]
129 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
130 [0xa0,0xfc,0x00,0x1f]
131
132 # CHECK: vst20.32 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x00,0x1f]
133 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
134 [0x8b,0xfc,0x00,0x1f]
135
136 # CHECK: vst20.32 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x00,0xbf]
137 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
138 [0xa0,0xfc,0x00,0xbf]
139
140 # CHECK: vst21.32 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x20,0x1f]
141 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
142 [0x80,0xfc,0x20,0x1f]
143
144 # CHECK: vst21.32 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0x20,0x7f]
145 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
146 [0xa0,0xfc,0x20,0x7f]
147
148 # CHECK: vld40.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x01,0x1e]
149 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
150 [0x90,0xfc,0x01,0x1e]
151
152 # CHECK: vld40.8 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x1e]
153 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
154 [0xb0,0xfc,0x01,0x1e]
155
156 # CHECK: vld40.8 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x01,0x1e]
157 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
158 [0x9b,0xfc,0x01,0x1e]
159
160 # CHECK: vld40.8 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x7e]
161 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
162 [0xb0,0xfc,0x01,0x7e]
163
164 # CHECK: vld41.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x21,0x1e]
165 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
166 [0x90,0xfc,0x21,0x1e]
167
168 # CHECK: vld41.8 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x21,0x9e]
169 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
170 [0xb0,0xfc,0x21,0x9e]
171
172 # CHECK: vld42.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x41,0x1e]
173 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
174 [0x90,0xfc,0x41,0x1e]
175
176 # CHECK: vld42.8 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x41,0x1e]
177 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
178 [0xb0,0xfc,0x41,0x1e]
179
180 # CHECK: vld43.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x61,0x1e]
181 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
182 [0x90,0xfc,0x61,0x1e]
183
184 # CHECK: vld43.8 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x61,0x9e]
185 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
186 [0xb0,0xfc,0x61,0x9e]
187
188 # CHECK: vld40.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x81,0x1e]
189 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
190 [0x90,0xfc,0x81,0x1e]
191
192 # CHECK: vld40.16 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x81,0x1e]
193 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
194 [0xb0,0xfc,0x81,0x1e]
195
196 # CHECK: vld40.16 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x81,0x1e]
197 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
198 [0x9b,0xfc,0x81,0x1e]
199
200 # CHECK: vld40.16 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x81,0x7e]
201 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
202 [0xb0,0xfc,0x81,0x7e]
203
204 # CHECK: vld41.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xa1,0x1e]
205 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
206 [0x90,0xfc,0xa1,0x1e]
207
208 # CHECK: vld41.16 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0xa1,0x9e]
209 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
210 [0xb0,0xfc,0xa1,0x9e]
211
212 # CHECK: vld42.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xc1,0x1e]
213 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
214 [0x90,0xfc,0xc1,0x1e]
215
216 # CHECK: vld42.16 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0xc1,0x1e]
217 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
218 [0xb0,0xfc,0xc1,0x1e]
219
220 # CHECK: vld43.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xe1,0x1e]
221 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
222 [0x90,0xfc,0xe1,0x1e]
223
224 # CHECK: vld43.16 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0xe1,0x9e]
225 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
226 [0xb0,0xfc,0xe1,0x9e]
227
228 # CHECK: vld40.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x01,0x1f]
229 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
230 [0x90,0xfc,0x01,0x1f]
231
232 # CHECK: vld40.32 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x1f]
233 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
234 [0xb0,0xfc,0x01,0x1f]
235
236 # CHECK: vld40.32 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x01,0x1f]
237 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
238 [0x9b,0xfc,0x01,0x1f]
239
240 # CHECK: vld40.32 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x7f]
241 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
242 [0xb0,0xfc,0x01,0x7f]
243
244 # CHECK: vld41.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x21,0x1f]
245 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
246 [0x90,0xfc,0x21,0x1f]
247
248 # CHECK: vld41.32 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x21,0x9f]
249 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
250 [0xb0,0xfc,0x21,0x9f]
251
252 # CHECK: vld42.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x41,0x1f]
253 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
254 [0x90,0xfc,0x41,0x1f]
255
256 # CHECK: vld42.32 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x41,0x1f]
257 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
258 [0xb0,0xfc,0x41,0x1f]
259
260 # CHECK: vld43.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x61,0x1f]
261 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
262 [0x90,0xfc,0x61,0x1f]
263
264 # CHECK: vld43.32 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x61,0x9f]
265 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
266 [0xb0,0xfc,0x61,0x9f]