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[ARM] GlobalISel: Allow i8 and i16 adds Teach the instruction selector and legalizer that it's ok to have adds with 8 or 16-bit integers. This is the second part of https://reviews.llvm.org/D27704 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290105 91177308-0d34-0410-b5e6-96231b3b80d8 Diana Picus 3 years ago
4 changed file(s) with 128 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
2424
2525 ARMLegalizerInfo::ARMLegalizerInfo() {
2626 using namespace TargetOpcode;
27
2728 const LLT p0 = LLT::pointer(0, 32);
29
30 const LLT s8 = LLT::scalar(8);
31 const LLT s16 = LLT::scalar(16);
2832 const LLT s32 = LLT::scalar(32);
2933
3034 setAction({G_FRAME_INDEX, p0}, Legal);
3236 setAction({G_LOAD, s32}, Legal);
3337 setAction({G_LOAD, 1, p0}, Legal);
3438
35 setAction({G_ADD, s32}, Legal);
39 for (auto Ty : {s8, s16, s32})
40 setAction({G_ADD, Ty}, Legal);
3641
3742 computeTables();
3843 }
2626 %0(s8) = COPY %r0
2727 ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
2828
29 %r0 = COPY %0(s8)
30 ; CHECK: %r0 = COPY [[VREGX]]
29 %1(s8) = COPY %r1
30 ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
31
32 %2(s8) = G_ADD %0, %1
33 ; CHECK: [[VREGSUM:%[0-9]+]] = ADDrr [[VREGX]], [[VREGY]], 14, _, _
34
35 %r0 = COPY %2(s8)
36 ; CHECK: %r0 = COPY [[VREGSUM]]
3137
3238 BX_RET 14, _, implicit %r0
3339 ; CHECK: BX_RET 14, _, implicit %r0
5359 %0(s16) = COPY %r0
5460 ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
5561
56 %r0 = COPY %0(s16)
57 ; CHECK: %r0 = COPY [[VREGX]]
62 %1(s16) = COPY %r1
63 ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
64
65 %2(s16) = G_ADD %0, %1
66 ; CHECK: [[VREGSUM:%[0-9]+]] = ADDrr [[VREGX]], [[VREGY]], 14, _, _
67
68 %r0 = COPY %2(s16)
69 ; CHECK: %r0 = COPY [[VREGSUM]]
5870
5971 BX_RET 14, _, implicit %r0
6072 ; CHECK: BX_RET 14, _, implicit %r0
0 # RUN: llc -mtriple arm-- -global-isel -run-pass=legalizer %s -o - | FileCheck %s
11 --- |
2 define void @test_add_s8() { ret void }
3 define void @test_add_s16() { ret void }
24 define void @test_add_s32() { ret void }
5
36 define void @test_load_from_stack() { ret void }
7 ...
8 ---
9 name: test_add_s8
10 # CHECK-LABEL: name: test_add_s8
11 legalized: false
12 # CHECK: legalized: true
13 regBankSelected: false
14 selected: false
15 tracksRegLiveness: true
16 registers:
17 - { id: 0, class: _ }
18 - { id: 1, class: _ }
19 - { id: 2, class: _ }
20 body: |
21 bb.0:
22 liveins: %r0, %r1
23
24 %0(s8) = COPY %r0
25 %1(s8) = COPY %r1
26 %2(s8) = G_ADD %0, %1
27 ; G_ADD with s8 is legal, so we should find it unchanged in the output
28 ; CHECK: {{%[0-9]+}}(s8) = G_ADD {{%[0-9]+, %[0-9]+}}
29 %r0 = COPY %2(s8)
30 BX_RET 14, _, implicit %r0
31 ...
32 ---
33 name: test_add_s16
34 # CHECK-LABEL: name: test_add_s16
35 legalized: false
36 # CHECK: legalized: true
37 regBankSelected: false
38 selected: false
39 tracksRegLiveness: true
40 registers:
41 - { id: 0, class: _ }
42 - { id: 1, class: _ }
43 - { id: 2, class: _ }
44 body: |
45 bb.0:
46 liveins: %r0, %r1
47
48 %0(s16) = COPY %r0
49 %1(s16) = COPY %r1
50 %2(s16) = G_ADD %0, %1
51 ; G_ADD with s16 is legal, so we should find it unchanged in the output
52 ; CHECK: {{%[0-9]+}}(s16) = G_ADD {{%[0-9]+, %[0-9]+}}
53 %r0 = COPY %2(s16)
54 BX_RET 14, _, implicit %r0
55
456 ...
557 ---
658 name: test_add_s32
55107 %0(p0) = G_FRAME_INDEX %fixed-stack.2
56108 %1(s32) = G_LOAD %0(p0)
57109 BX_RET 14, _
58
59110 ...
0 # RUN: llc -mtriple arm-- -global-isel -run-pass=regbankselect %s -o - | FileCheck %s
11 --- |
22 define void @test_add_s32() { ret void }
3 define void @test_add_s16() { ret void }
4 define void @test_add_s8() { ret void }
35 ...
46 ---
57 name: test_add_s32
2729 BX_RET 14, _, implicit %r0
2830
2931 ...
32 ---
33 name: test_add_s16
34 # CHECK-LABEL: name: test_add_s16
35 legalized: true
36 regBankSelected: false
37 selected: false
38 # CHECK: registers:
39 # CHECK: - { id: 0, class: gprb }
40 # CHECK: - { id: 1, class: gprb }
41 # CHECK: - { id: 2, class: gprb }
42
43 registers:
44 - { id: 0, class: _ }
45 - { id: 1, class: _ }
46 - { id: 2, class: _ }
47 body: |
48 bb.0:
49 liveins: %r0, %r1
50
51 %0(s16) = COPY %r0
52 %1(s16) = COPY %r1
53 %2(s16) = G_ADD %0, %1
54 %r0 = COPY %2(s16)
55 BX_RET 14, _, implicit %r0
56
57 ...
58 ---
59 name: test_add_s8
60 # CHECK-LABEL: name: test_add_s8
61 legalized: true
62 regBankSelected: false
63 selected: false
64 # CHECK: registers:
65 # CHECK: - { id: 0, class: gprb }
66 # CHECK: - { id: 1, class: gprb }
67 # CHECK: - { id: 2, class: gprb }
68
69 registers:
70 - { id: 0, class: _ }
71 - { id: 1, class: _ }
72 - { id: 2, class: _ }
73 body: |
74 bb.0:
75 liveins: %r0, %r1
76
77 %0(s8) = COPY %r0
78 %1(s8) = COPY %r1
79 %2(s8) = G_ADD %0, %1
80 %r0 = COPY %2(s8)
81 BX_RET 14, _, implicit %r0
82
83 ...