llvm.org GIT mirror llvm / 071a279
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41863 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 13 years ago
14 changed file(s) with 336 addition(s) and 268 deletion(s). Raw diff Collapse all Expand all
516516
517517 /// ASI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
518518 /// instruction modifies the CSPR register.
519 let Defs = [CPSR] in {
519520 multiclass ASI1_bin_s_irs opcod, string opc, PatFrag opnode> {
520521 def ri : AI1
521522 opc, "s $dst, $a, $b",
522 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>, Imp<[], [CPSR]>;
523 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
523524 def rr : AI1
524525 opc, "s $dst, $a, $b",
525 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>, Imp<[], [CPSR]>;
526 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
526527 def rs : AI1
527528 opc, "s $dst, $a, $b",
528 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>, Imp<[], [CPSR]>;
529 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
530 }
529531 }
530532
531533 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
532534 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
533535 /// a explicit result, only implicitly set CPSR.
536 let Defs = [CPSR] in {
534537 multiclass AI1_cmp_irs opcod, string opc, PatFrag opnode> {
535538 def ri : AI1
536539 opc, " $a, $b",
537 [(opnode GPR:$a, so_imm:$b)]>, Imp<[], [CPSR]>;
540 [(opnode GPR:$a, so_imm:$b)]>;
538541 def rr : AI1
539542 opc, " $a, $b",
540 [(opnode GPR:$a, GPR:$b)]>, Imp<[], [CPSR]>;
543 [(opnode GPR:$a, GPR:$b)]>;
541544 def rs : AI1
542545 opc, " $a, $b",
543 [(opnode GPR:$a, so_reg:$b)]>, Imp<[], [CPSR]>;
546 [(opnode GPR:$a, so_reg:$b)]>;
547 }
544548 }
545549
546550 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
619623
620624 /// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and
621625 /// setting carry bit. But it can optionally set CPSR.
626 let Uses = [CPSR] in {
622627 multiclass AsXI1_bin_c_irs opcod, string opc, PatFrag opnode> {
623628 def ri : AXI1
624629 DPRIm, !strconcat(opc, "${s} $dst, $a, $b"),
625 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>, Imp<[CPSR], []>;
630 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
626631 def rr : AXI1
627632 DPRReg, !strconcat(opc, "${s} $dst, $a, $b"),
628 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>, Imp<[CPSR], []>;
633 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
629634 def rs : AXI1
630635 DPRSoReg, !strconcat(opc, "${s} $dst, $a, $b"),
631 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>, Imp<[CPSR], []>;
636 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
637 }
632638 }
633639
634640 //===----------------------------------------------------------------------===//
654660 i32imm:$size),
655661 "${instid:label} ${cpidx:cpentry}", []>;
656662
663 let Defs = [SP], Uses = [SP] in {
657664 def ADJCALLSTACKUP :
658665 PseudoInst<(outs), (ins i32imm:$amt, pred:$p),
659666 "@ ADJCALLSTACKUP $amt",
660 [(ARMcallseq_end imm:$amt)]>, Imp<[SP],[SP]>;
667 [(ARMcallseq_end imm:$amt)]>;
661668
662669 def ADJCALLSTACKDOWN :
663670 PseudoInst<(outs), (ins i32imm:$amt, pred:$p),
664671 "@ ADJCALLSTACKDOWN $amt",
665 [(ARMcallseq_start imm:$amt)]>, Imp<[SP],[SP]>;
672 [(ARMcallseq_start imm:$amt)]>;
673 }
666674
667675 def DWARF_LOC :
668676 PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
962970 // These aren't really mov instructions, but we have to define them this way
963971 // due to flag operands.
964972
973 let Defs = [CPSR] in {
965974 def MOVsrl_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
966975 "mov", "s $dst, $src, lsr #1",
967 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, Imp<[], [CPSR]>;
976 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>;
968977 def MOVsra_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
969978 "mov", "s $dst, $src, asr #1",
970 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, Imp<[], [CPSR]>;
979 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>;
980 }
971981
972982 //===----------------------------------------------------------------------===//
973983 // Extend Instructions.
10331043 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
10341044
10351045 // RSB with 's' bit set.
1046 let Defs = [CPSR] in {
10361047 def RSBSri : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
10371048 "rsb", "s $dst, $a, $b",
1038 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>, Imp<[], [CPSR]>;
1049 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>;
10391050 def RSBSrs : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
10401051 "rsb", "s $dst, $a, $b",
1041 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>, Imp<[], [CPSR]>;
1052 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
1053 }
10421054
10431055 // FIXME: Do not allow RSC to be predicated for now. But they can set CPSR.
1056 let Uses = [CPSR] in {
10441057 def RSCri : AXI1<0x7, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
10451058 DPRIm, "rsc${s} $dst, $a, $b",
1046 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>, Imp<[CPSR], []>;
1059 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>;
10471060 def RSCrs : AXI1<0x7, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
10481061 DPRSoReg, "rsc${s} $dst, $a, $b",
1049 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>, Imp<[CPSR], []>;
1062 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>;
1063 }
10501064
10511065 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
10521066 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
159159 // Miscellaneous Instructions.
160160 //
161161
162 let Defs = [SP], Uses = [SP] in {
162163 def tADJCALLSTACKUP :
163164 PseudoInst<(outs), (ins i32imm:$amt),
164165 "@ tADJCALLSTACKUP $amt",
165 [(ARMcallseq_end imm:$amt)]>, Imp<[SP],[SP]>, Requires<[IsThumb]>;
166 [(ARMcallseq_end imm:$amt)]>, Requires<[IsThumb]>;
166167
167168 def tADJCALLSTACKDOWN :
168169 PseudoInst<(outs), (ins i32imm:$amt),
169170 "@ tADJCALLSTACKDOWN $amt",
170 [(ARMcallseq_start imm:$amt)]>, Imp<[SP],[SP]>, Requires<[IsThumb]>;
171 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb]>;
172 }
171173
172174 let isNotDuplicable = 1 in
173175 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp),
284284
285285 // FMSRR: GPR -> SPR
286286
287 def FMSTAT : ASI<(outs), (ins), "fmstat", "", [(arm_fmstat)]>, Imp<[], [CPSR]>;
287 let Defs = [CPSR] in
288 def FMSTAT : ASI<(outs), (ins), "fmstat", "", [(arm_fmstat)]>;
288289
289290 // FMXR: GPR -> VFP Sstem reg
290291
146146
147147 def WTF : PseudoInstAlpha<(outs), (ins variable_ops), "#wtf", [], s_pseudo>;
148148
149 let isLoad = 1, hasCtrlDep = 1 in {
149 let isLoad = 1, hasCtrlDep = 1, Defs = [R30], Uses = [R30] in {
150150 def ADJUSTSTACKUP : PseudoInstAlpha<(outs), (ins s64imm:$amt), "; ADJUP $amt",
151 [(callseq_start imm:$amt)], s_pseudo>, Imp<[R30],[R30]>;
151 [(callseq_start imm:$amt)], s_pseudo>;
152152 def ADJUSTSTACKDOWN : PseudoInstAlpha<(outs), (ins s64imm:$amt), "; ADJDOWN $amt",
153 [(callseq_end imm:$amt)], s_pseudo>, Imp<[R30],[R30]>;
153 [(callseq_end imm:$amt)], s_pseudo>;
154154 }
155155 def ALTENT : PseudoInstAlpha<(outs), (ins s64imm:$TARGET), "$$$TARGET..ng:\n", [], s_pseudo>;
156156 def PCLABEL : PseudoInstAlpha<(outs), (ins s64imm:$num), "PCMARKER_$num:\n",[], s_pseudo>;
340340 MipsInst;
341341
342342 // As stack alignment is always done with addiu, we need a 16-bit immediate
343 let Defs = [SP], Uses = [SP] in {
343344 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins uimm16:$amt),
344345 "!ADJCALLSTACKDOWN $amt",
345 [(callseq_start imm:$amt)]>, Imp<[SP],[SP]>;
346 [(callseq_start imm:$amt)]>;
346347 def ADJCALLSTACKUP : Pseudo<(outs), (ins uimm16:$amt),
347348 "!ADJCALLSTACKUP $amt",
348 [(callseq_end imm:$amt)]>, Imp<[SP],[SP]>;
349 [(callseq_end imm:$amt)]>;
350 }
349351
350352 def IMPLICIT_DEF_CPURegs : Pseudo<(outs CPURegs:$dst), (ins),
351353 "!IMPLICIT_DEF $dst",
129129 PPC970_DGroup_First, PPC970_Unit_FXU;
130130 }
131131
132 let Defs = [X1], Uses = [X1] in
132133 def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),
133134 "${:comment} DYNALLOC8 $result, $negsize, $fpsi",
134135 [(set G8RC:$result,
135 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>,
136 Imp<[X1],[X1]>;
136 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>;
137137
138138 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS),
139139 "mtlr $rS", SprMTSPR>,
296296 // Pseudo-instructions:
297297
298298 let hasCtrlDep = 1 in {
299 let Defs = [R1], Uses = [R1] in {
299300 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt),
300301 "${:comment} ADJCALLSTACKDOWN",
301 [(callseq_start imm:$amt)]>, Imp<[R1],[R1]>;
302 [(callseq_start imm:$amt)]>;
302303 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt),
303304 "${:comment} ADJCALLSTACKUP",
304 [(callseq_end imm:$amt)]>, Imp<[R1],[R1]>;
305 [(callseq_end imm:$amt)]>;
306 }
305307
306308 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
307309 "UPDATE_VRSAVE $rD, $rS", []>;
308310 }
309311
312 let Defs = [R1], Uses = [R1] in
310313 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi),
311314 "${:comment} DYNALLOC $result, $negsize, $fpsi",
312315 [(set GPRC:$result,
313 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>,
314 Imp<[R1],[R1]>;
316 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
315317
316318 def IMPLICIT_DEF_GPRC: Pseudo<(outs GPRC:$rD), (ins),
317319 "${:comment}IMPLICIT_DEF_GPRC $rD",
200200 class Pseudo pattern>
201201 : InstSP;
202202
203 let Defs = [O6], Uses = [O6] in {
203204 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
204205 "!ADJCALLSTACKDOWN $amt",
205 [(callseq_start imm:$amt)]>, Imp<[O6],[O6]>;
206 [(callseq_start imm:$amt)]>;
206207 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt),
207208 "!ADJCALLSTACKUP $amt",
208 [(callseq_end imm:$amt)]>, Imp<[O6],[O6]>;
209 [(callseq_end imm:$amt)]>;
210 }
209211 def IMPLICIT_DEF_Int : Pseudo<(outs IntRegs:$dst), (ins),
210212 "!IMPLICIT_DEF $dst",
211213 [(set IntRegs:$dst, (undef))]>;
202202 string DisableEncoding = "";
203203 }
204204
205 /// Imp - Helper class for specifying the implicit uses/defs set for an
206 /// instruction.
207 class Imp uses, list defs> {
208 list Uses = uses;
209 list Defs = defs;
210 }
211
212205 /// Predicates - These are extra conditionals which are turned into instruction
213206 /// selector matching code. Currently each predicate is just a string.
214207 class Predicate {
140140 def FpGETRESULT80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP,
141141 [(set RFP80:$dst, X86fpget)]>; // FPR = ST(0)
142142
143 let Defs = [ST0] in {
143144 def FpSETRESULT32 : FpI_<(outs), (ins RFP32:$src), SpecialFP,
144 [(X86fpset RFP32:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
145 [(X86fpset RFP32:$src)]>;// ST(0) = FPR
145146
146147 def FpSETRESULT64 : FpI_<(outs), (ins RFP64:$src), SpecialFP,
147 [(X86fpset RFP64:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
148 [(X86fpset RFP64:$src)]>;// ST(0) = FPR
148149
149150 def FpSETRESULT80 : FpI_<(outs), (ins RFP80:$src), SpecialFP,
150 [(X86fpset RFP80:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
151 [(X86fpset RFP80:$src)]>;// ST(0) = FPR
152 }
151153
152154 // FpI - Floating Point Psuedo Instruction template. Predicated on FPStack.
153155 // Note that f80-only instructions are used even in SSE mode and use FpI_
485487 def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
486488 [(X86cmp RFP80:$lhs, RFP80:$rhs)]>; // CC = ST(0) cmp ST(i)
487489
490 let Uses = [ST0] in {
488491 def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
489492 (outs), (ins RST:$reg),
490 "fucom\t$reg">, DD, Imp<[ST0],[]>;
493 "fucom\t$reg">, DD;
491494 def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
492495 (outs), (ins RST:$reg),
493 "fucomp\t$reg">, DD, Imp<[ST0],[]>;
496 "fucomp\t$reg">, DD;
494497 def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
495498 (outs), (ins),
496 "fucompp">, DA, Imp<[ST0],[]>;
499 "fucompp">, DA;
497500
498501 def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
499502 (outs), (ins RST:$reg),
500 "fucomi\t{$reg, %st(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
503 "fucomi\t{$reg, %st(0)|%ST(0), $reg}">, DB;
501504 def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
502505 (outs), (ins RST:$reg),
503 "fucomip\t{$reg, %st(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>;
506 "fucomip\t{$reg, %st(0)|%ST(0), $reg}">, DF;
507 }
504508
505509 // Floating point flag ops.
510 let Defs = [AX] in
506511 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
507 (outs), (ins), "fnstsw", []>, DF, Imp<[],[AX]>;
512 (outs), (ins), "fnstsw", []>, DF;
508513
509514 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
510515 (outs), (ins i16mem:$dst), "fnstcw\t$dst", []>;
245245 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
246246 // a stack adjustment and the codegen must know that they may modify the stack
247247 // pointer before prolog-epilog rewriting occurs.
248 let Defs = [ESP], Uses = [ESP] in {
248249 def ADJCALLSTACKDOWN : I<0, Pseudo, (outs), (ins i32imm:$amt), "#ADJCALLSTACKDOWN",
249 [(X86callseq_start imm:$amt)]>, Imp<[ESP],[ESP]>;
250 [(X86callseq_start imm:$amt)]>;
250251 def ADJCALLSTACKUP : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
251252 "#ADJCALLSTACKUP",
252 [(X86callseq_end imm:$amt1, imm:$amt2)]>,
253 Imp<[ESP],[ESP]>;
253 [(X86callseq_end imm:$amt1, imm:$amt2)]>;
254 }
254255 def IMPLICIT_USE : I<0, Pseudo, (outs), (ins variable_ops),
255256 "#IMPLICIT_USE", []>;
256257 def IMPLICIT_DEF : I<0, Pseudo, (outs variable_ops), (ins),
363364 //===----------------------------------------------------------------------===//
364365 // Miscellaneous Instructions...
365366 //
367 let Defs = [EBP, ESP], Uses = [EBP, ESP] in
366368 def LEAVE : I<0xC9, RawFrm,
367 (outs), (ins), "leave", []>, Imp<[EBP,ESP],[EBP,ESP]>;
369 (outs), (ins), "leave", []>;
370
371 let Defs = [ESP], Uses = [ESP] in {
368372 def POP32r : I<0x58, AddRegFrm,
369 (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, Imp<[ESP],[ESP]>;
373 (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
370374
371375 def PUSH32r : I<0x50, AddRegFrm,
372 (outs), (ins GR32:$reg), "push{l}\t$reg", []>, Imp<[ESP],[ESP]>;
376 (outs), (ins GR32:$reg), "push{l}\t$reg", []>;
377 }
373378
374379 def MovePCtoStack : I<0, Pseudo, (outs), (ins piclabel:$label),
375380 "call\t$label", []>;
418423 "lea{l}\t{$src|$dst}, {$dst|$src}",
419424 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
420425
426 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
421427 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
422 [(X86rep_movs i8)]>,
423 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
428 [(X86rep_movs i8)]>, REP;
424429 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
425 [(X86rep_movs i16)]>,
426 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize;
430 [(X86rep_movs i16)]>, REP, OpSize;
427431 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
428 [(X86rep_movs i32)]>,
429 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
430
432 [(X86rep_movs i32)]>, REP;
433 }
434
435 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
431436 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
432 [(X86rep_stos i8)]>,
433 Imp<[AL,ECX,EDI], [ECX,EDI]>, REP;
437 [(X86rep_stos i8)]>, REP;
438 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
434439 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
435 [(X86rep_stos i16)]>,
436 Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize;
440 [(X86rep_stos i16)]>, REP, OpSize;
441 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
437442 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
438 [(X86rep_stos i32)]>,
439 Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP;
440
443 [(X86rep_stos i32)]>, REP;
444
445 let Defs = [RAX, RDX] in
441446 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
442 TB, Imp<[],[RAX,RDX]>;
447 TB;
443448
444449 //===----------------------------------------------------------------------===//
445450 // Input/Output Instructions...
446451 //
452 let Defs = [AL], Uses = [DX] in
447453 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
448 "in{b}\t{%dx, %al|%AL, %DX}",
449 []>, Imp<[DX], [AL]>;
454 "in{b}\t{%dx, %al|%AL, %DX}", []>;
455 let Defs = [AX], Uses = [DX] in
450456 def IN16rr : I<0xED, RawFrm, (outs), (ins),
451 "in{w}\t{%dx, %ax|%AX, %DX}",
452 []>, Imp<[DX], [AX]>, OpSize;
457 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
458 let Defs = [EAX], Uses = [DX] in
453459 def IN32rr : I<0xED, RawFrm, (outs), (ins),
454 "in{l}\t{%dx, %eax|%EAX, %DX}",
455 []>, Imp<[DX],[EAX]>;
456
460 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
461
462 let Defs = [AL] in
457463 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
458 "in{b}\t{$port, %al|%AL, $port}",
459 []>,
460 Imp<[], [AL]>;
464 "in{b}\t{$port, %al|%AL, $port}", []>;
465 let Defs = [AX] in
461466 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
462 "in{w}\t{$port, %ax|%AX, $port}",
463 []>,
464 Imp<[], [AX]>, OpSize;
467 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
468 let Defs = [EAX] in
465469 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
466 "in{l}\t{$port, %eax|%EAX, $port}",
467 []>,
468 Imp<[],[EAX]>;
469
470 "in{l}\t{$port, %eax|%EAX, $port}", []>;
471
472 let Uses = [DX, AL] in
470473 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
471 "out{b}\t{%al, %dx|%DX, %AL}",
472 []>, Imp<[DX, AL], []>;
474 "out{b}\t{%al, %dx|%DX, %AL}", []>;
475 let Uses = [DX, AX] in
473476 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
474 "out{w}\t{%ax, %dx|%DX, %AX}",
475 []>, Imp<[DX, AX], []>, OpSize;
477 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
478 let Uses = [DX, EAX] in
476479 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
477 "out{l}\t{%eax, %dx|%DX, %EAX}",
478 []>, Imp<[DX, EAX], []>;
479
480 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
481
482 let Uses = [AL] in
480483 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
481 "out{b}\t{%al, $port|$port, %AL}",
482 []>,
483 Imp<[AL], []>;
484 "out{b}\t{%al, $port|$port, %AL}", []>;
485 let Uses = [AX] in
484486 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
485 "out{w}\t{%ax, $port|$port, %AX}",
486 []>,
487 Imp<[AX], []>, OpSize;
487 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
488 let Uses = [EAX] in
488489 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
489 "out{l}\t{%eax, $port|$port, %EAX}",
490 []>,
491 Imp<[EAX], []>;
490 "out{l}\t{%eax, $port|$port, %EAX}", []>;
492491
493492 //===----------------------------------------------------------------------===//
494493 // Move Instructions...
547546 //
548547
549548 // Extra precision multiplication
549 let Defs = [AL,AH], Uses = [AL] in
550550 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
551551 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
552552 // This probably ought to be moved to a def : Pat<> if the
553553 // syntax can be accepted.
554 [(set AL, (mul AL, GR8:$src))]>,
555 Imp<[AL],[AL,AH]>; // AL,AH = AL*GR8
554 [(set AL, (mul AL, GR8:$src))]>; // AL,AH = AL*GR8
555 let Defs = [AX,DX], Uses = [AX] in
556556 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>,
557 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16
558 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l}\t$src", []>,
559 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*GR32
557 OpSize; // AX,DX = AX*GR16
558 let Defs = [EAX,EDX], Uses = [EAX] in
559 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l}\t$src", []>;
560 // EAX,EDX = EAX*GR32
561 let Defs = [AL,AH], Uses = [AL] in
560562 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
561563 "mul{b}\t$src",
562564 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
563565 // This probably ought to be moved to a def : Pat<> if the
564566 // syntax can be accepted.
565 [(set AL, (mul AL, (loadi8 addr:$src)))]>,
566 Imp<[AL],[AL,AH]>; // AL,AH = AL*[mem8]
567 [(set AL, (mul AL, (loadi8 addr:$src)))]>; // AL,AH = AL*[mem8]
568 let Defs = [AX,DX], Uses = [AX] in
567569 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
568 "mul{w}\t$src", []>, Imp<[AX],[AX,DX]>,
569 OpSize; // AX,DX = AX*[mem16]
570 "mul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
571 let Defs = [EAX,EDX], Uses = [EAX] in
570572 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
571 "mul{l}\t$src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32]
572
573 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>,
574 Imp<[AL],[AL,AH]>; // AL,AH = AL*GR8
573 "mul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
574
575 let Defs = [AL,AH], Uses = [AL] in
576 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
577 // AL,AH = AL*GR8
578 let Defs = [AX,DX], Uses = [AX] in
575579 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
576 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16
577 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>,
578 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*GR32
580 OpSize; // AX,DX = AX*GR16
581 let Defs = [EAX,EDX], Uses = [EAX] in
582 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
583 // EAX,EDX = EAX*GR32
584 let Defs = [AL,AH], Uses = [AL] in
579585 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
580 "imul{b}\t$src", []>, Imp<[AL],[AL,AH]>; // AL,AH = AL*[mem8]
586 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
587 let Defs = [AX,DX], Uses = [AX] in
581588 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
582 "imul{w}\t$src", []>, Imp<[AX],[AX,DX]>,
583 OpSize; // AX,DX = AX*[mem16]
589 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
590 let Defs = [EAX,EDX], Uses = [EAX] in
584591 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
585 "imul{l}\t$src", []>,
586 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
592 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
587593
588594 // unsigned division/remainder
595 let Defs = [AX], Uses = [AL,AH] in
589596 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
590 "div{b}\t$src", []>, Imp<[AX],[AX]>;
597 "div{b}\t$src", []>;
598 let Defs = [AX,DX], Uses = [AX,DX] in
591599 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
592 "div{w}\t$src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
600 "div{w}\t$src", []>, OpSize;
601 let Defs = [EAX,EDX], Uses = [EAX,EDX] in
593602 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
594 "div{l}\t$src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
603 "div{l}\t$src", []>;
604 let Defs = [AX], Uses = [AL,AH] in
595605 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
596 "div{b}\t$src", []>, Imp<[AX],[AX]>;
606 "div{b}\t$src", []>;
607 let Defs = [AX,DX], Uses = [AX,DX] in
597608 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
598 "div{w}\t$src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
609 "div{w}\t$src", []>, OpSize;
610 let Defs = [EAX,EDX], Uses = [EAX,EDX] in
599611 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
600 "div{l}\t$src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
612 "div{l}\t$src", []>;
601613
602614 // Signed division/remainder.
615 let Defs = [AX], Uses = [AL,AH] in
603616 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
604 "idiv{b}\t$src", []>, Imp<[AX],[AX]>;
617 "idiv{b}\t$src", []>;
618 let Defs = [AX,DX], Uses = [AX,DX] in
605619 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
606 "idiv{w}\t$src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
620 "idiv{w}\t$src", []>, OpSize;
621 let Defs = [EAX,EDX], Uses = [EAX,EDX] in
607622 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
608 "idiv{l}\t$src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
623 "idiv{l}\t$src", []>;
624 let Defs = [AX], Uses = [AL,AH] in
609625 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
610 "idiv{b}\t$src", []>, Imp<[AX],[AX]>;
626 "idiv{b}\t$src", []>;
627 let Defs = [AX,DX], Uses = [AX,DX] in
611628 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
612 "idiv{w}\t$src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
629 "idiv{w}\t$src", []>, OpSize;
630 let Defs = [EAX,EDX], Uses = [EAX,EDX] in
613631 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
614 "idiv{l}\t$src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
632 "idiv{l}\t$src", []>;
615633
616634
617635 //===----------------------------------------------------------------------===//
12901308 }
12911309
12921310 // Shift instructions
1311 let Uses = [CL] in {
12931312 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
12941313 "shl{b}\t{%cl, $dst|$dst, %CL}",
1295 [(set GR8:$dst, (shl GR8:$src, CL))]>, Imp<[CL],[]>;
1314 [(set GR8:$dst, (shl GR8:$src, CL))]>;
12961315 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
12971316 "shl{w}\t{%cl, $dst|$dst, %CL}",
1298 [(set GR16:$dst, (shl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1317 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
12991318 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
13001319 "shl{l}\t{%cl, $dst|$dst, %CL}",
1301 [(set GR32:$dst, (shl GR32:$src, CL))]>, Imp<[CL],[]>;
1320 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1321 }
13021322
13031323 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
13041324 "shl{b}\t{$src2, $dst|$dst, $src2}",
13211341 "shl{l}\t$dst", []>;
13221342
13231343 let isTwoAddress = 0 in {
1344 let Uses = [CL] in {
13241345 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
13251346 "shl{b}\t{%cl, $dst|$dst, %CL}",
1326 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>,
1327 Imp<[CL],[]>;
1347 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
13281348 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
13291349 "shl{w}\t{%cl, $dst|$dst, %CL}",
1330 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>,
1331 Imp<[CL],[]>, OpSize;
1350 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
13321351 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
13331352 "shl{l}\t{%cl, $dst|$dst, %CL}",
1334 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>,
1335 Imp<[CL],[]>;
1353 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1354 }
13361355 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
13371356 "shl{b}\t{$src, $dst|$dst, $src}",
13381357 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
13571376 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
13581377 }
13591378
1379 let Uses = [CL] in {
13601380 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
13611381 "shr{b}\t{%cl, $dst|$dst, %CL}",
1362 [(set GR8:$dst, (srl GR8:$src, CL))]>, Imp<[CL],[]>;
1382 [(set GR8:$dst, (srl GR8:$src, CL))]>;
13631383 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
13641384 "shr{w}\t{%cl, $dst|$dst, %CL}",
1365 [(set GR16:$dst, (srl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1385 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
13661386 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
13671387 "shr{l}\t{%cl, $dst|$dst, %CL}",
1368 [(set GR32:$dst, (srl GR32:$src, CL))]>, Imp<[CL],[]>;
1388 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1389 }
13691390
13701391 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
13711392 "shr{b}\t{$src2, $dst|$dst, $src2}",
13891410 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
13901411
13911412 let isTwoAddress = 0 in {
1413 let Uses = [CL] in {
13921414 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
13931415 "shr{b}\t{%cl, $dst|$dst, %CL}",
1394 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>,
1395 Imp<[CL],[]>;
1416 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
13961417 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
13971418 "shr{w}\t{%cl, $dst|$dst, %CL}",
13981419 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1399 Imp<[CL],[]>, OpSize;
1420 OpSize;
14001421 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
14011422 "shr{l}\t{%cl, $dst|$dst, %CL}",
1402 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>,
1403 Imp<[CL],[]>;
1423 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1424 }
14041425 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
14051426 "shr{b}\t{$src, $dst|$dst, $src}",
14061427 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
14241445 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
14251446 }
14261447
1448 let Uses = [CL] in {
14271449 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
14281450 "sar{b}\t{%cl, $dst|$dst, %CL}",
1429 [(set GR8:$dst, (sra GR8:$src, CL))]>, Imp<[CL],[]>;
1451 [(set GR8:$dst, (sra GR8:$src, CL))]>;
14301452 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
14311453 "sar{w}\t{%cl, $dst|$dst, %CL}",
1432 [(set GR16:$dst, (sra GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1454 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
14331455 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
14341456 "sar{l}\t{%cl, $dst|$dst, %CL}",
1435 [(set GR32:$dst, (sra GR32:$src, CL))]>, Imp<[CL],[]>;
1457 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1458 }
14361459
14371460 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
14381461 "sar{b}\t{$src2, $dst|$dst, $src2}",
14571480 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
14581481
14591482 let isTwoAddress = 0 in {
1483 let Uses = [CL] in {
14601484 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
14611485 "sar{b}\t{%cl, $dst|$dst, %CL}",
1462 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>,
1463 Imp<[CL],[]>;
1486 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
14641487 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
14651488 "sar{w}\t{%cl, $dst|$dst, %CL}",
1466 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>,
1467 Imp<[CL],[]>, OpSize;
1489 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
14681490 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
14691491 "sar{l}\t{%cl, $dst|$dst, %CL}",
1470 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>,
1471 Imp<[CL],[]>;
1492 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1493 }
14721494 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
14731495 "sar{b}\t{$src, $dst|$dst, $src}",
14741496 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
14951517
14961518 // Rotate instructions
14971519 // FIXME: provide shorter instructions when imm8 == 1
1520 let Uses = [CL] in {
14981521 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
14991522 "rol{b}\t{%cl, $dst|$dst, %CL}",
1500 [(set GR8:$dst, (rotl GR8:$src, CL))]>, Imp<[CL],[]>;
1523 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
15011524 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
15021525 "rol{w}\t{%cl, $dst|$dst, %CL}",
1503 [(set GR16:$dst, (rotl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1526 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
15041527 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
15051528 "rol{l}\t{%cl, $dst|$dst, %CL}",
1506 [(set GR32:$dst, (rotl GR32:$src, CL))]>, Imp<[CL],[]>;
1529 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
1530 }
15071531
15081532 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
15091533 "rol{b}\t{$src2, $dst|$dst, $src2}",
15271551 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
15281552
15291553 let isTwoAddress = 0 in {
1554 let Uses = [CL] in {
15301555 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
15311556 "rol{b}\t{%cl, $dst|$dst, %CL}",
1532 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>,
1533 Imp<[CL],[]>;
1557 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
15341558 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
15351559 "rol{w}\t{%cl, $dst|$dst, %CL}",
1536 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>,
1537 Imp<[CL],[]>, OpSize;
1560 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
15381561 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
15391562 "rol{l}\t{%cl, $dst|$dst, %CL}",
1540 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>,
1541 Imp<[CL],[]>;
1563 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
1564 }
15421565 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
15431566 "rol{b}\t{$src, $dst|$dst, $src}",
15441567 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
15631586 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
15641587 }
15651588
1589 let Uses = [CL] in {
15661590 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
15671591 "ror{b}\t{%cl, $dst|$dst, %CL}",
1568 [(set GR8:$dst, (rotr GR8:$src, CL))]>, Imp<[CL],[]>;
1592 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
15691593 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
15701594 "ror{w}\t{%cl, $dst|$dst, %CL}",
1571 [(set GR16:$dst, (rotr GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1595 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
15721596 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
15731597 "ror{l}\t{%cl, $dst|$dst, %CL}",
1574 [(set GR32:$dst, (rotr GR32:$src, CL))]>, Imp<[CL],[]>;
1598 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
1599 }
15751600
15761601 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
15771602 "ror{b}\t{$src2, $dst|$dst, $src2}",
15951620 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
15961621
15971622 let isTwoAddress = 0 in {
1623 let Uses = [CL] in {
15981624 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
15991625 "ror{b}\t{%cl, $dst|$dst, %CL}",
1600 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>,
1601 Imp<[CL],[]>;
1626 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
16021627 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
16031628 "ror{w}\t{%cl, $dst|$dst, %CL}",
1604 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>,
1605 Imp<[CL],[]>, OpSize;
1629 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
16061630 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
16071631 "ror{l}\t{%cl, $dst|$dst, %CL}",
1608 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>,
1609 Imp<[CL],[]>;
1632 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
1633 }
16101634 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
16111635 "ror{b}\t{$src, $dst|$dst, $src}",
16121636 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
16341658
16351659
16361660 // Double shift instructions (generalizations of rotate)
1661 let Uses = [CL] in {
16371662 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
16381663 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1639 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>,
1640 Imp<[CL],[]>, TB;
1664 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
16411665 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
16421666 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1643 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>,
1644 Imp<[CL],[]>, TB;
1667 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
16451668 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
16461669 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
16471670 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
1648 Imp<[CL],[]>, TB, OpSize;
1671 TB, OpSize;
16491672 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
16501673 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
16511674 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
1652 Imp<[CL],[]>, TB, OpSize;
1675 TB, OpSize;
1676 }
16531677
16541678 let isCommutable = 1 in { // These instructions commute to each other.
16551679 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
16791703 }
16801704
16811705 let isTwoAddress = 0 in {
1706 let Uses = [CL] in {
16821707 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
16831708 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
16841709 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
1685 addr:$dst)]>,
1686 Imp<[CL],[]>, TB;
1710 addr:$dst)]>, TB;
16871711 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
16881712 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
16891713 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
1690 addr:$dst)]>,
1691 Imp<[CL],[]>, TB;
1714 addr:$dst)]>, TB;
1715 }
16921716 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
16931717 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
16941718 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
17021726 (i8 imm:$src3)), addr:$dst)]>,
17031727 TB;
17041728
1729 let Uses = [CL] in {
17051730 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
17061731 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
17071732 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
1708 addr:$dst)]>,
1709 Imp<[CL],[]>, TB, OpSize;
1733 addr:$dst)]>, TB, OpSize;
17101734 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
17111735 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
17121736 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
1713 addr:$dst)]>,
1714 Imp<[CL],[]>, TB, OpSize;
1737 addr:$dst)]>, TB, OpSize;
1738 }
17151739 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
17161740 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
17171741 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
17291753
17301754 // Arithmetic.
17311755 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1732 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1756 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
1757 (ins GR8 :$src1, GR8 :$src2),
17331758 "add{b}\t{$src2, $dst|$dst, $src2}",
17341759 [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>;
17351760 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1736 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1761 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
1762 (ins GR16:$src1, GR16:$src2),
17371763 "add{w}\t{$src2, $dst|$dst, $src2}",
17381764 [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize;
1739 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1765 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
1766 (ins GR32:$src1, GR32:$src2),
17401767 "add{l}\t{$src2, $dst|$dst, $src2}",
17411768 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
17421769 } // end isConvertibleToThreeAddress
17431770 } // end isCommutable
1744 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1771 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
1772 (ins GR8 :$src1, i8mem :$src2),
17451773 "add{b}\t{$src2, $dst|$dst, $src2}",
17461774 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>;
1747 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1775 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
1776 (ins GR16:$src1, i16mem:$src2),
17481777 "add{w}\t{$src2, $dst|$dst, $src2}",
1749 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>, OpSize;
1750 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1778 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>,OpSize;
1779 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
1780 (ins GR32:$src1, i32mem:$src2),
17511781 "add{l}\t{$src2, $dst|$dst, $src2}",
17521782 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>;
17531783
17561786 [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>;
17571787
17581788 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1759 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1789 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
1790 (ins GR16:$src1, i16imm:$src2),
17601791 "add{w}\t{$src2, $dst|$dst, $src2}",
17611792 [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize;
1762 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1793 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
1794 (ins GR32:$src1, i32imm:$src2),
17631795 "add{l}\t{$src2, $dst|$dst, $src2}",
17641796 [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>;
1765 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1797 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
1798 (ins GR16:$src1, i16i8imm:$src2),
17661799 "add{w}\t{$src2, $dst|$dst, $src2}",
1767 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>,
1768 OpSize;
1769 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1800 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1801 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
1802 (ins GR32:$src1, i32i8imm:$src2),
17701803 "add{l}\t{$src2, $dst|$dst, $src2}",
1771 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>;
1804 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>;
17721805 }
17731806
17741807 let isTwoAddress = 0 in {
20322065
20332066
20342067 // Condition code ops, incl. set if equal/not equal/...
2035 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>, Imp<[AH],[]>; // flags = AH
2036 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>, Imp<[],[AH]>; // AH = flags
2068 let Uses = [AH] in
2069 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2070 let Defs = [AH] in
2071 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
20372072
20382073 def SETEr : I<0x94, MRM0r,
20392074 (outs GR8 :$dst), (ins),
22952330 "movz{wl|x}\t{$src, $dst|$dst, $src}",
22962331 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
22972332
2333 let Defs = [AX], Uses = [AL] in
22982334 def CBW : I<0x98, RawFrm, (outs), (ins),
2299 "{cbtw|cbw}", []>, Imp<[AL],[AX]>, OpSize; // AX = signext(AL)
2335 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
2336 let Defs = [EAX], Uses = [AX] in
23002337 def CWDE : I<0x98, RawFrm, (outs), (ins),
2301 "{cwtl|cwde}", []>, Imp<[AX],[EAX]>; // EAX = signext(AX)
2302
2338 "{cwtl|cwde}", []>; // EAX = signext(AX)
2339
2340 let Defs = [AX,DX], Uses = [AX] in
23032341 def CWD : I<0x99, RawFrm, (outs), (ins),
2304 "{cwtd|cwd}", []>, Imp<[AX],[AX,DX]>, OpSize; // DX:AX = signext(AX)
2342 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
2343 let Defs = [EAX,EDX], Uses = [EAX] in
23052344 def CDQ : I<0x99, RawFrm, (outs), (ins),
2306 "{cltd|cdq}", []>, Imp<[EAX],[EAX,EDX]>; // EDX:EAX = signext(EAX)
2345 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
23072346
23082347
23092348 //===----------------------------------------------------------------------===//
23502389 // Thread Local Storage Instructions
23512390 //
23522391
2392 let Uses = [EBX] in
23532393 def TLS_addr : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
23542394 "leal\t${sym:mem}(,%ebx,1), $dst",
2355 [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>,
2356 Imp<[EBX],[]>;
2395 [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
23572396
23582397 let AddedComplexity = 10 in
23592398 def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
475475 [(set GR32:$dst, (int_x86_mmx_pmovmskb VR64:$src))]>;
476476
477477 // Misc.
478 let Uses = [EDI] in
478479 def MMX_MASKMOVQ : MMXI<0xF7, MRMDestMem, (outs), (ins VR64:$src, VR64:$mask),
479480 "maskmovq\t{$mask, $src|$src, $mask}",
480 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>,
481 Imp<[EDI],[]>;
481 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>;
482482
483483 //===----------------------------------------------------------------------===//
484484 // Alias Instructions
20112011 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
20122012
20132013 // Conditional store
2014 let Uses = [EDI] in
20142015 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
20152016 "maskmovdqu\t{$mask, $src|$src, $mask}",
2016 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
2017 Imp<[EDI],[]>;
2017 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
20182018
20192019 // Non-temporal stores
20202020 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
112112 //===----------------------------------------------------------------------===//
113113 // Miscellaneous Instructions...
114114 //
115 let Defs = [RBP,RSP], Uses = [RBP,RSP] in
115116 def LEAVE64 : I<0xC9, RawFrm,
116 (outs), (ins), "leave", []>, Imp<[RBP,RSP],[RBP,RSP]>;
117 (outs), (ins), "leave", []>;
118 let Defs = [RSP], Uses = [RSP] in {
117119 def POP64r : I<0x58, AddRegFrm,
118 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>, Imp<[RSP],[RSP]>;
120 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
119121 def PUSH64r : I<0x50, AddRegFrm,
120 (outs), (ins GR64:$reg), "push{q}\t$reg", []>, Imp<[RSP],[RSP]>;
122 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
123 }
121124
122125 def LEA64_32r : I<0x8D, MRMSrcMem,
123126 (outs GR32:$dst), (ins lea64_32mem:$src),
141144 "xchg{q}\t{$src2|$src1}, {$src1|$src2}", []>;
142145
143146 // Repeat string ops
147 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
144148 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
145 [(X86rep_movs i64)]>,
146 Imp<[RCX,RDI,RSI], [RCX,RDI,RSI]>, REP;
149 [(X86rep_movs i64)]>, REP;
150 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
147151 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
148 [(X86rep_stos i64)]>,
149 Imp<[RAX,RCX,RDI], [RCX,RDI]>, REP;
152 [(X86rep_stos i64)]>, REP;
150153
151154 //===----------------------------------------------------------------------===//
152155 // Move Instructions...
210213 "movz{wq|x}\t{$src, $dst|$dst, $src}",
211214 [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
212215
216 let Defs = [RAX], Uses = [EAX] in
213217 def CDQE : RI<0x98, RawFrm, (outs), (ins),
214 "{cltq|cdqe}", []>, Imp<[EAX],[RAX]>; // RAX = signext(EAX)
215
218 "{cltq|cdqe}", []>; // RAX = signext(EAX)
219
220 let Defs = [RAX,RDX], Uses = [RAX] in
216221 def CQO : RI<0x99, RawFrm, (outs), (ins),
217 "{cqto|cqo}", []>, Imp<[RAX],[RAX,RDX]>; // RDX:RAX = signext(RAX)
222 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
218223
219224 //===----------------------------------------------------------------------===//
220225 // Arithmetic Instructions...
333338 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
334339
335340 // Unsigned multiplication
341 let Defs = [RAX,RDX], Uses = [RAX] in {
336342 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
337 "mul{q}\t$src", []>,
338 Imp<[RAX],[RAX,RDX]>; // RAX,RDX = RAX*GR64
343 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
339344 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
340 "mul{q}\t$src", []>,
341 Imp<[RAX],[RAX,RDX]>; // RAX,RDX = RAX*[mem64]
345 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
342346
343347 // Signed multiplication
344348 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
345 "imul{q}\t$src", []>,
346 Imp<[RAX],[RAX,RDX]>; // RAX,RDX = RAX*GR64
349 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
347350 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
348 "imul{q}\t$src", []>,
349 Imp<[RAX],[RAX,RDX]>; // RAX,RDX = RAX*[mem64]
351 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
352 }
350353
351354 let isTwoAddress = 1 in {
352355 let isCommutable = 1 in
378381 [(set GR64:$dst, (mul (load addr:$src1), i64immSExt8:$src2))]>;
379382
380383 // Unsigned division / remainder
384 let Defs = [RAX,RDX], Uses = [RAX,RDX] in {
381385 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
382 "div{q}\t$src", []>, Imp<[RAX,RDX],[RAX,RDX]>;
386 "div{q}\t$src", []>;
383387 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
384 "div{q}\t$src", []>, Imp<[RAX,RDX],[RAX,RDX]>;
388 "div{q}\t$src", []>;
385389
386390 // Signed division / remainder
387391 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
388 "idiv{q}\t$src", []>, Imp<[RAX,RDX],[RAX,RDX]>;
392 "idiv{q}\t$src", []>;
389393 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
390 "idiv{q}\t$src", []>, Imp<[RAX,RDX],[RAX,RDX]>;
394 "idiv{q}\t$src", []>;
395 }
391396
392397 // Unary instructions
393398 let CodeSize = 2 in {
430435
431436 // Shift instructions
432437 let isTwoAddress = 1 in {
438 let Uses = [CL] in
433439 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
434440 "shl{q}\t{%cl, $dst|$dst, %CL}",
435 [(set GR64:$dst, (shl GR64:$src, CL))]>,
436 Imp<[CL],[]>;
441 [(set GR64:$dst, (shl GR64:$src, CL))]>;
437442 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
438443 "shl{q}\t{$src2, $dst|$dst, $src2}",
439444 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
441446 "shl{q}\t$dst", []>;
442447 } // isTwoAddress
443448
449 let Uses = [CL] in
444450 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
445451 "shl{q}\t{%cl, $dst|$dst, %CL}",
446 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>,
447 Imp<[CL],[]>;
452 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
448453 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
449454 "shl{q}\t{$src, $dst|$dst, $src}",
450455 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
453458 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
454459
455460 let isTwoAddress = 1 in {
461 let Uses = [CL] in
456462 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
457463 "shr{q}\t{%cl, $dst|$dst, %CL}",
458 [(set GR64:$dst, (srl GR64:$src, CL))]>,
459 Imp<[CL],[]>;
464 [(set GR64:$dst, (srl GR64:$src, CL))]>;
460465 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
461466 "shr{q}\t{$src2, $dst|$dst, $src2}",
462467 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
465470 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
466471 } // isTwoAddress
467472
473 let Uses = [CL] in
468474 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
469475 "shr{q}\t{%cl, $dst|$dst, %CL}",
470 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>,
471 Imp<[CL],[]>;
476 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
472477 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
473478 "shr{q}\t{$src, $dst|$dst, $src}",
474479 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
477482 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
478483
479484 let isTwoAddress = 1 in {
485 let Uses = [CL] in
480486 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
481487 "sar{q}\t{%cl, $dst|$dst, %CL}",
482 [(set GR64:$dst, (sra GR64:$src, CL))]>, Imp<[CL],[]>;
488 [(set GR64:$dst, (sra GR64:$src, CL))]>;
483489 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
484490 "sar{q}\t{$src2, $dst|$dst, $src2}",
485491 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
488494 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
489495 } // isTwoAddress
490496
497 let Uses = [CL] in
491498 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
492499 "sar{q}\t{%cl, $dst|$dst, %CL}",
493 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>,
494 Imp<[CL],[]>;
500 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
495501 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
496502 "sar{q}\t{$src, $dst|$dst, $src}",
497503 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
501507
502508 // Rotate instructions
503509 let isTwoAddress = 1 in {
510 let Uses = [CL] in
504511 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
505512 "rol{q}\t{%cl, $dst|$dst, %CL}",
506 [(set GR64:$dst, (rotl GR64:$src, CL))]>, Imp<[CL],[]>;
513 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
507514 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
508515 "rol{q}\t{$src2, $dst|$dst, $src2}",
509516 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
512519 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
513520 } // isTwoAddress
514521
522 let Uses = [CL] in
515523 def ROL64mCL : I<0xD3, MRM0m, (outs), (ins i64mem:$dst),
516524 "rol{q}\t{%cl, $dst|$dst, %CL}",
517 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>,
518 Imp<[CL],[]>;
525 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
519526 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
520527 "rol{q}\t{$src, $dst|$dst, $src}",
521528 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
524531 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
525532
526533 let isTwoAddress = 1 in {
534 let Uses = [CL] in
527535 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
528536 "ror{q}\t{%cl, $dst|$dst, %CL}",
529 [(set GR64:$dst, (rotr GR64:$src, CL))]>, Imp<[CL],[]>;
537 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
530538 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
531539 "ror{q}\t{$src2, $dst|$dst, $src2}",
532540 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
535543 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
536544 } // isTwoAddress
537545
546 let Uses = [CL] in
538547 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
539548 "ror{q}\t{%cl, $dst|$dst, %CL}",
540 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>,
541 Imp<[CL],[]>;
549 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
542550 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
543551 "ror{q}\t{$src, $dst|$dst, $src}",
544552 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
548556
549557 // Double shift instructions (generalizations of rotate)
550558 let isTwoAddress = 1 in {
559 let Uses = [CL] in {
551560 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
552 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}", []>,
553 Imp<[CL],[]>, TB;
561 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}", []>, TB;
554562 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
555 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}", []>,
556 Imp<[CL],[]>, TB;
563 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}", []>, TB;
564 }
557565
558566 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
559567 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
569577
570578 // Temporary hack: there is no patterns associated with these instructions
571579 // so we have to tell tblgen that these do not produce results.
580 let Uses = [CL] in {
572581 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
573 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}", []>,
574 Imp<[CL],[]>, TB;
582 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}", []>, TB;
575583 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
576 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}", []>,
577 Imp<[CL],[]>, TB;
584 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}", []>, TB;
585 }
578586 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
579587 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
580588 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,