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Merging r205630: ------------------------------------------------------------------------ r205630 | hfinkel | 2014-04-04 11:15:57 -0400 (Fri, 04 Apr 2014) | 6 lines [PowerPC] Add a full condition code register to make the "cc" clobber work gcc inline asm supports specifying "cc" as a clobber of all condition registers. Add just enough modeling of the full register to make this work. Fixed PR19326. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205908 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 6 years ago
2 changed file(s) with 82 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
143143 def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>;
144144 }
145145
146 // The full condition-code register. This is not modeled fully, but defined
147 // here primarily, for compatibility with gcc, to allow the inline asm "cc"
148 // clobber specification to work.
149 def CC : PPCReg<"cc">, DwarfRegAlias {
150 let Aliases = [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7];
151 }
152
146153 // Link register
147154 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
148155 //let Aliases = [LR] in
233240 def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY)> {
234241 let CopyCost = -1;
235242 }
243
244 def CCRC : RegisterClass<"PPC", [i32], 32, (add CC)> {
245 let isAllocatable = 0;
246 }
247
0 ; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
1 target datalayout = "E-m:e-i64:64-n32:64"
2 target triple = "powerpc64-unknown-linux-gnu"
3
4 define i64 @test1(i64 %a, i64 %b) {
5 entry:
6 %c = icmp eq i64 %a, %b
7 br label %foo
8
9 foo:
10 call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{cr0},~{cr1},~{cr2},~{cr3},~{cr4},~{cr5},~{cr6},~{cr7}" (i64 %a)
11 br i1 %c, label %bar, label %end
12
13 bar:
14 ret i64 %b
15
16 end:
17 ret i64 %a
18
19 ; CHECK-LABEL: @test1
20 ; CHECK: mfcr [[REG1:[0-9]+]]
21 ; CHECK-DAG: cmpld
22 ; CHECK-DAG: mfocrf [[REG2:[0-9]+]],
23 ; CHECK-DAG: stw [[REG1]], 8(1)
24 ; CHECK-DAG: stw [[REG2]], -4(1)
25
26 ; CHECK: sc
27 ; CHECK: lwz [[REG3:[0-9]+]], -4(1)
28 ; CHECK: mtocrf 128, [[REG3]]
29
30 ; CHECK: lwz [[REG4:[0-9]+]], 8(1)
31 ; CHECK-DAG: mtocrf 32, [[REG4]]
32 ; CHECK-DAG: mtocrf 16, [[REG4]]
33 ; CHECK-DAG: mtocrf 8, [[REG4]]
34 ; CHECK: blr
35 }
36
37 define i64 @test2(i64 %a, i64 %b) {
38 entry:
39 %c = icmp eq i64 %a, %b
40 br label %foo
41
42 foo:
43 call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{cc}" (i64 %a)
44 br i1 %c, label %bar, label %end
45
46 bar:
47 ret i64 %b
48
49 end:
50 ret i64 %a
51
52 ; CHECK-LABEL: @test2
53 ; CHECK: mfcr [[REG1:[0-9]+]]
54 ; CHECK-DAG: cmpld
55 ; CHECK-DAG: mfocrf [[REG2:[0-9]+]],
56 ; CHECK-DAG: stw [[REG1]], 8(1)
57 ; CHECK-DAG: stw [[REG2]], -4(1)
58
59 ; CHECK: sc
60 ; CHECK: lwz [[REG3:[0-9]+]], -4(1)
61 ; CHECK: mtocrf 128, [[REG3]]
62
63 ; CHECK: lwz [[REG4:[0-9]+]], 8(1)
64 ; CHECK-DAG: mtocrf 32, [[REG4]]
65 ; CHECK-DAG: mtocrf 16, [[REG4]]
66 ; CHECK-DAG: mtocrf 8, [[REG4]]
67 ; CHECK: blr
68 }
69