llvm.org GIT mirror llvm / 06a4440
[ARM] Do not test for CPUs, use SubtargetFeatures. Also remove 2 flags. This is a follow-up for r273544. The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods. This commit also removes two command-line flags that weren't used in any of the tests: widen-vmovs and swift-partial-update-clearance. The former may be easily replaced with the mattr mechanism, but the latter may not (as it is a subtarget property, and not a proper feature). Differential Revision: http://reviews.llvm.org/D21797 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274620 91177308-0d34-0410-b5e6-96231b3b80d8 Diana Picus 4 years ago
5 changed file(s) with 21 addition(s) and 15 deletion(s). Raw diff Collapse all Expand all
144144 def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg",
145145 "SlowLoadDSubregister", "true",
146146 "Loading into D subregs is slow">;
147 // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.
148 def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs",
149 "DontWidenVMOVS", "true",
150 "Don't widen VMOVS to VMOVD">;
147151
148152 // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
149153 // VFP to NEON, as an execution domain optimization.
611615
612616 // FIXME: A15 has currently the same Schedule model as A9.
613617 def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15,
618 FeatureDontWidenVMOVS,
614619 FeatureHasRetAddrStack,
615620 FeatureMuxedUnits,
616621 FeatureTrustZone,
4949 static cl::opt
5050 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
5151 cl::desc("Enable ARM 2-addr to 3-addr conv"));
52
53 static cl::opt
54 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
55 cl::desc("Widen ARM vmovs to vmovd when possible"));
56
57 static cl::opt
58 SwiftPartialUpdateClearance("swift-partial-update-clearance",
59 cl::Hidden, cl::init(12),
60 cl::desc("Clearance before partial register updates"));
6152
6253 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
6354 struct ARM_MLxEntry {
13041295 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
13051296 // widened to VMOVD. We prefer the VMOVD when possible because it may be
13061297 // changed into a VORR that can go down the NEON pipeline.
1307 if (!WidenVMOVS || !MI.isCopy() || Subtarget.isCortexA15() ||
1308 Subtarget.isFPOnlySP())
1298 if (!MI.isCopy() || Subtarget.dontWidenVMOVS() || Subtarget.isFPOnlySP())
13091299 return false;
13101300
13111301 // Look for a copy between even S-registers. That is where we keep floats
44914481 unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance(
44924482 const MachineInstr &MI, unsigned OpNum,
44934483 const TargetRegisterInfo *TRI) const {
4494 if (!SwiftPartialUpdateClearance ||
4495 !(Subtarget.isSwift() || Subtarget.isCortexA15()))
4484 auto PartialUpdateClearance = Subtarget.getPartialUpdateClearance();
4485 if (!PartialUpdateClearance)
44964486 return 0;
44974487
44984488 assert(TRI && "Need TRI instance");
45444534
45454535 // MI has an unwanted D-register dependency.
45464536 // Avoid defs in the previous N instructrions.
4547 return SwiftPartialUpdateClearance;
4537 return PartialUpdateClearance;
45484538 }
45494539
45504540 // Break a partial register dependency after getPartialRegUpdateClearance
218218 case CortexA15:
219219 MaxInterleaveFactor = 2;
220220 PreISelOperandLatencyAdjustment = 1;
221 PartialUpdateClearance = 12;
221222 break;
222223 case CortexA17:
223224 case CortexA32:
240241 MaxInterleaveFactor = 2;
241242 LdStMultipleTiming = SingleIssuePlusExtras;
242243 PreISelOperandLatencyAdjustment = 1;
244 PartialUpdateClearance = 12;
243245 break;
244246 }
245247 }
258258 /// If true, the AGU and NEON/FPU units are multiplexed.
259259 bool HasMuxedUnits = false;
260260
261 /// If true, VMOVS will never be widened to VMOVD
262 bool DontWidenVMOVS = false;
263
261264 /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
262265 bool UseNEONForFPMovs = false;
263266
300303 std::string CPUString;
301304
302305 unsigned MaxInterleaveFactor = 1;
306
307 /// Clearance before partial register updates (in number of instructions)
308 unsigned PartialUpdateClearance = 0;
303309
304310 /// What kind of timing do load multiple/store multiple have (double issue,
305311 /// single issue etc).
447453 bool hasSlowOddRegister() const { return SlowOddRegister; }
448454 bool hasSlowLoadDSubregister() const { return SlowLoadDSubregister; }
449455 bool hasMuxedUnits() const { return HasMuxedUnits; }
456 bool dontWidenVMOVS() const { return DontWidenVMOVS; }
450457 bool useNEONForFPMovs() const { return UseNEONForFPMovs; }
451458 bool checkVLDnAccessAlignment() const { return CheckVLDnAlign; }
452459 bool nonpipelinedVFP() const { return NonpipelinedVFP; }
590597
591598 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
592599
600 unsigned getPartialUpdateClearance() const { return PartialUpdateClearance; }
601
593602 ARMLdStMultipleTiming getLdStMultipleTiming() const {
594603 return LdStMultipleTiming;
595604 }
None ; RUN: llc < %s -widen-vmovs -mcpu=cortex-a8 -verify-machineinstrs -disable-block-placement | FileCheck %s
0 ; RUN: llc < %s -mcpu=cortex-a8 -verify-machineinstrs -disable-block-placement | FileCheck %s
11 target triple = "thumbv7-apple-ios"
22
33 ; The 1.0e+10 constant is loaded from the constant pool and kept in a register.