llvm.org GIT mirror llvm / 06886aa
Move the constant-folding support for FP_ROUND in SelectionDAG from the one-operand version of getNode() to the two-operand version, since it became a two-operand node at sound point. Zap a testcase that this allows us to completely fold away. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154447 91177308-0d34-0410-b5e6-96231b3b80d8 Owen Anderson 8 years ago
2 changed file(s) with 12 addition(s) and 19 deletion(s). Raw diff Collapse all Expand all
24272427 case ISD::FABS:
24282428 V.clearSign();
24292429 return getConstantFP(V, VT);
2430 case ISD::FP_ROUND:
24312430 case ISD::FP_EXTEND: {
24322431 bool ignored;
24332432 // This can return overflow, underflow, or inexact; we don't care.
29922991 return getConstantFP(V1, VT);
29932992 default: break;
29942993 }
2994 }
2995
2996 if (Opcode == ISD::FP_ROUND) {
2997 APFloat V = N1CFP->getValueAPF(); // make copy
2998 bool ignored;
2999 // This can return overflow, underflow, or inexact; we don't care.
3000 // FIXME need to be more flexible about rounding mode.
3001 (void)V.convert(*EVTToAPFloatSemantics(VT),
3002 APFloat::rmNearestTiesToEven, &ignored);
3003 return getConstantFP(V, VT);
29953004 }
29963005 }
29973006
3939 ret double %1
4040 }
4141
42 ; rdar://9059537
43 define i32 @test4() ssp {
42 ; rdar://9287902
43 define float @test4() nounwind {
4444 entry:
4545 ; SOFT: test4:
46 ; SOFT: vmov.f64 [[REG4:(d[0-9]+)]], #1.000000e+00
47 ; This S-reg must be the first sub-reg of the last D-reg on vbsl.
48 ; SOFT: vcvt.f32.f64 {{s1?[02468]}}, [[REG4]]
49 ; SOFT: vshr.u64 [[REG4]], [[REG4]], #32
50 ; SOFT: vmov.i32 [[REG5:(d[0-9]+)]], #0x80000000
51 ; SOFT: vbsl [[REG5]], [[REG4]], {{d[0-9]+}}
52 %call80 = tail call double @copysign(double 1.000000e+00, double undef)
53 %conv81 = fptrunc double %call80 to float
54 %tmp88 = bitcast float %conv81 to i32
55 ret i32 %tmp88
56 }
57
58 ; rdar://9287902
59 define float @test5() nounwind {
60 entry:
61 ; SOFT: test5:
6246 ; SOFT: vmov [[REG7:(d[0-9]+)]], r0, r1
6347 ; SOFT: vmov.i32 [[REG6:(d[0-9]+)]], #0x80000000
6448 ; SOFT: vshr.u64 [[REG7]], [[REG7]], #32