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[SystemZ] Implement conditional returns Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265689 91177308-0d34-0410-b5e6-96231b3b80d8 Ulrich Weigand 4 years ago
79 changed file(s) with 1094 addition(s) and 884 deletion(s). Raw diff Collapse all Expand all
106106 switch (MI->getOpcode()) {
107107 case SystemZ::Return:
108108 LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R14D);
109 break;
110
111 case SystemZ::CondReturn:
112 LoweredMI = MCInstBuilder(SystemZ::BCR)
113 .addImm(MI->getOperand(0).getImm())
114 .addImm(MI->getOperand(1).getImm())
115 .addReg(SystemZ::R14D);
116 break;
117
118 case SystemZ::CRBReturn:
119 LoweredMI = MCInstBuilder(SystemZ::CRB)
120 .addReg(MI->getOperand(0).getReg())
121 .addReg(MI->getOperand(1).getReg())
122 .addImm(MI->getOperand(2).getImm())
123 .addReg(SystemZ::R14D)
124 .addImm(0);
125 break;
126
127 case SystemZ::CGRBReturn:
128 LoweredMI = MCInstBuilder(SystemZ::CGRB)
129 .addReg(MI->getOperand(0).getReg())
130 .addReg(MI->getOperand(1).getReg())
131 .addImm(MI->getOperand(2).getImm())
132 .addReg(SystemZ::R14D)
133 .addImm(0);
134 break;
135
136 case SystemZ::CIBReturn:
137 LoweredMI = MCInstBuilder(SystemZ::CIB)
138 .addReg(MI->getOperand(0).getReg())
139 .addImm(MI->getOperand(1).getImm())
140 .addImm(MI->getOperand(2).getImm())
141 .addReg(SystemZ::R14D)
142 .addImm(0);
143 break;
144
145 case SystemZ::CGIBReturn:
146 LoweredMI = MCInstBuilder(SystemZ::CGIB)
147 .addReg(MI->getOperand(0).getReg())
148 .addImm(MI->getOperand(1).getImm())
149 .addImm(MI->getOperand(2).getImm())
150 .addReg(SystemZ::R14D)
151 .addImm(0);
152 break;
153
154 case SystemZ::CLRBReturn:
155 LoweredMI = MCInstBuilder(SystemZ::CLRB)
156 .addReg(MI->getOperand(0).getReg())
157 .addReg(MI->getOperand(1).getReg())
158 .addImm(MI->getOperand(2).getImm())
159 .addReg(SystemZ::R14D)
160 .addImm(0);
161 break;
162
163 case SystemZ::CLGRBReturn:
164 LoweredMI = MCInstBuilder(SystemZ::CLGRB)
165 .addReg(MI->getOperand(0).getReg())
166 .addReg(MI->getOperand(1).getReg())
167 .addImm(MI->getOperand(2).getImm())
168 .addReg(SystemZ::R14D)
169 .addImm(0);
170 break;
171
172 case SystemZ::CLIBReturn:
173 LoweredMI = MCInstBuilder(SystemZ::CLIB)
174 .addReg(MI->getOperand(0).getReg())
175 .addImm(MI->getOperand(1).getImm())
176 .addImm(MI->getOperand(2).getImm())
177 .addReg(SystemZ::R14D)
178 .addImm(0);
179 break;
180
181 case SystemZ::CLGIBReturn:
182 LoweredMI = MCInstBuilder(SystemZ::CLGIB)
183 .addReg(MI->getOperand(0).getReg())
184 .addImm(MI->getOperand(1).getImm())
185 .addImm(MI->getOperand(2).getImm())
186 .addReg(SystemZ::R14D)
187 .addImm(0);
109188 break;
110189
111190 case SystemZ::CallBRASL:
379379 bool SystemZElimCompare::
380380 fuseCompareAndBranch(MachineInstr *Compare,
381381 SmallVectorImpl &CCUsers) {
382 // See whether we have a single branch with which to fuse.
383 if (CCUsers.size() != 1)
384 return false;
385 MachineInstr *Branch = CCUsers[0];
386 SystemZII::CompareAndBranchType Type;
387 switch (Branch->getOpcode()) {
388 case SystemZ::BRC:
389 Type = SystemZII::CompareAndBranch;
390 break;
391 case SystemZ::CondReturn:
392 Type = SystemZII::CompareAndReturn;
393 break;
394 default:
395 return false;
396 }
397
382398 // See whether we have a comparison that can be fused.
383399 unsigned FusedOpcode = TII->getCompareAndBranch(Compare->getOpcode(),
384 Compare);
400 Type, Compare);
385401 if (!FusedOpcode)
386 return false;
387
388 // See whether we have a single branch with which to fuse.
389 if (CCUsers.size() != 1)
390 return false;
391 MachineInstr *Branch = CCUsers[0];
392 if (Branch->getOpcode() != SystemZ::BRC)
393402 return false;
394403
395404 // Make sure that the operands are available at the branch.
402411 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI)))
403412 return false;
404413
405 // Read the branch mask and target.
414 // Read the branch mask and target (if applicable).
406415 MachineOperand CCMask(MBBI->getOperand(1));
407 MachineOperand Target(MBBI->getOperand(2));
408416 assert((CCMask.getImm() & ~SystemZ::CCMASK_ICMP) == 0 &&
409417 "Invalid condition-code mask for integer comparison");
418 // This is only valid for CompareAndBranch.
419 MachineOperand Target(MBBI->getOperand(
420 Type == SystemZII::CompareAndBranch ? 2 : 0));
410421
411422 // Clear out all current operands.
412423 int CCUse = MBBI->findRegisterUseOperandIdx(SystemZ::CC, false, TRI);
413 assert(CCUse >= 0 && "BRC must use CC");
424 assert(CCUse >= 0 && "BRC/BCR must use CC");
414425 Branch->RemoveOperand(CCUse);
415 Branch->RemoveOperand(2);
426 if (Type == SystemZII::CompareAndBranch)
427 Branch->RemoveOperand(2);
416428 Branch->RemoveOperand(1);
417429 Branch->RemoveOperand(0);
418430
419431 // Rebuild Branch as a fused compare and branch.
420432 Branch->setDesc(TII->get(FusedOpcode));
421 MachineInstrBuilder(*Branch->getParent()->getParent(), Branch)
422 .addOperand(Compare->getOperand(0))
423 .addOperand(Compare->getOperand(1))
424 .addOperand(CCMask)
425 .addOperand(Target)
426 .addReg(SystemZ::CC, RegState::ImplicitDefine);
433 MachineInstrBuilder MIB(*Branch->getParent()->getParent(), Branch);
434 MIB.addOperand(Compare->getOperand(0))
435 .addOperand(Compare->getOperand(1))
436 .addOperand(CCMask);
437
438 if (Type == SystemZII::CompareAndBranch) {
439 // Only conditional branches define CC, as they may be converted back
440 // to a non-fused branch because of a long displacement. Conditional
441 // returns don't have that problem.
442 MIB.addOperand(Target)
443 .addReg(SystemZ::CC, RegState::ImplicitDefine);
444 }
427445
428446 // Clear any intervening kills of SrcReg and SrcReg2.
429447 MBBI = Compare;
507507
508508 bool SystemZInstrInfo::isPredicable(MachineInstr &MI) const {
509509 unsigned Opcode = MI.getOpcode();
510 return STI.hasLoadStoreOnCond() && getConditionalMove(Opcode);
510 if (STI.hasLoadStoreOnCond() && getConditionalMove(Opcode))
511 return true;
512 if (Opcode == SystemZ::Return)
513 return true;
514 return false;
511515 }
512516
513517 bool SystemZInstrInfo::
514518 isProfitableToIfCvt(MachineBasicBlock &MBB,
515519 unsigned NumCycles, unsigned ExtraPredCycles,
516520 BranchProbability Probability) const {
521 // Avoid using conditional returns at the end of a loop (since then
522 // we'd need to emit an unconditional branch to the beginning anyway,
523 // making the loop body longer). This doesn't apply for low-probability
524 // loops (eg. compare-and-swap retry), so just decide based on branch
525 // probability instead of looping structure.
526 if (MBB.succ_empty() && Probability < BranchProbability(1, 8))
527 return false;
517528 // For now only convert single instructions.
518529 return NumCycles == 1;
519530 }
526537 BranchProbability Probability) const {
527538 // For now avoid converting mutually-exclusive cases.
528539 return false;
540 }
541
542 bool SystemZInstrInfo::
543 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
544 BranchProbability Probability) const {
545 // For now only duplicate single instructions.
546 return NumCycles == 1;
529547 }
530548
531549 bool SystemZInstrInfo::PredicateInstruction(
544562 .addReg(SystemZ::CC, RegState::Implicit);
545563 return true;
546564 }
565 }
566 if (Opcode == SystemZ::Return) {
567 MI.setDesc(get(SystemZ::CondReturn));
568 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
569 .addImm(CCValid).addImm(CCMask)
570 .addReg(SystemZ::CC, RegState::Implicit);
571 return true;
547572 }
548573 return false;
549574 }
12521277 }
12531278
12541279 unsigned SystemZInstrInfo::getCompareAndBranch(unsigned Opcode,
1280 SystemZII::CompareAndBranchType Type,
12551281 const MachineInstr *MI) const {
12561282 switch (Opcode) {
1257 case SystemZ::CR:
1258 return SystemZ::CRJ;
1259 case SystemZ::CGR:
1260 return SystemZ::CGRJ;
12611283 case SystemZ::CHI:
1262 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CIJ : 0;
12631284 case SystemZ::CGHI:
1264 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CGIJ : 0;
1265 case SystemZ::CLR:
1266 return SystemZ::CLRJ;
1267 case SystemZ::CLGR:
1268 return SystemZ::CLGRJ;
1285 if (!(MI && isInt<8>(MI->getOperand(1).getImm())))
1286 return 0;
1287 break;
12691288 case SystemZ::CLFI:
1270 return MI && isUInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CLIJ : 0;
12711289 case SystemZ::CLGFI:
1272 return MI && isUInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CLGIJ : 0;
1290 if (!(MI && isUInt<8>(MI->getOperand(1).getImm())))
1291 return 0;
1292 }
1293 switch (Type) {
1294 case SystemZII::CompareAndBranch:
1295 switch (Opcode) {
1296 case SystemZ::CR:
1297 return SystemZ::CRJ;
1298 case SystemZ::CGR:
1299 return SystemZ::CGRJ;
1300 case SystemZ::CHI:
1301 return SystemZ::CIJ;
1302 case SystemZ::CGHI:
1303 return SystemZ::CGIJ;
1304 case SystemZ::CLR:
1305 return SystemZ::CLRJ;
1306 case SystemZ::CLGR:
1307 return SystemZ::CLGRJ;
1308 case SystemZ::CLFI:
1309 return SystemZ::CLIJ;
1310 case SystemZ::CLGFI:
1311 return SystemZ::CLGIJ;
1312 default:
1313 return 0;
1314 }
1315 case SystemZII::CompareAndReturn:
1316 switch (Opcode) {
1317 case SystemZ::CR:
1318 return SystemZ::CRBReturn;
1319 case SystemZ::CGR:
1320 return SystemZ::CGRBReturn;
1321 case SystemZ::CHI:
1322 return SystemZ::CIBReturn;
1323 case SystemZ::CGHI:
1324 return SystemZ::CGIBReturn;
1325 case SystemZ::CLR:
1326 return SystemZ::CLRBReturn;
1327 case SystemZ::CLGR:
1328 return SystemZ::CLGRBReturn;
1329 case SystemZ::CLFI:
1330 return SystemZ::CLIBReturn;
1331 case SystemZ::CLGFI:
1332 return SystemZ::CLGIBReturn;
1333 default:
1334 return 0;
1335 }
12731336 default:
12741337 return 0;
12751338 }
109109 Branch(BranchType type, unsigned ccValid, unsigned ccMask,
110110 const MachineOperand *target)
111111 : Type(type), CCValid(ccValid), CCMask(ccMask), Target(target) {}
112 };
113 // Kinds of branch in compare-and-branch instructions. Together with type
114 // of the converted compare, this identifies the compare-and-branch
115 // instruction.
116 enum CompareAndBranchType {
117 // Relative branch - CRJ etc.
118 CompareAndBranch,
119
120 // Indirect branch, used for return - CRBReturn etc.
121 CompareAndReturn
112122 };
113123 } // end namespace SystemZII
114124
164174 MachineBasicBlock &FMBB,
165175 unsigned NumCyclesF, unsigned ExtraPredCyclesF,
166176 BranchProbability Probability) const override;
177 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
178 BranchProbability Probability) const override;
167179 bool PredicateInstruction(MachineInstr &MI,
168180 ArrayRef Pred) const override;
169181 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
232244 // BRANCH exists, return the opcode for the latter, otherwise return 0.
233245 // MI, if nonnull, is the compare instruction.
234246 unsigned getCompareAndBranch(unsigned Opcode,
247 SystemZII::CompareAndBranchType Type,
235248 const MachineInstr *MI = nullptr) const;
236249
237250 // Emit code before MBBI in MI to move immediate value Value into
3434 // A return instruction (br %r14).
3535 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
3636 def Return : Alias<2, (outs), (ins), [(z_retflag)]>;
37
38 // A conditional return instruction (bcr , %r14).
39 let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in
40 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>;
41
42 // Fused compare and conditional returns.
43 let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, Uses = [CC] in {
44 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>;
45 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>;
46 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>;
47 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>;
48 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>;
49 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>;
50 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>;
51 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>;
52 }
3753
3854 // Unconditional branches. R1 is the condition-code mask (all 1s).
3955 let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in {
6177 [(z_br_ccmask cond4:$valid, cond4:$R1, bb:$I2)]>;
6278 def BRCL : InstRIL<0xC04, (outs), (ins cond4:$valid, cond4:$R1,
6379 brtarget32:$I2), "jg$R1\t$I2", []>;
80 let isIndirectBranch = 1 in
81 def BCR : InstRR<0x07, (outs), (ins cond4:$valid, cond4:$R1, GR64:$R2),
82 "b${R1}r\t$R2", []>;
6483 }
6584 def AsmBRC : InstRI<0xA74, (outs), (ins imm32zx4:$R1, brtarget16:$I2),
6685 "brc\t$R1, $I2", []>;
6786 def AsmBRCL : InstRIL<0xC04, (outs), (ins imm32zx4:$R1, brtarget32:$I2),
6887 "brcl\t$R1, $I2", []>;
69 def AsmBC : InstRX<0x47, (outs), (ins imm32zx4:$R1, bdxaddr12only:$XBD2),
70 "bc\t$R1, $XBD2", []>;
71 def AsmBCR : InstRR<0x07, (outs), (ins imm32zx4:$R1, GR64:$R2),
72 "bcr\t$R1, $R2", []>;
88 let isIndirectBranch = 1 in {
89 def AsmBC : InstRX<0x47, (outs), (ins imm32zx4:$R1, bdxaddr12only:$XBD2),
90 "bc\t$R1, $XBD2", []>;
91 def AsmBCR : InstRR<0x07, (outs), (ins imm32zx4:$R1, GR64:$R2),
92 "bcr\t$R1, $R2", []>;
93 }
7394 }
7495
7596 def AsmNop : InstAlias<"nop\t$XBD", (AsmBC 0, bdxaddr12only:$XBD), 0>;
109130 def LGIJ : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2, ccmask:$M3,
110131 brtarget16:$RI4),
111132 "clgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
112 def RB : InstRRS<0xECF6, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
113 bdaddr12only:$BD4),
114 "crb"##pos1##"\t$R1, $R2, "##pos2##"$BD4", []>;
115 def GRB : InstRRS<0xECE4, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
116 bdaddr12only:$BD4),
117 "cgrb"##pos1##"\t$R1, $R2, "##pos2##"$BD4", []>;
118 def IB : InstRIS<0xECFE, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3,
119 bdaddr12only:$BD4),
120 "cib"##pos1##"\t$R1, $I2, "##pos2##"$BD4", []>;
121 def GIB : InstRIS<0xECFC, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3,
122 bdaddr12only:$BD4),
123 "cgib"##pos1##"\t$R1, $I2, "##pos2##"$BD4", []>;
124 def LRB : InstRRS<0xECF7, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
125 bdaddr12only:$BD4),
126 "clrb"##pos1##"\t$R1, $R2, "##pos2##"$BD4", []>;
127 def LGRB : InstRRS<0xECE5, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
128 bdaddr12only:$BD4),
129 "clgrb"##pos1##"\t$R1, $R2, "##pos2##"$BD4", []>;
130 def LIB : InstRIS<0xECFF, (outs), (ins GR32:$R1, imm32zx8:$I2, ccmask:$M3,
131 bdaddr12only:$BD4),
132 "clib"##pos1##"\t$R1, $I2, "##pos2##"$BD4", []>;
133 def LGIB : InstRIS<0xECFD, (outs), (ins GR64:$R1, imm64zx8:$I2, ccmask:$M3,
134 bdaddr12only:$BD4),
135 "clgib"##pos1##"\t$R1, $I2, "##pos2##"$BD4", []>;
133 let isIndirectBranch = 1 in {
134 def RB : InstRRS<0xECF6, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
135 bdaddr12only:$BD4),
136 "crb"##pos1##"\t$R1, $R2, "##pos2##"$BD4", []>;
137 def GRB : InstRRS<0xECE4, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
138 bdaddr12only:$BD4),
139 "cgrb"##pos1##"\t$R1, $R2, "##pos2##"$BD4", []>;
140 def IB : InstRIS<0xECFE, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3,
141 bdaddr12only:$BD4),
142 "cib"##pos1##"\t$R1, $I2, "##pos2##"$BD4", []>;
143 def GIB : InstRIS<0xECFC, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3,
144 bdaddr12only:$BD4),
145 "cgib"##pos1##"\t$R1, $I2, "##pos2##"$BD4", []>;
146 def LRB : InstRRS<0xECF7, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
147 bdaddr12only:$BD4),
148 "clrb"##pos1##"\t$R1, $R2, "##pos2##"$BD4", []>;
149 def LGRB : InstRRS<0xECE5, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
150 bdaddr12only:$BD4),
151 "clgrb"##pos1##"\t$R1, $R2, "##pos2##"$BD4", []>;
152 def LIB : InstRIS<0xECFF, (outs), (ins GR32:$R1, imm32zx8:$I2, ccmask:$M3,
153 bdaddr12only:$BD4),
154 "clib"##pos1##"\t$R1, $I2, "##pos2##"$BD4", []>;
155 def LGIB : InstRIS<0xECFD, (outs), (ins GR64:$R1, imm64zx8:$I2, ccmask:$M3,
156 bdaddr12only:$BD4),
157 "clgib"##pos1##"\t$R1, $I2, "##pos2##"$BD4", []>;
158 }
136159 }
137160 }
138161 let isCodeGenOnly = 1 in
204227 def CLGIJ : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2,
205228 brtarget16:$RI4),
206229 "clgij"##name##"\t$R1, $I2, $RI4", []>;
207 def CRB : InstRRS<0xECF6, (outs), (ins GR32:$R1, GR32:$R2,
208 bdaddr12only:$BD4),
209 "crb"##name##"\t$R1, $R2, $BD4", []>;
210 def CGRB : InstRRS<0xECE4, (outs), (ins GR64:$R1, GR64:$R2,
211 bdaddr12only:$BD4),
212 "cgrb"##name##"\t$R1, $R2, $BD4", []>;
213 def CIB : InstRIS<0xECFE, (outs), (ins GR32:$R1, imm32sx8:$I2,
214 bdaddr12only:$BD4),
215 "cib"##name##"\t$R1, $I2, $BD4", []>;
216 def CGIB : InstRIS<0xECFC, (outs), (ins GR64:$R1, imm64sx8:$I2,
217 bdaddr12only:$BD4),
218 "cgib"##name##"\t$R1, $I2, $BD4", []>;
219 def CLRB : InstRRS<0xECF7, (outs), (ins GR32:$R1, GR32:$R2,
220 bdaddr12only:$BD4),
221 "clrb"##name##"\t$R1, $R2, $BD4", []>;
222 def CLGRB : InstRRS<0xECE5, (outs), (ins GR64:$R1, GR64:$R2,
223 bdaddr12only:$BD4),
224 "clgrb"##name##"\t$R1, $R2, $BD4", []>;
225 def CLIB : InstRIS<0xECFF, (outs), (ins GR32:$R1, imm32zx8:$I2,
226 bdaddr12only:$BD4),
227 "clib"##name##"\t$R1, $I2, $BD4", []>;
228 def CLGIB : InstRIS<0xECFD, (outs), (ins GR64:$R1, imm64zx8:$I2,
229 bdaddr12only:$BD4),
230 "clgib"##name##"\t$R1, $I2, $BD4", []>;
230 let isIndirectBranch = 1 in {
231 def CRB : InstRRS<0xECF6, (outs), (ins GR32:$R1, GR32:$R2,
232 bdaddr12only:$BD4),
233 "crb"##name##"\t$R1, $R2, $BD4", []>;
234 def CGRB : InstRRS<0xECE4, (outs), (ins GR64:$R1, GR64:$R2,
235 bdaddr12only:$BD4),
236 "cgrb"##name##"\t$R1, $R2, $BD4", []>;
237 def CIB : InstRIS<0xECFE, (outs), (ins GR32:$R1, imm32sx8:$I2,
238 bdaddr12only:$BD4),
239 "cib"##name##"\t$R1, $I2, $BD4", []>;
240 def CGIB : InstRIS<0xECFC, (outs), (ins GR64:$R1, imm64sx8:$I2,
241 bdaddr12only:$BD4),
242 "cgib"##name##"\t$R1, $I2, $BD4", []>;
243 def CLRB : InstRRS<0xECF7, (outs), (ins GR32:$R1, GR32:$R2,
244 bdaddr12only:$BD4),
245 "clrb"##name##"\t$R1, $R2, $BD4", []>;
246 def CLGRB : InstRRS<0xECE5, (outs), (ins GR64:$R1, GR64:$R2,
247 bdaddr12only:$BD4),
248 "clgrb"##name##"\t$R1, $R2, $BD4", []>;
249 def CLIB : InstRIS<0xECFF, (outs), (ins GR32:$R1, imm32zx8:$I2,
250 bdaddr12only:$BD4),
251 "clib"##name##"\t$R1, $I2, $BD4", []>;
252 def CLGIB : InstRIS<0xECFD, (outs), (ins GR64:$R1, imm64zx8:$I2,
253 bdaddr12only:$BD4),
254 "clgib"##name##"\t$R1, $I2, $BD4", []>;
255 }
231256 }
232257 }
233258 multiclass IntCondExtendedMnemonic ccmask, string name1, string name2>
124124 }
125125
126126 void SystemZPassConfig::addPreSched2() {
127 if (getOptLevel() != CodeGenOpt::None &&
128 getSystemZTargetMachine().getSubtargetImpl()->hasLoadStoreOnCond())
127 if (getOptLevel() != CodeGenOpt::None)
129128 addPass(&IfConverterID);
130129 }
131130
1111 ; CHECK: crjle %r2, %r4, [[KEEP:\..*]]
1212 ; CHECK: lr [[NEW]], %r4
1313 ; CHECK: cs %r2, [[NEW]], 0(%r3)
14 ; CHECK: jl [[LOOP]]
15 ; CHECK: br %r14
14 ; CHECK: ber %r14
15 ; CHECK: j [[LOOP]]
1616 %res = atomicrmw min i32 *%src, i32 %b seq_cst
1717 ret i32 %res
1818 }
2626 ; CHECK: crjhe %r2, %r4, [[KEEP:\..*]]
2727 ; CHECK: lr [[NEW]], %r4
2828 ; CHECK: cs %r2, [[NEW]], 0(%r3)
29 ; CHECK: jl [[LOOP]]
30 ; CHECK: br %r14
29 ; CHECK: ber %r14
30 ; CHECK: j [[LOOP]]
3131 %res = atomicrmw max i32 *%src, i32 %b seq_cst
3232 ret i32 %res
3333 }
4141 ; CHECK: clrjle %r2, %r4, [[KEEP:\..*]]
4242 ; CHECK: lr [[NEW]], %r4
4343 ; CHECK: cs %r2, [[NEW]], 0(%r3)
44 ; CHECK: jl [[LOOP]]
45 ; CHECK: br %r14
44 ; CHECK: ber %r14
45 ; CHECK: j [[LOOP]]
4646 %res = atomicrmw umin i32 *%src, i32 %b seq_cst
4747 ret i32 %res
4848 }
5656 ; CHECK: clrjhe %r2, %r4, [[KEEP:\..*]]
5757 ; CHECK: lr [[NEW]], %r4
5858 ; CHECK: cs %r2, [[NEW]], 0(%r3)
59 ; CHECK: jl [[LOOP]]
60 ; CHECK: br %r14
59 ; CHECK: ber %r14
60 ; CHECK: j [[LOOP]]
6161 %res = atomicrmw umax i32 *%src, i32 %b seq_cst
6262 ret i32 %res
6363 }
6767 ; CHECK-LABEL: f5:
6868 ; CHECK: l %r2, 4092(%r3)
6969 ; CHECK: cs %r2, {{%r[0-9]+}}, 4092(%r3)
70 ; CHECK: br %r14
70 ; CHECK: ber %r14
7171 %ptr = getelementptr i32, i32 *%src, i64 1023
7272 %res = atomicrmw min i32 *%ptr, i32 %b seq_cst
7373 ret i32 %res
7878 ; CHECK-LABEL: f6:
7979 ; CHECK: ly %r2, 4096(%r3)
8080 ; CHECK: csy %r2, {{%r[0-9]+}}, 4096(%r3)
81 ; CHECK: br %r14
81 ; CHECK: ber %r14
8282 %ptr = getelementptr i32, i32 *%src, i64 1024
8383 %res = atomicrmw min i32 *%ptr, i32 %b seq_cst
8484 ret i32 %res
8989 ; CHECK-LABEL: f7:
9090 ; CHECK: ly %r2, 524284(%r3)
9191 ; CHECK: csy %r2, {{%r[0-9]+}}, 524284(%r3)
92 ; CHECK: br %r14
92 ; CHECK: ber %r14
9393 %ptr = getelementptr i32, i32 *%src, i64 131071
9494 %res = atomicrmw min i32 *%ptr, i32 %b seq_cst
9595 ret i32 %res
101101 ; CHECK: agfi %r3, 524288
102102 ; CHECK: l %r2, 0(%r3)
103103 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
104 ; CHECK: br %r14
104 ; CHECK: ber %r14
105105 %ptr = getelementptr i32, i32 *%src, i64 131072
106106 %res = atomicrmw min i32 *%ptr, i32 %b seq_cst
107107 ret i32 %res
112112 ; CHECK-LABEL: f9:
113113 ; CHECK: ly %r2, -4(%r3)
114114 ; CHECK: csy %r2, {{%r[0-9]+}}, -4(%r3)
115 ; CHECK: br %r14
115 ; CHECK: ber %r14
116116 %ptr = getelementptr i32, i32 *%src, i64 -1
117117 %res = atomicrmw min i32 *%ptr, i32 %b seq_cst
118118 ret i32 %res
123123 ; CHECK-LABEL: f10:
124124 ; CHECK: ly %r2, -524288(%r3)
125125 ; CHECK: csy %r2, {{%r[0-9]+}}, -524288(%r3)
126 ; CHECK: br %r14
126 ; CHECK: ber %r14
127127 %ptr = getelementptr i32, i32 *%src, i64 -131072
128128 %res = atomicrmw min i32 *%ptr, i32 %b seq_cst
129129 ret i32 %res
135135 ; CHECK: agfi %r3, -524292
136136 ; CHECK: l %r2, 0(%r3)
137137 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
138 ; CHECK: br %r14
138 ; CHECK: ber %r14
139139 %ptr = getelementptr i32, i32 *%src, i64 -131073
140140 %res = atomicrmw min i32 *%ptr, i32 %b seq_cst
141141 ret i32 %res
147147 ; CHECK: agr %r3, %r4
148148 ; CHECK: l %r2, 0(%r3)
149149 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
150 ; CHECK: br %r14
150 ; CHECK: ber %r14
151151 %add = add i64 %base, %index
152152 %ptr = inttoptr i64 %add to i32 *
153153 %res = atomicrmw min i32 *%ptr, i32 %b seq_cst
164164 ; CHECK: crjle %r2, [[LIMIT]], [[KEEP:\..*]]
165165 ; CHECK: lhi [[NEW]], 42
166166 ; CHECK: cs %r2, [[NEW]], 0(%r3)
167 ; CHECK: jl [[LOOP]]
168 ; CHECK: br %r14
167 ; CHECK: ber %r14
168 ; CHECK: j [[LOOP]]
169169 %res = atomicrmw min i32 *%ptr, i32 42 seq_cst
170170 ret i32 %res
171171 }
1111 ; CHECK: cgrjle %r2, %r4, [[KEEP:\..*]]
1212 ; CHECK: lgr [[NEW]], %r4
1313 ; CHECK: csg %r2, [[NEW]], 0(%r3)
14 ; CHECK: jl [[LOOP]]
15 ; CHECK: br %r14
14 ; CHECK: ber %r14
15 ; CHECK: j [[LOOP]]
1616 %res = atomicrmw min i64 *%src, i64 %b seq_cst
1717 ret i64 %res
1818 }
2626 ; CHECK: cgrjhe %r2, %r4, [[KEEP:\..*]]
2727 ; CHECK: lgr [[NEW]], %r4
2828 ; CHECK: csg %r2, [[NEW]], 0(%r3)
29 ; CHECK: jl [[LOOP]]
30 ; CHECK: br %r14
29 ; CHECK: ber %r14
30 ; CHECK: j [[LOOP]]
3131 %res = atomicrmw max i64 *%src, i64 %b seq_cst
3232 ret i64 %res
3333 }
4141 ; CHECK: clgrjle %r2, %r4, [[KEEP:\..*]]
4242 ; CHECK: lgr [[NEW]], %r4
4343 ; CHECK: csg %r2, [[NEW]], 0(%r3)
44 ; CHECK: jl [[LOOP]]
45 ; CHECK: br %r14
44 ; CHECK: ber %r14
45 ; CHECK: j [[LOOP]]
4646 %res = atomicrmw umin i64 *%src, i64 %b seq_cst
4747 ret i64 %res
4848 }
5656 ; CHECK: clgrjhe %r2, %r4, [[KEEP:\..*]]
5757 ; CHECK: lgr [[NEW]], %r4
5858 ; CHECK: csg %r2, [[NEW]], 0(%r3)
59 ; CHECK: jl [[LOOP]]
60 ; CHECK: br %r14
59 ; CHECK: ber %r14
60 ; CHECK: j [[LOOP]]
6161 %res = atomicrmw umax i64 *%src, i64 %b seq_cst
6262 ret i64 %res
6363 }
6767 ; CHECK-LABEL: f5:
6868 ; CHECK: lg %r2, 524280(%r3)
6969 ; CHECK: csg %r2, {{%r[0-9]+}}, 524280(%r3)
70 ; CHECK: br %r14
70 ; CHECK: ber %r14
7171 %ptr = getelementptr i64, i64 *%src, i64 65535
7272 %res = atomicrmw min i64 *%ptr, i64 %b seq_cst
7373 ret i64 %res
7979 ; CHECK: agfi %r3, 524288
8080 ; CHECK: lg %r2, 0(%r3)
8181 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
82 ; CHECK: br %r14
82 ; CHECK: ber %r14
8383 %ptr = getelementptr i64, i64 *%src, i64 65536
8484 %res = atomicrmw min i64 *%ptr, i64 %b seq_cst
8585 ret i64 %res
9090 ; CHECK-LABEL: f7:
9191 ; CHECK: lg %r2, -524288(%r3)
9292 ; CHECK: csg %r2, {{%r[0-9]+}}, -524288(%r3)
93 ; CHECK: br %r14
93 ; CHECK: ber %r14
9494 %ptr = getelementptr i64, i64 *%src, i64 -65536
9595 %res = atomicrmw min i64 *%ptr, i64 %b seq_cst
9696 ret i64 %res
102102 ; CHECK: agfi %r3, -524296
103103 ; CHECK: lg %r2, 0(%r3)
104104 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
105 ; CHECK: br %r14
105 ; CHECK: ber %r14
106106 %ptr = getelementptr i64, i64 *%src, i64 -65537
107107 %res = atomicrmw min i64 *%ptr, i64 %b seq_cst
108108 ret i64 %res
114114 ; CHECK: agr %r3, %r4
115115 ; CHECK: lg %r2, 0(%r3)
116116 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
117 ; CHECK: br %r14
117 ; CHECK: ber %r14
118118 %add = add i64 %base, %index
119119 %ptr = inttoptr i64 %add to i64 *
120120 %res = atomicrmw min i64 *%ptr, i64 %b seq_cst
131131 ; CHECK: cgrjle %r2, [[LIMIT]], [[KEEP:\..*]]
132132 ; CHECK: lghi [[NEW]], 42
133133 ; CHECK: csg %r2, [[NEW]], 0(%r3)
134 ; CHECK: jl [[LOOP]]
135 ; CHECK: br %r14
134 ; CHECK: ber %r14
135 ; CHECK: j [[LOOP]]
136136 %res = atomicrmw min i64 *%ptr, i64 42 seq_cst
137137 ret i64 %res
138138 }
44 define i32 @f1(i32 %x, i32 %y, i32 %op) {
55 ; CHECK-LABEL: f1:
66 ; CHECK: ahi %r4, -1
7 ; CHECK: clijh %r4, 5,
7 ; CHECK: clibh %r4, 5, 0(%r14)
88 ; CHECK: llgfr [[OP64:%r[0-5]]], %r4
99 ; CHECK: sllg [[INDEX:%r[1-5]]], [[OP64]], 3
1010 ; CHECK: larl [[BASE:%r[1-5]]]
88 define void @f1(i8 *%ptr, i8 %alt, i32 %limit) {
99 ; CHECK-LABEL: f1:
1010 ; CHECK-NOT: %r2
11 ; CHECK: jl [[LABEL:[^ ]*]]
12 ; CHECK-NOT: %r2
13 ; CHECK: stc %r3, 0(%r2)
14 ; CHECK: [[LABEL]]:
11 ; CHECK: blr %r14
12 ; CHECK-NOT: %r2
13 ; CHECK: stc %r3, 0(%r2)
1514 ; CHECK: br %r14
1615 %cond = icmp ult i32 %limit, 420
1716 %orig = load i8 , i8 *%ptr
2423 define void @f2(i8 *%ptr, i8 %alt, i32 %limit) {
2524 ; CHECK-LABEL: f2:
2625 ; CHECK-NOT: %r2
27 ; CHECK: jhe [[LABEL:[^ ]*]]
28 ; CHECK-NOT: %r2
29 ; CHECK: stc %r3, 0(%r2)
30 ; CHECK: [[LABEL]]:
26 ; CHECK: bher %r14
27 ; CHECK-NOT: %r2
28 ; CHECK: stc %r3, 0(%r2)
3129 ; CHECK: br %r14
3230 %cond = icmp ult i32 %limit, 420
3331 %orig = load i8 , i8 *%ptr
4139 define void @f3(i8 *%ptr, i32 %alt, i32 %limit) {
4240 ; CHECK-LABEL: f3:
4341 ; CHECK-NOT: %r2
44 ; CHECK: jl [[LABEL:[^ ]*]]
45 ; CHECK-NOT: %r2
46 ; CHECK: stc %r3, 0(%r2)
47 ; CHECK: [[LABEL]]:
42 ; CHECK: blr %r14
43 ; CHECK-NOT: %r2
44 ; CHECK: stc %r3, 0(%r2)
4845 ; CHECK: br %r14
4946 %cond = icmp ult i32 %limit, 420
5047 %orig = load i8 , i8 *%ptr
5956 define void @f4(i8 *%ptr, i32 %alt, i32 %limit) {
6057 ; CHECK-LABEL: f4:
6158 ; CHECK-NOT: %r2
62 ; CHECK: jhe [[LABEL:[^ ]*]]
63 ; CHECK-NOT: %r2
64 ; CHECK: stc %r3, 0(%r2)
65 ; CHECK: [[LABEL]]:
59 ; CHECK: bher %r14
60 ; CHECK-NOT: %r2
61 ; CHECK: stc %r3, 0(%r2)
6662 ; CHECK: br %r14
6763 %cond = icmp ult i32 %limit, 420
6864 %orig = load i8 , i8 *%ptr
7874 define void @f5(i8 *%ptr, i32 %alt, i32 %limit) {
7975 ; CHECK-LABEL: f5:
8076 ; CHECK-NOT: %r2
81 ; CHECK: jl [[LABEL:[^ ]*]]
82 ; CHECK-NOT: %r2
83 ; CHECK: stc %r3, 0(%r2)
84 ; CHECK: [[LABEL]]:
77 ; CHECK: blr %r14
78 ; CHECK-NOT: %r2
79 ; CHECK: stc %r3, 0(%r2)
8580 ; CHECK: br %r14
8681 %cond = icmp ult i32 %limit, 420
8782 %orig = load i8 , i8 *%ptr
9691 define void @f6(i8 *%ptr, i32 %alt, i32 %limit) {
9792 ; CHECK-LABEL: f6:
9893 ; CHECK-NOT: %r2
99 ; CHECK: jhe [[LABEL:[^ ]*]]
100 ; CHECK-NOT: %r2
101 ; CHECK: stc %r3, 0(%r2)
102 ; CHECK: [[LABEL]]:
94 ; CHECK: bher %r14
95 ; CHECK-NOT: %r2
96 ; CHECK: stc %r3, 0(%r2)
10397 ; CHECK: br %r14
10498 %cond = icmp ult i32 %limit, 420
10599 %orig = load i8 , i8 *%ptr
115109 define void @f7(i8 *%ptr, i64 %alt, i32 %limit) {
116110 ; CHECK-LABEL: f7:
117111 ; CHECK-NOT: %r2
118 ; CHECK: jl [[LABEL:[^ ]*]]
119 ; CHECK-NOT: %r2
120 ; CHECK: stc %r3, 0(%r2)
121 ; CHECK: [[LABEL]]:
112 ; CHECK: blr %r14
113 ; CHECK-NOT: %r2
114 ; CHECK: stc %r3, 0(%r2)
122115 ; CHECK: br %r14
123116 %cond = icmp ult i32 %limit, 420
124117 %orig = load i8 , i8 *%ptr
133126 define void @f8(i8 *%ptr, i64 %alt, i32 %limit) {
134127 ; CHECK-LABEL: f8:
135128 ; CHECK-NOT: %r2
136 ; CHECK: jhe [[LABEL:[^ ]*]]
137 ; CHECK-NOT: %r2
138 ; CHECK: stc %r3, 0(%r2)
139 ; CHECK: [[LABEL]]:
129 ; CHECK: bher %r14
130 ; CHECK-NOT: %r2
131 ; CHECK: stc %r3, 0(%r2)
140132 ; CHECK: br %r14
141133 %cond = icmp ult i32 %limit, 420
142134 %orig = load i8 , i8 *%ptr
152144 define void @f9(i8 *%ptr, i64 %alt, i32 %limit) {
153145 ; CHECK-LABEL: f9:
154146 ; CHECK-NOT: %r2
155 ; CHECK: jl [[LABEL:[^ ]*]]
156 ; CHECK-NOT: %r2
157 ; CHECK: stc %r3, 0(%r2)
158 ; CHECK: [[LABEL]]:
147 ; CHECK: blr %r14
148 ; CHECK-NOT: %r2
149 ; CHECK: stc %r3, 0(%r2)
159150 ; CHECK: br %r14
160151 %cond = icmp ult i32 %limit, 420
161152 %orig = load i8 , i8 *%ptr
170161 define void @f10(i8 *%ptr, i64 %alt, i32 %limit) {
171162 ; CHECK-LABEL: f10:
172163 ; CHECK-NOT: %r2
173 ; CHECK: jhe [[LABEL:[^ ]*]]
174 ; CHECK-NOT: %r2
175 ; CHECK: stc %r3, 0(%r2)
176 ; CHECK: [[LABEL]]:
164 ; CHECK: bher %r14
165 ; CHECK-NOT: %r2
166 ; CHECK: stc %r3, 0(%r2)
177167 ; CHECK: br %r14
178168 %cond = icmp ult i32 %limit, 420
179169 %orig = load i8 , i8 *%ptr
188178 define void @f11(i8 *%base, i8 %alt, i32 %limit) {
189179 ; CHECK-LABEL: f11:
190180 ; CHECK-NOT: %r2
191 ; CHECK: jl [[LABEL:[^ ]*]]
181 ; CHECK: blr %r14
192182 ; CHECK-NOT: %r2
193183 ; CHECK: stc %r3, 4095(%r2)
194 ; CHECK: [[LABEL]]:
195184 ; CHECK: br %r14
196185 %ptr = getelementptr i8, i8 *%base, i64 4095
197186 %cond = icmp ult i32 %limit, 420
205194 define void @f12(i8 *%base, i8 %alt, i32 %limit) {
206195 ; CHECK-LABEL: f12:
207196 ; CHECK-NOT: %r2
208 ; CHECK: jl [[LABEL:[^ ]*]]
197 ; CHECK: blr %r14
209198 ; CHECK-NOT: %r2
210199 ; CHECK: stcy %r3, 4096(%r2)
211 ; CHECK: [[LABEL]]:
212200 ; CHECK: br %r14
213201 %ptr = getelementptr i8, i8 *%base, i64 4096
214202 %cond = icmp ult i32 %limit, 420
222210 define void @f13(i8 *%base, i8 %alt, i32 %limit) {
223211 ; CHECK-LABEL: f13:
224212 ; CHECK-NOT: %r2
225 ; CHECK: jl [[LABEL:[^ ]*]]
213 ; CHECK: blr %r14
226214 ; CHECK-NOT: %r2
227215 ; CHECK: stcy %r3, 524287(%r2)
228 ; CHECK: [[LABEL]]:
229216 ; CHECK: br %r14
230217 %ptr = getelementptr i8, i8 *%base, i64 524287
231218 %cond = icmp ult i32 %limit, 420
240227 define void @f14(i8 *%base, i8 %alt, i32 %limit) {
241228 ; CHECK-LABEL: f14:
242229 ; CHECK-NOT: %r2
243 ; CHECK: jl [[LABEL:[^ ]*]]
230 ; CHECK: blr %r14
244231 ; CHECK-NOT: %r2
245232 ; CHECK: agfi %r2, 524288
246233 ; CHECK: stc %r3, 0(%r2)
247 ; CHECK: [[LABEL]]:
248234 ; CHECK: br %r14
249235 %ptr = getelementptr i8, i8 *%base, i64 524288
250236 %cond = icmp ult i32 %limit, 420
258244 define void @f15(i8 *%base, i8 %alt, i32 %limit) {
259245 ; CHECK-LABEL: f15:
260246 ; CHECK-NOT: %r2
261 ; CHECK: jl [[LABEL:[^ ]*]]
247 ; CHECK: blr %r14
262248 ; CHECK-NOT: %r2
263249 ; CHECK: stcy %r3, -524288(%r2)
264 ; CHECK: [[LABEL]]:
265250 ; CHECK: br %r14
266251 %ptr = getelementptr i8, i8 *%base, i64 -524288
267252 %cond = icmp ult i32 %limit, 420
276261 define void @f16(i8 *%base, i8 %alt, i32 %limit) {
277262 ; CHECK-LABEL: f16:
278263 ; CHECK-NOT: %r2
279 ; CHECK: jl [[LABEL:[^ ]*]]
264 ; CHECK: blr %r14
280265 ; CHECK-NOT: %r2
281266 ; CHECK: agfi %r2, -524289
282267 ; CHECK: stc %r3, 0(%r2)
283 ; CHECK: [[LABEL]]:
284268 ; CHECK: br %r14
285269 %ptr = getelementptr i8, i8 *%base, i64 -524289
286270 %cond = icmp ult i32 %limit, 420
294278 define void @f17(i64 %base, i64 %index, i8 %alt, i32 %limit) {
295279 ; CHECK-LABEL: f17:
296280 ; CHECK-NOT: %r2
297 ; CHECK: jl [[LABEL:[^ ]*]]
281 ; CHECK: blr %r14
298282 ; CHECK-NOT: %r2
299283 ; CHECK: stcy %r4, 4096(%r3,%r2)
300 ; CHECK: [[LABEL]]:
301284 ; CHECK: br %r14
302285 %add1 = add i64 %base, %index
303286 %add2 = add i64 %add1, 4096
88 define void @f1(i16 *%ptr, i16 %alt, i32 %limit) {
99 ; CHECK-LABEL: f1:
1010 ; CHECK-NOT: %r2
11 ; CHECK: jl [[LABEL:[^ ]*]]
12 ; CHECK-NOT: %r2
13 ; CHECK: sth %r3, 0(%r2)
14 ; CHECK: [[LABEL]]:
11 ; CHECK: blr %r14
12 ; CHECK-NOT: %r2
13 ; CHECK: sth %r3, 0(%r2)
1514 ; CHECK: br %r14
1615 %cond = icmp ult i32 %limit, 420
1716 %orig = load i16 , i16 *%ptr
2423 define void @f2(i16 *%ptr, i16 %alt, i32 %limit) {
2524 ; CHECK-LABEL: f2:
2625 ; CHECK-NOT: %r2
27 ; CHECK: jhe [[LABEL:[^ ]*]]
28 ; CHECK-NOT: %r2
29 ; CHECK: sth %r3, 0(%r2)
30 ; CHECK: [[LABEL]]:
26 ; CHECK: bher %r14
27 ; CHECK-NOT: %r2
28 ; CHECK: sth %r3, 0(%r2)
3129 ; CHECK: br %r14
3230 %cond = icmp ult i32 %limit, 420
3331 %orig = load i16 , i16 *%ptr
4139 define void @f3(i16 *%ptr, i32 %alt, i32 %limit) {
4240 ; CHECK-LABEL: f3:
4341 ; CHECK-NOT: %r2
44 ; CHECK: jl [[LABEL:[^ ]*]]
45 ; CHECK-NOT: %r2
46 ; CHECK: sth %r3, 0(%r2)
47 ; CHECK: [[LABEL]]:
42 ; CHECK: blr %r14
43 ; CHECK-NOT: %r2
44 ; CHECK: sth %r3, 0(%r2)
4845 ; CHECK: br %r14
4946 %cond = icmp ult i32 %limit, 420
5047 %orig = load i16 , i16 *%ptr
5956 define void @f4(i16 *%ptr, i32 %alt, i32 %limit) {
6057 ; CHECK-LABEL: f4:
6158 ; CHECK-NOT: %r2
62 ; CHECK: jhe [[LABEL:[^ ]*]]
63 ; CHECK-NOT: %r2
64 ; CHECK: sth %r3, 0(%r2)
65 ; CHECK: [[LABEL]]:
59 ; CHECK: bher %r14
60 ; CHECK-NOT: %r2
61 ; CHECK: sth %r3, 0(%r2)
6662 ; CHECK: br %r14
6763 %cond = icmp ult i32 %limit, 420
6864 %orig = load i16 , i16 *%ptr
7874 define void @f5(i16 *%ptr, i32 %alt, i32 %limit) {
7975 ; CHECK-LABEL: f5:
8076 ; CHECK-NOT: %r2
81 ; CHECK: jl [[LABEL:[^ ]*]]
82 ; CHECK-NOT: %r2
83 ; CHECK: sth %r3, 0(%r2)
84 ; CHECK: [[LABEL]]:
77 ; CHECK: blr %r14
78 ; CHECK-NOT: %r2
79 ; CHECK: sth %r3, 0(%r2)
8580 ; CHECK: br %r14
8681 %cond = icmp ult i32 %limit, 420
8782 %orig = load i16 , i16 *%ptr
9691 define void @f6(i16 *%ptr, i32 %alt, i32 %limit) {
9792 ; CHECK-LABEL: f6:
9893 ; CHECK-NOT: %r2
99 ; CHECK: jhe [[LABEL:[^ ]*]]
100 ; CHECK-NOT: %r2
101 ; CHECK: sth %r3, 0(%r2)
102 ; CHECK: [[LABEL]]:
94 ; CHECK: bher %r14
95 ; CHECK-NOT: %r2
96 ; CHECK: sth %r3, 0(%r2)
10397 ; CHECK: br %r14
10498 %cond = icmp ult i32 %limit, 420
10599 %orig = load i16 , i16 *%ptr
115109 define void @f7(i16 *%ptr, i64 %alt, i32 %limit) {
116110 ; CHECK-LABEL: f7:
117111 ; CHECK-NOT: %r2
118 ; CHECK: jl [[LABEL:[^ ]*]]
119 ; CHECK-NOT: %r2
120 ; CHECK: sth %r3, 0(%r2)
121 ; CHECK: [[LABEL]]:
112 ; CHECK: blr %r14
113 ; CHECK-NOT: %r2
114 ; CHECK: sth %r3, 0(%r2)
122115 ; CHECK: br %r14
123116 %cond = icmp ult i32 %limit, 420
124117 %orig = load i16 , i16 *%ptr
133126 define void @f8(i16 *%ptr, i64 %alt, i32 %limit) {
134127 ; CHECK-LABEL: f8:
135128 ; CHECK-NOT: %r2
136 ; CHECK: jhe [[LABEL:[^ ]*]]
137 ; CHECK-NOT: %r2
138 ; CHECK: sth %r3, 0(%r2)
139 ; CHECK: [[LABEL]]:
129 ; CHECK: bher %r14
130 ; CHECK-NOT: %r2
131 ; CHECK: sth %r3, 0(%r2)
140132 ; CHECK: br %r14
141133 %cond = icmp ult i32 %limit, 420
142134 %orig = load i16 , i16 *%ptr
152144 define void @f9(i16 *%ptr, i64 %alt, i32 %limit) {
153145 ; CHECK-LABEL: f9:
154146 ; CHECK-NOT: %r2
155 ; CHECK: jl [[LABEL:[^ ]*]]
156 ; CHECK-NOT: %r2
157 ; CHECK: sth %r3, 0(%r2)
158 ; CHECK: [[LABEL]]:
147 ; CHECK: blr %r14
148 ; CHECK-NOT: %r2
149 ; CHECK: sth %r3, 0(%r2)
159150 ; CHECK: br %r14
160151 %cond = icmp ult i32 %limit, 420
161152 %orig = load i16 , i16 *%ptr
170161 define void @f10(i16 *%ptr, i64 %alt, i32 %limit) {
171162 ; CHECK-LABEL: f10:
172163 ; CHECK-NOT: %r2
173 ; CHECK: jhe [[LABEL:[^ ]*]]
174 ; CHECK-NOT: %r2
175 ; CHECK: sth %r3, 0(%r2)
176 ; CHECK: [[LABEL]]:
164 ; CHECK: bher %r14
165 ; CHECK-NOT: %r2
166 ; CHECK: sth %r3, 0(%r2)
177167 ; CHECK: br %r14
178168 %cond = icmp ult i32 %limit, 420
179169 %orig = load i16 , i16 *%ptr
188178 define void @f11(i16 *%base, i16 %alt, i32 %limit) {
189179 ; CHECK-LABEL: f11:
190180 ; CHECK-NOT: %r2
191 ; CHECK: jl [[LABEL:[^ ]*]]
181 ; CHECK: blr %r14
192182 ; CHECK-NOT: %r2
193183 ; CHECK: sth %r3, 4094(%r2)
194 ; CHECK: [[LABEL]]:
195184 ; CHECK: br %r14
196185 %ptr = getelementptr i16, i16 *%base, i64 2047
197186 %cond = icmp ult i32 %limit, 420
205194 define void @f12(i16 *%base, i16 %alt, i32 %limit) {
206195 ; CHECK-LABEL: f12:
207196 ; CHECK-NOT: %r2
208 ; CHECK: jl [[LABEL:[^ ]*]]
197 ; CHECK: blr %r14
209198 ; CHECK-NOT: %r2
210199 ; CHECK: sthy %r3, 4096(%r2)
211 ; CHECK: [[LABEL]]:
212200 ; CHECK: br %r14
213201 %ptr = getelementptr i16, i16 *%base, i64 2048
214202 %cond = icmp ult i32 %limit, 420
222210 define void @f13(i16 *%base, i16 %alt, i32 %limit) {
223211 ; CHECK-LABEL: f13:
224212 ; CHECK-NOT: %r2
225 ; CHECK: jl [[LABEL:[^ ]*]]
213 ; CHECK: blr %r14
226214 ; CHECK-NOT: %r2
227215 ; CHECK: sthy %r3, 524286(%r2)
228 ; CHECK: [[LABEL]]:
229216 ; CHECK: br %r14
230217 %ptr = getelementptr i16, i16 *%base, i64 262143
231218 %cond = icmp ult i32 %limit, 420
240227 define void @f14(i16 *%base, i16 %alt, i32 %limit) {
241228 ; CHECK-LABEL: f14:
242229 ; CHECK-NOT: %r2
243 ; CHECK: jl [[LABEL:[^ ]*]]
230 ; CHECK: blr %r14
244231 ; CHECK-NOT: %r2
245232 ; CHECK: agfi %r2, 524288
246233 ; CHECK: sth %r3, 0(%r2)
247 ; CHECK: [[LABEL]]:
248234 ; CHECK: br %r14
249235 %ptr = getelementptr i16, i16 *%base, i64 262144
250236 %cond = icmp ult i32 %limit, 420
258244 define void @f15(i16 *%base, i16 %alt, i32 %limit) {
259245 ; CHECK-LABEL: f15:
260246 ; CHECK-NOT: %r2
261 ; CHECK: jl [[LABEL:[^ ]*]]
247 ; CHECK: blr %r14
262248 ; CHECK-NOT: %r2
263249 ; CHECK: sthy %r3, -524288(%r2)
264 ; CHECK: [[LABEL]]:
265250 ; CHECK: br %r14
266251 %ptr = getelementptr i16, i16 *%base, i64 -262144
267252 %cond = icmp ult i32 %limit, 420
276261 define void @f16(i16 *%base, i16 %alt, i32 %limit) {
277262 ; CHECK-LABEL: f16:
278263 ; CHECK-NOT: %r2
279 ; CHECK: jl [[LABEL:[^ ]*]]
264 ; CHECK: blr %r14
280265 ; CHECK-NOT: %r2
281266 ; CHECK: agfi %r2, -524290
282267 ; CHECK: sth %r3, 0(%r2)
283 ; CHECK: [[LABEL]]:
284268 ; CHECK: br %r14
285269 %ptr = getelementptr i16, i16 *%base, i64 -262145
286270 %cond = icmp ult i32 %limit, 420
294278 define void @f17(i64 %base, i64 %index, i16 %alt, i32 %limit) {
295279 ; CHECK-LABEL: f17:
296280 ; CHECK-NOT: %r2
297 ; CHECK: jl [[LABEL:[^ ]*]]
281 ; CHECK: blr %r14
298282 ; CHECK-NOT: %r2
299283 ; CHECK: sthy %r4, 4096(%r3,%r2)
300 ; CHECK: [[LABEL]]:
301284 ; CHECK: br %r14
302285 %add1 = add i64 %base, %index
303286 %add2 = add i64 %add1, 4096
77 define void @f1(i32 *%ptr, i32 %alt, i32 %limit) {
88 ; CHECK-LABEL: f1:
99 ; CHECK-NOT: %r2
10 ; CHECK: jl [[LABEL:[^ ]*]]
11 ; CHECK-NOT: %r2
12 ; CHECK: st %r3, 0(%r2)
13 ; CHECK: [[LABEL]]:
10 ; CHECK: blr %r14
11 ; CHECK-NOT: %r2
12 ; CHECK: st %r3, 0(%r2)
1413 ; CHECK: br %r14
1514 %cond = icmp ult i32 %limit, 420
1615 %orig = load i32 , i32 *%ptr
2322 define void @f2(i32 *%ptr, i32 %alt, i32 %limit) {
2423 ; CHECK-LABEL: f2:
2524 ; CHECK-NOT: %r2
26 ; CHECK: jhe [[LABEL:[^ ]*]]
27 ; CHECK-NOT: %r2
28 ; CHECK: st %r3, 0(%r2)
29 ; CHECK: [[LABEL]]:
25 ; CHECK: bher %r14
26 ; CHECK-NOT: %r2
27 ; CHECK: st %r3, 0(%r2)
3028 ; CHECK: br %r14
3129 %cond = icmp ult i32 %limit, 420
3230 %orig = load i32 , i32 *%ptr
4038 define void @f3(i32 *%ptr, i64 %alt, i32 %limit) {
4139 ; CHECK-LABEL: f3:
4240 ; CHECK-NOT: %r2
43 ; CHECK: jl [[LABEL:[^ ]*]]
44 ; CHECK-NOT: %r2
45 ; CHECK: st %r3, 0(%r2)
46 ; CHECK: [[LABEL]]:
41 ; CHECK: blr %r14
42 ; CHECK-NOT: %r2
43 ; CHECK: st %r3, 0(%r2)
4744 ; CHECK: br %r14
4845 %cond = icmp ult i32 %limit, 420
4946 %orig = load i32 , i32 *%ptr
5855 define void @f4(i32 *%ptr, i64 %alt, i32 %limit) {
5956 ; CHECK-LABEL: f4:
6057 ; CHECK-NOT: %r2
61 ; CHECK: jhe [[LABEL:[^ ]*]]
62 ; CHECK-NOT: %r2
63 ; CHECK: st %r3, 0(%r2)
64 ; CHECK: [[LABEL]]:
58 ; CHECK: bher %r14
59 ; CHECK-NOT: %r2
60 ; CHECK: st %r3, 0(%r2)
6561 ; CHECK: br %r14
6662 %cond = icmp ult i32 %limit, 420
6763 %orig = load i32 , i32 *%ptr
7773 define void @f5(i32 *%ptr, i64 %alt, i32 %limit) {
7874 ; CHECK-LABEL: f5:
7975 ; CHECK-NOT: %r2
80 ; CHECK: jl [[LABEL:[^ ]*]]
81 ; CHECK-NOT: %r2
82 ; CHECK: st %r3, 0(%r2)
83 ; CHECK: [[LABEL]]:
76 ; CHECK: blr %r14
77 ; CHECK-NOT: %r2
78 ; CHECK: st %r3, 0(%r2)
8479 ; CHECK: br %r14
8580 %cond = icmp ult i32 %limit, 420
8681 %orig = load i32 , i32 *%ptr
9590 define void @f6(i32 *%ptr, i64 %alt, i32 %limit) {
9691 ; CHECK-LABEL: f6:
9792 ; CHECK-NOT: %r2
98 ; CHECK: jhe [[LABEL:[^ ]*]]
99 ; CHECK-NOT: %r2
100 ; CHECK: st %r3, 0(%r2)
101 ; CHECK: [[LABEL]]:
93 ; CHECK: bher %r14
94 ; CHECK-NOT: %r2
95 ; CHECK: st %r3, 0(%r2)
10296 ; CHECK: br %r14
10397 %cond = icmp ult i32 %limit, 420
10498 %orig = load i32 , i32 *%ptr
113107 define void @f7(i32 *%base, i32 %alt, i32 %limit) {
114108 ; CHECK-LABEL: f7:
115109 ; CHECK-NOT: %r2
116 ; CHECK: jl [[LABEL:[^ ]*]]
110 ; CHECK: blr %r14
117111 ; CHECK-NOT: %r2
118112 ; CHECK: st %r3, 4092(%r2)
119 ; CHECK: [[LABEL]]:
120113 ; CHECK: br %r14
121114 %ptr = getelementptr i32, i32 *%base, i64 1023
122115 %cond = icmp ult i32 %limit, 420
130123 define void @f8(i32 *%base, i32 %alt, i32 %limit) {
131124 ; CHECK-LABEL: f8:
132125 ; CHECK-NOT: %r2
133 ; CHECK: jl [[LABEL:[^ ]*]]
126 ; CHECK: blr %r14
134127 ; CHECK-NOT: %r2
135128 ; CHECK: sty %r3, 4096(%r2)
136 ; CHECK: [[LABEL]]:
137129 ; CHECK: br %r14
138130 %ptr = getelementptr i32, i32 *%base, i64 1024
139131 %cond = icmp ult i32 %limit, 420
147139 define void @f9(i32 *%base, i32 %alt, i32 %limit) {
148140 ; CHECK-LABEL: f9:
149141 ; CHECK-NOT: %r2
150 ; CHECK: jl [[LABEL:[^ ]*]]
142 ; CHECK: blr %r14
151143 ; CHECK-NOT: %r2
152144 ; CHECK: sty %r3, 524284(%r2)
153 ; CHECK: [[LABEL]]:
154145 ; CHECK: br %r14
155146 %ptr = getelementptr i32, i32 *%base, i64 131071
156147 %cond = icmp ult i32 %limit, 420
165156 define void @f10(i32 *%base, i32 %alt, i32 %limit) {
166157 ; CHECK-LABEL: f10:
167158 ; CHECK-NOT: %r2
168 ; CHECK: jl [[LABEL:[^ ]*]]
159 ; CHECK: blr %r14
169160 ; CHECK-NOT: %r2
170161 ; CHECK: agfi %r2, 524288
171162 ; CHECK: st %r3, 0(%r2)
172 ; CHECK: [[LABEL]]:
173163 ; CHECK: br %r14
174164 %ptr = getelementptr i32, i32 *%base, i64 131072
175165 %cond = icmp ult i32 %limit, 420
183173 define void @f11(i32 *%base, i32 %alt, i32 %limit) {
184174 ; CHECK-LABEL: f11:
185175 ; CHECK-NOT: %r2
186 ; CHECK: jl [[LABEL:[^ ]*]]
176 ; CHECK: blr %r14
187177 ; CHECK-NOT: %r2
188178 ; CHECK: sty %r3, -524288(%r2)
189 ; CHECK: [[LABEL]]:
190179 ; CHECK: br %r14
191180 %ptr = getelementptr i32, i32 *%base, i64 -131072
192181 %cond = icmp ult i32 %limit, 420
201190 define void @f12(i32 *%base, i32 %alt, i32 %limit) {
202191 ; CHECK-LABEL: f12:
203192 ; CHECK-NOT: %r2
204 ; CHECK: jl [[LABEL:[^ ]*]]
193 ; CHECK: blr %r14
205194 ; CHECK-NOT: %r2
206195 ; CHECK: agfi %r2, -524292
207196 ; CHECK: st %r3, 0(%r2)
208 ; CHECK: [[LABEL]]:
209197 ; CHECK: br %r14
210198 %ptr = getelementptr i32, i32 *%base, i64 -131073
211199 %cond = icmp ult i32 %limit, 420
219207 define void @f13(i64 %base, i64 %index, i32 %alt, i32 %limit) {
220208 ; CHECK-LABEL: f13:
221209 ; CHECK-NOT: %r2
222 ; CHECK: jl [[LABEL:[^ ]*]]
210 ; CHECK: blr %r14
223211 ; CHECK-NOT: %r2
224212 ; CHECK: sty %r4, 4096(%r3,%r2)
225 ; CHECK: [[LABEL]]:
226213 ; CHECK: br %r14
227214 %add1 = add i64 %base, %index
228215 %add2 = add i64 %add1, 4096
77 define void @f1(i64 *%ptr, i64 %alt, i32 %limit) {
88 ; CHECK-LABEL: f1:
99 ; CHECK-NOT: %r2
10 ; CHECK: jl [[LABEL:[^ ]*]]
11 ; CHECK-NOT: %r2
12 ; CHECK: stg %r3, 0(%r2)
13 ; CHECK: [[LABEL]]:
10 ; CHECK: blr %r14
11 ; CHECK-NOT: %r2
12 ; CHECK: stg %r3, 0(%r2)
1413 ; CHECK: br %r14
1514 %cond = icmp ult i32 %limit, 420
1615 %orig = load i64 , i64 *%ptr
2322 define void @f2(i64 *%ptr, i64 %alt, i32 %limit) {
2423 ; CHECK-LABEL: f2:
2524 ; CHECK-NOT: %r2
26 ; CHECK: jhe [[LABEL:[^ ]*]]
27 ; CHECK-NOT: %r2
28 ; CHECK: stg %r3, 0(%r2)
29 ; CHECK: [[LABEL]]:
25 ; CHECK: bher %r14
26 ; CHECK-NOT: %r2
27 ; CHECK: stg %r3, 0(%r2)
3028 ; CHECK: br %r14
3129 %cond = icmp ult i32 %limit, 420
3230 %orig = load i64 , i64 *%ptr
3937 define void @f3(i64 *%base, i64 %alt, i32 %limit) {
4038 ; CHECK-LABEL: f3:
4139 ; CHECK-NOT: %r2
42 ; CHECK: jl [[LABEL:[^ ]*]]
40 ; CHECK: blr %r14
4341 ; CHECK-NOT: %r2
4442 ; CHECK: stg %r3, 524280(%r2)
45 ; CHECK: [[LABEL]]:
4643 ; CHECK: br %r14
4744 %ptr = getelementptr i64, i64 *%base, i64 65535
4845 %cond = icmp ult i32 %limit, 420
5754 define void @f4(i64 *%base, i64 %alt, i32 %limit) {
5855 ; CHECK-LABEL: f4:
5956 ; CHECK-NOT: %r2
60 ; CHECK: jl [[LABEL:[^ ]*]]
57 ; CHECK: blr %r14
6158 ; CHECK-NOT: %r2
6259 ; CHECK: agfi %r2, 524288
6360 ; CHECK: stg %r3, 0(%r2)
64 ; CHECK: [[LABEL]]:
6561 ; CHECK: br %r14
6662 %ptr = getelementptr i64, i64 *%base, i64 65536
6763 %cond = icmp ult i32 %limit, 420
7571 define void @f5(i64 *%base, i64 %alt, i32 %limit) {
7672 ; CHECK-LABEL: f5:
7773 ; CHECK-NOT: %r2
78 ; CHECK: jl [[LABEL:[^ ]*]]
74 ; CHECK: blr %r14
7975 ; CHECK-NOT: %r2
8076 ; CHECK: stg %r3, -524288(%r2)
81 ; CHECK: [[LABEL]]:
8277 ; CHECK: br %r14
8378 %ptr = getelementptr i64, i64 *%base, i64 -65536
8479 %cond = icmp ult i32 %limit, 420
9388 define void @f6(i64 *%base, i64 %alt, i32 %limit) {
9489 ; CHECK-LABEL: f6:
9590 ; CHECK-NOT: %r2
96 ; CHECK: jl [[LABEL:[^ ]*]]
91 ; CHECK: blr %r14
9792 ; CHECK-NOT: %r2
9893 ; CHECK: agfi %r2, -524296
9994 ; CHECK: stg %r3, 0(%r2)
100 ; CHECK: [[LABEL]]:
10195 ; CHECK: br %r14
10296 %ptr = getelementptr i64, i64 *%base, i64 -65537
10397 %cond = icmp ult i32 %limit, 420
111105 define void @f7(i64 %base, i64 %index, i64 %alt, i32 %limit) {
112106 ; CHECK-LABEL: f7:
113107 ; CHECK-NOT: %r2
114 ; CHECK: jl [[LABEL:[^ ]*]]
108 ; CHECK: blr %r14
115109 ; CHECK-NOT: %r2
116110 ; CHECK: stg %r4, 524287(%r3,%r2)
117 ; CHECK: [[LABEL]]:
118111 ; CHECK: br %r14
119112 %add1 = add i64 %base, %index
120113 %add2 = add i64 %add1, 524287
77 define void @f1(float *%ptr, float %alt, i32 %limit) {
88 ; CHECK-LABEL: f1:
99 ; CHECK-NOT: %r2
10 ; CHECK: jl [[LABEL:[^ ]*]]
11 ; CHECK-NOT: %r2
12 ; CHECK: ste %f0, 0(%r2)
13 ; CHECK: [[LABEL]]:
10 ; CHECK: blr %r14
11 ; CHECK-NOT: %r2
12 ; CHECK: ste %f0, 0(%r2)
1413 ; CHECK: br %r14
1514 %cond = icmp ult i32 %limit, 420
1615 %orig = load float , float *%ptr
2322 define void @f2(float *%ptr, float %alt, i32 %limit) {
2423 ; CHECK-LABEL: f2:
2524 ; CHECK-NOT: %r2
26 ; CHECK: jhe [[LABEL:[^ ]*]]
27 ; CHECK-NOT: %r2
28 ; CHECK: ste %f0, 0(%r2)
29 ; CHECK: [[LABEL]]:
25 ; CHECK: bher %r14
26 ; CHECK-NOT: %r2
27 ; CHECK: ste %f0, 0(%r2)
3028 ; CHECK: br %r14
3129 %cond = icmp ult i32 %limit, 420
3230 %orig = load float , float *%ptr
3937 define void @f3(float *%base, float %alt, i32 %limit) {
4038 ; CHECK-LABEL: f3:
4139 ; CHECK-NOT: %r2
42 ; CHECK: jl [[LABEL:[^ ]*]]
40 ; CHECK: blr %r14
4341 ; CHECK-NOT: %r2
4442 ; CHECK: ste %f0, 4092(%r2)
45 ; CHECK: [[LABEL]]:
4643 ; CHECK: br %r14
4744 %ptr = getelementptr float, float *%base, i64 1023
4845 %cond = icmp ult i32 %limit, 420
5653 define void @f4(float *%base, float %alt, i32 %limit) {
5754 ; CHECK-LABEL: f4:
5855 ; CHECK-NOT: %r2
59 ; CHECK: jl [[LABEL:[^ ]*]]
56 ; CHECK: blr %r14
6057 ; CHECK-NOT: %r2
6158 ; CHECK: stey %f0, 4096(%r2)
62 ; CHECK: [[LABEL]]:
6359 ; CHECK: br %r14
6460 %ptr = getelementptr float, float *%base, i64 1024
6561 %cond = icmp ult i32 %limit, 420
7369 define void @f5(float *%base, float %alt, i32 %limit) {
7470 ; CHECK-LABEL: f5:
7571 ; CHECK-NOT: %r2
76 ; CHECK: jl [[LABEL:[^ ]*]]
72 ; CHECK: blr %r14
7773 ; CHECK-NOT: %r2
7874 ; CHECK: stey %f0, 524284(%r2)
79 ; CHECK: [[LABEL]]:
8075 ; CHECK: br %r14
8176 %ptr = getelementptr float, float *%base, i64 131071
8277 %cond = icmp ult i32 %limit, 420
9186 define void @f6(float *%base, float %alt, i32 %limit) {
9287 ; CHECK-LABEL: f6:
9388 ; CHECK-NOT: %r2
94 ; CHECK: jl [[LABEL:[^ ]*]]
89 ; CHECK: blr %r14
9590 ; CHECK-NOT: %r2
9691 ; CHECK: agfi %r2, 524288
9792 ; CHECK: ste %f0, 0(%r2)
98 ; CHECK: [[LABEL]]:
9993 ; CHECK: br %r14
10094 %ptr = getelementptr float, float *%base, i64 131072
10195 %cond = icmp ult i32 %limit, 420
109103 define void @f7(float *%base, float %alt, i32 %limit) {
110104 ; CHECK-LABEL: f7:
111105 ; CHECK-NOT: %r2
112 ; CHECK: jl [[LABEL:[^ ]*]]
106 ; CHECK: blr %r14
113107 ; CHECK-NOT: %r2
114108 ; CHECK: stey %f0, -524288(%r2)
115 ; CHECK: [[LABEL]]:
116109 ; CHECK: br %r14
117110 %ptr = getelementptr float, float *%base, i64 -131072
118111 %cond = icmp ult i32 %limit, 420
127120 define void @f8(float *%base, float %alt, i32 %limit) {
128121 ; CHECK-LABEL: f8:
129122 ; CHECK-NOT: %r2
130 ; CHECK: jl [[LABEL:[^ ]*]]
123 ; CHECK: blr %r14
131124 ; CHECK-NOT: %r2
132125 ; CHECK: agfi %r2, -524292
133126 ; CHECK: ste %f0, 0(%r2)
134 ; CHECK: [[LABEL]]:
135127 ; CHECK: br %r14
136128 %ptr = getelementptr float, float *%base, i64 -131073
137129 %cond = icmp ult i32 %limit, 420
145137 define void @f9(i64 %base, i64 %index, float %alt, i32 %limit) {
146138 ; CHECK-LABEL: f9:
147139 ; CHECK-NOT: %r2
148 ; CHECK: jl [[LABEL:[^ ]*]]
140 ; CHECK: blr %r14
149141 ; CHECK-NOT: %r2
150142 ; CHECK: stey %f0, 4096(%r3,%r2)
151 ; CHECK: [[LABEL]]:
152143 ; CHECK: br %r14
153144 %add1 = add i64 %base, %index
154145 %add2 = add i64 %add1, 4096
77 define void @f1(double *%ptr, double %alt, i32 %limit) {
88 ; CHECK-LABEL: f1:
99 ; CHECK-NOT: %r2
10 ; CHECK: jl [[LABEL:[^ ]*]]
11 ; CHECK-NOT: %r2
12 ; CHECK: std %f0, 0(%r2)
13 ; CHECK: [[LABEL]]:
10 ; CHECK: blr %r14
11 ; CHECK-NOT: %r2
12 ; CHECK: std %f0, 0(%r2)
1413 ; CHECK: br %r14
1514 %cond = icmp ult i32 %limit, 420
1615 %orig = load double , double *%ptr
2322 define void @f2(double *%ptr, double %alt, i32 %limit) {
2423 ; CHECK-LABEL: f2:
2524 ; CHECK-NOT: %r2
26 ; CHECK: jhe [[LABEL:[^ ]*]]
27 ; CHECK-NOT: %r2
28 ; CHECK: std %f0, 0(%r2)
29 ; CHECK: [[LABEL]]:
25 ; CHECK: bher %r14
26 ; CHECK-NOT: %r2
27 ; CHECK: std %f0, 0(%r2)
3028 ; CHECK: br %r14
3129 %cond = icmp ult i32 %limit, 420
3230 %orig = load double , double *%ptr
3937 define void @f3(double *%base, double %alt, i32 %limit) {
4038 ; CHECK-LABEL: f3:
4139 ; CHECK-NOT: %r2
42 ; CHECK: jl [[LABEL:[^ ]*]]
40 ; CHECK: blr %r14
4341 ; CHECK-NOT: %r2
4442 ; CHECK: std %f0, 4088(%r2)
45 ; CHECK: [[LABEL]]:
4643 ; CHECK: br %r14
4744 %ptr = getelementptr double, double *%base, i64 511
4845 %cond = icmp ult i32 %limit, 420
5653 define void @f4(double *%base, double %alt, i32 %limit) {
5754 ; CHECK-LABEL: f4:
5855 ; CHECK-NOT: %r2
59 ; CHECK: jl [[LABEL:[^ ]*]]
56 ; CHECK: blr %r14
6057 ; CHECK-NOT: %r2
6158 ; CHECK: stdy %f0, 4096(%r2)
62 ; CHECK: [[LABEL]]:
6359 ; CHECK: br %r14
6460 %ptr = getelementptr double, double *%base, i64 512
6561 %cond = icmp ult i32 %limit, 420
7369 define void @f5(double *%base, double %alt, i32 %limit) {
7470 ; CHECK-LABEL: f5:
7571 ; CHECK-NOT: %r2
76 ; CHECK: jl [[LABEL:[^ ]*]]
72 ; CHECK: blr %r14
7773 ; CHECK-NOT: %r2
7874 ; CHECK: stdy %f0, 524280(%r2)
79 ; CHECK: [[LABEL]]:
8075 ; CHECK: br %r14
8176 %ptr = getelementptr double, double *%base, i64 65535
8277 %cond = icmp ult i32 %limit, 420
9186 define void @f6(double *%base, double %alt, i32 %limit) {
9287 ; CHECK-LABEL: f6:
9388 ; CHECK-NOT: %r2
94 ; CHECK: jl [[LABEL:[^ ]*]]
89 ; CHECK: blr %r14
9590 ; CHECK-NOT: %r2
9691 ; CHECK: agfi %r2, 524288
9792 ; CHECK: std %f0, 0(%r2)
98 ; CHECK: [[LABEL]]:
9993 ; CHECK: br %r14
10094 %ptr = getelementptr double, double *%base, i64 65536
10195 %cond = icmp ult i32 %limit, 420
109103 define void @f7(double *%base, double %alt, i32 %limit) {
110104 ; CHECK-LABEL: f7:
111105 ; CHECK-NOT: %r2
112 ; CHECK: jl [[LABEL:[^ ]*]]
106 ; CHECK: blr %r14
113107 ; CHECK-NOT: %r2
114108 ; CHECK: stdy %f0, -524288(%r2)
115 ; CHECK: [[LABEL]]:
116109 ; CHECK: br %r14
117110 %ptr = getelementptr double, double *%base, i64 -65536
118111 %cond = icmp ult i32 %limit, 420
127120 define void @f8(double *%base, double %alt, i32 %limit) {
128121 ; CHECK-LABEL: f8:
129122 ; CHECK-NOT: %r2
130 ; CHECK: jl [[LABEL:[^ ]*]]
123 ; CHECK: blr %r14
131124 ; CHECK-NOT: %r2
132125 ; CHECK: agfi %r2, -524296
133126 ; CHECK: std %f0, 0(%r2)
134 ; CHECK: [[LABEL]]:
135127 ; CHECK: br %r14
136128 %ptr = getelementptr double, double *%base, i64 -65537
137129 %cond = icmp ult i32 %limit, 420
145137 define void @f9(i64 %base, i64 %index, double %alt, i32 %limit) {
146138 ; CHECK-LABEL: f9:
147139 ; CHECK-NOT: %r2
148 ; CHECK: jl [[LABEL:[^ ]*]]
140 ; CHECK: blr %r14
149141 ; CHECK-NOT: %r2
150142 ; CHECK: stdy %f0, 524287(%r3,%r2)
151 ; CHECK: [[LABEL]]:
152143 ; CHECK: br %r14
153144 %add1 = add i64 %base, %index
154145 %add2 = add i64 %add1, 524287
88 define i64 @f1(i64 %a, i64 %b, float %f1, float %f2) {
99 ; CHECK-LABEL: f1:
1010 ; CHECK: cebr %f0, %f2
11 ; CHECK-NEXT: je
11 ; CHECK-NEXT: ber %r14
1212 ; CHECK: lgr %r2, %r3
1313 ; CHECK: br %r14
1414 %cond = fcmp oeq float %f1, %f2
2020 define i64 @f2(i64 %a, i64 %b, float %f1, float *%ptr) {
2121 ; CHECK-LABEL: f2:
2222 ; CHECK: ceb %f0, 0(%r4)
23 ; CHECK-NEXT: je
23 ; CHECK-NEXT: ber %r14
2424 ; CHECK: lgr %r2, %r3
2525 ; CHECK: br %r14
2626 %f2 = load float , float *%ptr
3333 define i64 @f3(i64 %a, i64 %b, float %f1, float *%base) {
3434 ; CHECK-LABEL: f3:
3535 ; CHECK: ceb %f0, 4092(%r4)
36 ; CHECK-NEXT: je
36 ; CHECK-NEXT: ber %r14
3737 ; CHECK: lgr %r2, %r3
3838 ; CHECK: br %r14
3939 %ptr = getelementptr float, float *%base, i64 1023
4949 ; CHECK-LABEL: f4:
5050 ; CHECK: aghi %r4, 4096
5151 ; CHECK: ceb %f0, 0(%r4)
52 ; CHECK-NEXT: je
52 ; CHECK-NEXT: ber %r14
5353 ; CHECK: lgr %r2, %r3
5454 ; CHECK: br %r14
5555 %ptr = getelementptr float, float *%base, i64 1024
6464 ; CHECK-LABEL: f5:
6565 ; CHECK: aghi %r4, -4
6666 ; CHECK: ceb %f0, 0(%r4)
67 ; CHECK-NEXT: je
67 ; CHECK-NEXT: ber %r14
6868 ; CHECK: lgr %r2, %r3
6969 ; CHECK: br %r14
7070 %ptr = getelementptr float, float *%base, i64 -1
7979 ; CHECK-LABEL: f6:
8080 ; CHECK: sllg %r1, %r5, 2
8181 ; CHECK: ceb %f0, 400(%r1,%r4)
82 ; CHECK-NEXT: je
82 ; CHECK-NEXT: ber %r14
8383 ; CHECK: lgr %r2, %r3
8484 ; CHECK: br %r14
8585 %ptr1 = getelementptr float, float *%base, i64 %index
152152 define i64 @f8(i64 %a, i64 %b, float %f) {
153153 ; CHECK-LABEL: f8:
154154 ; CHECK: ltebr %f0, %f0
155 ; CHECK-NEXT: je
155 ; CHECK-NEXT: ber %r14
156156 ; CHECK: lgr %r2, %r3
157157 ; CHECK: br %r14
158158 %cond = fcmp oeq float %f, 0.0
165165 define i64 @f9(i64 %a, i64 %b, float %f2, float *%ptr) {
166166 ; CHECK-LABEL: f9:
167167 ; CHECK: ceb %f0, 0(%r4)
168 ; CHECK-NEXT: je {{\.L.*}}
168 ; CHECK-NEXT: ber %r14
169169 ; CHECK: lgr %r2, %r3
170170 ; CHECK: br %r14
171171 %f1 = load float , float *%ptr
178178 define i64 @f10(i64 %a, i64 %b, float %f2, float *%ptr) {
179179 ; CHECK-LABEL: f10:
180180 ; CHECK: ceb %f0, 0(%r4)
181 ; CHECK-NEXT: jlh {{\.L.*}}
181 ; CHECK-NEXT: blhr %r14
182182 ; CHECK: lgr %r2, %r3
183183 ; CHECK: br %r14
184184 %f1 = load float , float *%ptr
191191 define i64 @f11(i64 %a, i64 %b, float %f2, float *%ptr) {
192192 ; CHECK-LABEL: f11:
193193 ; CHECK: ceb %f0, 0(%r4)
194 ; CHECK-NEXT: jh {{\.L.*}}
194 ; CHECK-NEXT: bhr %r14
195195 ; CHECK: lgr %r2, %r3
196196 ; CHECK: br %r14
197197 %f1 = load float , float *%ptr
204204 define i64 @f12(i64 %a, i64 %b, float %f2, float *%ptr) {
205205 ; CHECK-LABEL: f12:
206206 ; CHECK: ceb %f0, 0(%r4)
207 ; CHECK-NEXT: jhe {{\.L.*}}
207 ; CHECK-NEXT: bher %r14
208208 ; CHECK: lgr %r2, %r3
209209 ; CHECK: br %r14
210210 %f1 = load float , float *%ptr
217217 define i64 @f13(i64 %a, i64 %b, float %f2, float *%ptr) {
218218 ; CHECK-LABEL: f13:
219219 ; CHECK: ceb %f0, 0(%r4)
220 ; CHECK-NEXT: jle {{\.L.*}}
220 ; CHECK-NEXT: bler %r14
221221 ; CHECK: lgr %r2, %r3
222222 ; CHECK: br %r14
223223 %f1 = load float , float *%ptr
230230 define i64 @f14(i64 %a, i64 %b, float %f2, float *%ptr) {
231231 ; CHECK-LABEL: f14:
232232 ; CHECK: ceb %f0, 0(%r4)
233 ; CHECK-NEXT: jl {{\.L.*}}
233 ; CHECK-NEXT: blr %r14
234234 ; CHECK: lgr %r2, %r3
235235 ; CHECK: br %r14
236236 %f1 = load float , float *%ptr
243243 define i64 @f15(i64 %a, i64 %b, float %f2, float *%ptr) {
244244 ; CHECK-LABEL: f15:
245245 ; CHECK: ceb %f0, 0(%r4)
246 ; CHECK-NEXT: jnlh {{\.L.*}}
246 ; CHECK-NEXT: bnlhr %r14
247247 ; CHECK: lgr %r2, %r3
248248 ; CHECK: br %r14
249249 %f1 = load float , float *%ptr
256256 define i64 @f16(i64 %a, i64 %b, float %f2, float *%ptr) {
257257 ; CHECK-LABEL: f16:
258258 ; CHECK: ceb %f0, 0(%r4)
259 ; CHECK-NEXT: jne {{\.L.*}}
259 ; CHECK-NEXT: bner %r14
260260 ; CHECK: lgr %r2, %r3
261261 ; CHECK: br %r14
262262 %f1 = load float , float *%ptr
269269 define i64 @f17(i64 %a, i64 %b, float %f2, float *%ptr) {
270270 ; CHECK-LABEL: f17:
271271 ; CHECK: ceb %f0, 0(%r4)
272 ; CHECK-NEXT: jnle {{\.L.*}}
272 ; CHECK-NEXT: bnler %r14
273273 ; CHECK: lgr %r2, %r3
274274 ; CHECK: br %r14
275275 %f1 = load float , float *%ptr
282282 define i64 @f18(i64 %a, i64 %b, float %f2, float *%ptr) {
283283 ; CHECK-LABEL: f18:
284284 ; CHECK: ceb %f0, 0(%r4)
285 ; CHECK-NEXT: jnl {{\.L.*}}
285 ; CHECK-NEXT: bnlr %r14
286286 ; CHECK: lgr %r2, %r3
287287 ; CHECK: br %r14
288288 %f1 = load float , float *%ptr
295295 define i64 @f19(i64 %a, i64 %b, float %f2, float *%ptr) {
296296 ; CHECK-LABEL: f19:
297297 ; CHECK: ceb %f0, 0(%r4)
298 ; CHECK-NEXT: jnh {{\.L.*}}
298 ; CHECK-NEXT: bnhr %r14
299299 ; CHECK: lgr %r2, %r3
300300 ; CHECK: br %r14
301301 %f1 = load float , float *%ptr
308308 define i64 @f20(i64 %a, i64 %b, float %f2, float *%ptr) {
309309 ; CHECK-LABEL: f20:
310310 ; CHECK: ceb %f0, 0(%r4)
311 ; CHECK-NEXT: jnhe {{\.L.*}}
311 ; CHECK-NEXT: bnher %r14
312312 ; CHECK: lgr %r2, %r3
313313 ; CHECK: br %r14
314314 %f1 = load float , float *%ptr
1111 define i64 @f1(i64 %a, i64 %b, double %f1, double %f2) {
1212 ; CHECK-LABEL: f1:
1313 ; CHECK: cdbr %f0, %f2
14 ; CHECK-SCALAR-NEXT: je
14 ; CHECK-SCALAR-NEXT: ber %r14
1515 ; CHECK-SCALAR: lgr %r2, %r3
1616 ; CHECK-VECTOR-NEXT: locgrne %r2, %r3
1717 ; CHECK: br %r14
2424 define i64 @f2(i64 %a, i64 %b, double %f1, double *%ptr) {
2525 ; CHECK-LABEL: f2:
2626 ; CHECK: cdb %f0, 0(%r4)
27 ; CHECK-SCALAR-NEXT: je
27 ; CHECK-SCALAR-NEXT: ber %r14
2828 ; CHECK-SCALAR: lgr %r2, %r3
2929 ; CHECK-VECTOR-NEXT: locgrne %r2, %r3
3030 ; CHECK: br %r14
3838 define i64 @f3(i64 %a, i64 %b, double %f1, double *%base) {
3939 ; CHECK-LABEL: f3:
4040 ; CHECK: cdb %f0, 4088(%r4)
41 ; CHECK-SCALAR-NEXT: je
41 ; CHECK-SCALAR-NEXT: ber %r14
4242 ; CHECK-SCALAR: lgr %r2, %r3
4343 ; CHECK-VECTOR-NEXT: locgrne %r2, %r3
4444 ; CHECK: br %r14
5555 ; CHECK-LABEL: f4:
5656 ; CHECK: aghi %r4, 4096
5757 ; CHECK: cdb %f0, 0(%r4)
58 ; CHECK-SCALAR-NEXT: je
58 ; CHECK-SCALAR-NEXT: ber %r14
5959 ; CHECK-SCALAR: lgr %r2, %r3
6060 ; CHECK-VECTOR-NEXT: locgrne %r2, %r3
6161 ; CHECK: br %r14
7171 ; CHECK-LABEL: f5:
7272 ; CHECK: aghi %r4, -8
7373 ; CHECK: cdb %f0, 0(%r4)
74 ; CHECK-SCALAR-NEXT: je
74 ; CHECK-SCALAR-NEXT: ber %r14
7575 ; CHECK-SCALAR: lgr %r2, %r3
7676 ; CHECK-VECTOR-NEXT: locgrne %r2, %r3
7777 ; CHECK: br %r14
8787 ; CHECK-LABEL: f6:
8888 ; CHECK: sllg %r1, %r5, 3
8989 ; CHECK: cdb %f0, 800(%r1,%r4)
90 ; CHECK-SCALAR-NEXT: je
90 ; CHECK-SCALAR-NEXT: ber %r14
9191 ; CHECK-SCALAR: lgr %r2, %r3
9292 ; CHECK-VECTOR-NEXT: locgrne %r2, %r3
9393 ; CHECK: br %r14
161161 define i64 @f8(i64 %a, i64 %b, double %f) {
162162 ; CHECK-LABEL: f8:
163163 ; CHECK-SCALAR: ltdbr %f0, %f0
164 ; CHECK-SCALAR-NEXT: je
164 ; CHECK-SCALAR-NEXT: ber %r14
165165 ; CHECK-SCALAR: lgr %r2, %r3
166166 ; CHECK-VECTOR: ltdbr %f0, %f0
167167 ; CHECK-VECTOR-NEXT: locgrne %r2, %r3
175175 define i64 @f9(i64 %a, i64 %b, double %f2, double *%ptr) {
176176 ; CHECK-LABEL: f9:
177177 ; CHECK: cdb %f0, 0(%r4)
178 ; CHECK-SCALAR-NEXT: jl
178 ; CHECK-SCALAR-NEXT: blr %r14
179179 ; CHECK-SCALAR: lgr %r2, %r3
180180 ; CHECK-VECTOR-NEXT: locgrnl %r2, %r3
181181 ; CHECK: br %r14
99 ; CHECK: ld %f1, 0(%r4)
1010 ; CHECK: ld %f3, 8(%r4)
1111 ; CHECK: cxbr %f1, %f0
12 ; CHECK-NEXT: je
12 ; CHECK-NEXT: ber %r14
1313 ; CHECK: lgr %r2, %r3
1414 ; CHECK: br %r14
1515 %f2x = fpext float %f2 to fp128
2525 ; CHECK: ld %f0, 0(%r4)
2626 ; CHECK: ld %f2, 8(%r4)
2727 ; CHECK: ltxbr %f0, %f0
28 ; CHECK-NEXT: je
28 ; CHECK-NEXT: ber %r14
2929 ; CHECK: lgr %r2, %r3
3030 ; CHECK: br %r14
3131 %f = load fp128 , fp128 *%ptr
88 define float @f1(float %a, float %b, float *%dest) {
99 ; CHECK-LABEL: f1:
1010 ; CHECK: aebr %f0, %f2
11 ; CHECK-NEXT: je .L{{.*}}
11 ; CHECK-NEXT: ber %r14
1212 ; CHECK: br %r14
1313 entry:
1414 %res = fadd float %a, %b
2727 define float @f2(float %a, float %b, float *%dest) {
2828 ; CHECK-LABEL: f2:
2929 ; CHECK: aebr %f0, %f2
30 ; CHECK-NEXT: jl .L{{.*}}
30 ; CHECK-NEXT: blr %r14
3131 ; CHECK: br %r14
3232 entry:
3333 %res = fadd float %a, %b
4646 define float @f3(float %a, float %b, float *%dest) {
4747 ; CHECK-LABEL: f3:
4848 ; CHECK: aebr %f0, %f2
49 ; CHECK-NEXT: jh .L{{.*}}
49 ; CHECK-NEXT: bhr %r14
5050 ; CHECK: br %r14
5151 entry:
5252 %res = fadd float %a, %b
6565 define float @f4(float %a, float %b, float *%dest) {
6666 ; CHECK-LABEL: f4:
6767 ; CHECK: aebr %f0, %f2
68 ; CHECK-NEXT: jnlh .L{{.*}}
68 ; CHECK-NEXT: bnlhr %r14
6969 ; CHECK: br %r14
7070 entry:
7171 %res = fadd float %a, %b
8484 define float @f5(float %a, float %b, float *%dest) {
8585 ; CHECK-LABEL: f5:
8686 ; CHECK: seb %f0, 0(%r2)
87 ; CHECK-NEXT: jnhe .L{{.*}}
87 ; CHECK-NEXT: bnher %r14
8888 ; CHECK: br %r14
8989 entry:
9090 %cur = load float , float *%dest
104104 define float @f6(float %dummy, float %a, float *%dest) {
105105 ; CHECK-LABEL: f6:
106106 ; CHECK: lpebr %f0, %f2
107 ; CHECK-NEXT: jh .L{{.*}}
107 ; CHECK-NEXT: bhr %r14
108108 ; CHECK: br %r14
109109 entry:
110110 %res = call float @llvm.fabs.f32(float %a)
123123 define float @f7(float %dummy, float %a, float *%dest) {
124124 ; CHECK-LABEL: f7:
125125 ; CHECK: lnebr %f0, %f2
126 ; CHECK-NEXT: jl .L{{.*}}
126 ; CHECK-NEXT: blr %r14
127127 ; CHECK: br %r14
128128 entry:
129129 %abs = call float @llvm.fabs.f32(float %a)
143143 define float @f8(float %dummy, float %a, float *%dest) {
144144 ; CHECK-LABEL: f8:
145145 ; CHECK: lcebr %f0, %f2
146 ; CHECK-NEXT: jle .L{{.*}}
146 ; CHECK-NEXT: bler %r14
147147 ; CHECK: br %r14
148148 entry:
149149 %res = fsub float -0.0, %a
163163 ; CHECK-LABEL: f9:
164164 ; CHECK: meebr %f0, %f2
165165 ; CHECK-NEXT: ltebr %f0, %f0
166 ; CHECK-NEXT: jlh .L{{.*}}
166 ; CHECK-NEXT: blhr %r14
167167 ; CHECK: br %r14
168168 entry:
169169 %res = fmul float %a, %b
185185 ; CHECK: aebr %f0, %f2
186186 ; CHECK-NEXT: debr %f0, %f4
187187 ; CHECK-NEXT: ltebr %f0, %f0
188 ; CHECK-NEXT: jne .L{{.*}}
188 ; CHECK-NEXT: bner %r14
189189 ; CHECK: br %r14
190190 entry:
191191 %add = fadd float %a, %b
209209 ; CHECK-NEXT: sebr %f4, %f0
210210 ; CHECK-NEXT: ste %f4, 0(%r2)
211211 ; CHECK-NEXT: ltebr %f0, %f0
212 ; CHECK-NEXT: je .L{{.*}}
212 ; CHECK-NEXT: ber %r14
213213 ; CHECK: br %r14
214214 entry:
215215 %add = fadd float %a, %b
233233 ; CHECK-NEXT: #APP
234234 ; CHECK-NEXT: blah %f0
235235 ; CHECK-NEXT: #NO_APP
236 ; CHECK-NEXT: jl .L{{.*}}
236 ; CHECK-NEXT: blr %r14
237237 ; CHECK: br %r14
238238 entry:
239239 call void asm sideeffect "blah $0", "{f0}"(float %val)
255255 ; CHECK-NEXT: #APP
256256 ; CHECK-NEXT: blah %f0
257257 ; CHECK-NEXT: #NO_APP
258 ; CHECK-NEXT: jl .L{{.*}}
258 ; CHECK-NEXT: blr %r14
259259 ; CHECK: br %r14
260260 entry:
261261 call void asm sideeffect "blah $0", "{f0}"(double %val)
280280 ; CHECK-NEXT: mxbr
281281 ; CHECK-NEXT: std
282282 ; CHECK-NEXT: std
283 ; CHECK-NEXT: jl .L{{.*}}
283 ; CHECK-NEXT: blr %r14
284284 ; CHECK: br %r14
285285 entry:
286286 %val1 = load fp128 , fp128 *%ptr1
308308 ; CHECK-NEXT: #APP
309309 ; CHECK-NEXT: blah %f2
310310 ; CHECK-NEXT: #NO_APP
311 ; CHECK-NEXT: jl .L{{.*}}
311 ; CHECK-NEXT: blr %r14
312312 ; CHECK: br %r14
313313 entry:
314314 call void asm sideeffect "blah $0", "{f2}"(float %val)
331331 ; CHECK-NEXT: #APP
332332 ; CHECK-NEXT: blah %f2
333333 ; CHECK-NEXT: #NO_APP
334 ; CHECK-NEXT: jl .L{{.*}}
334 ; CHECK-NEXT: blr %r14
335335 ; CHECK: br %r14
336336 entry:
337337 call void asm sideeffect "blah $0", "{f2}"(double %val)
350350 define float @f17(float %a, float %b, float *%dest) {
351351 ; CHECK-LABEL: f17:
352352 ; CHECK: aebr %f0, %f2
353 ; CHECK-NEXT: jl .L{{.*}}
353 ; CHECK-NEXT: blr %r14
354354 ; CHECK: br %r14
355355 entry:
356356 %res = fadd float %a, %b
370370 define float @f18(float %dummy, float %a, float *%dest) {
371371 ; CHECK-LABEL: f18:
372372 ; CHECK: lnebr %f0, %f2
373 ; CHECK-NEXT: jl .L{{.*}}
373 ; CHECK-NEXT: blr %r14
374374 ; CHECK: br %r14
375375 entry:
376376 %abs = call float @llvm.fabs.f32(float %a)
390390 define float @f19(float %dummy, float %a, float *%dest) {
391391 ; CHECK-LABEL: f19:
392392 ; CHECK: lcebr %f0, %f2
393 ; CHECK-NEXT: jle .L{{.*}}
393 ; CHECK-NEXT: bler %r14
394394 ; CHECK: br %r14
395395 entry:
396396 %res = fsub float -0.0, %a
99 define float @f1(float %a, float %b, float %f) {
1010 ; CHECK-LABEL: f1:
1111 ; CHECK: lcebr
12 ; CHECK-NEXT: je
12 ; CHECK-NEXT: ber %r14
1313 %neg = fsub float -0.0, %f
1414 %cond = fcmp oeq float %neg, 0.0
1515 %res = select i1 %cond, float %a, float %b
2020 define double @f2(double %a, double %b, double %f) {
2121 ; CHECK-LABEL: f2:
2222 ; CHECK: lcdbr
23 ; CHECK-NEXT: je
23 ; CHECK-NEXT: ber %r14
2424 %neg = fsub double -0.0, %f
2525 %cond = fcmp oeq double %neg, 0.0
2626 %res = select i1 %cond, double %a, double %b
3333 define float @f3(float %a, float %b, float %f) {
3434 ; CHECK-LABEL: f3:
3535 ; CHECK: lnebr
36 ; CHECK-NEXT: je
36 ; CHECK-NEXT: ber %r14
3737 %abs = call float @llvm.fabs.f32(float %f)
3838 %neg = fsub float -0.0, %abs
3939 %cond = fcmp oeq float %neg, 0.0
4646 define double @f4(double %a, double %b, double %f) {
4747 ; CHECK-LABEL: f4:
4848 ; CHECK: lndbr
49 ; CHECK-NEXT: je
49 ; CHECK-NEXT: ber %r14
5050 %abs = call double @llvm.fabs.f64(double %f)
5151 %neg = fsub double -0.0, %abs
5252 %cond = fcmp oeq double %neg, 0.0
5959 define float @f5(float %a, float %b, float %f) {
6060 ; CHECK-LABEL: f5:
6161 ; CHECK: lpebr
62 ; CHECK-NEXT: je
62 ; CHECK-NEXT: ber %r14
6363 %abs = call float @llvm.fabs.f32(float %f)
6464 %cond = fcmp oeq float %abs, 0.0
6565 %res = select i1 %cond, float %a, float %b
7070 define double @f6(double %a, double %b, double %f) {
7171 ; CHECK-LABEL: f6:
7272 ; CHECK: lpdbr
73 ; CHECK-NEXT: je
73 ; CHECK-NEXT: ber %r14
7474 %abs = call double @llvm.fabs.f64(double %f)
7575 %cond = fcmp oeq double %abs, 0.0
7676 %res = select i1 %cond, double %a, double %b
3131 ; Like f2, but with a conditional store.
3232 define void @f3(float %val, i8 *%ptr, i32 %which) {
3333 ; CHECK-LABEL: f3:
34 ; CHECK: cijlh %r3, 0,
34 ; CHECK: ciblh %r3, 0, 0(%r14)
35
3536 ; CHECK: lgdr [[REG:%r[0-5]]], %f0
3637 ; CHECK: stch [[REG]], 0(%r2)
3738 ; CHECK: br %r14
4748 ; ...and again with 16-bit memory.
4849 define void @f4(float %val, i16 *%ptr, i32 %which) {
4950 ; CHECK-LABEL: f4:
50 ; CHECK: cijlh %r3, 0,
51 ; CHECK: ciblh %r3, 0, 0(%r14)
5152 ; CHECK: lgdr [[REG:%r[0-5]]], %f0
5253 ; CHECK: sthh [[REG]], 0(%r2)
5354 ; CHECK: br %r14
3030 ; Like f2, but with a conditional store.
3131 define void @f3(float %val, i8 *%ptr, i32 %which) {
3232 ; CHECK-LABEL: f3:
33 ; CHECK-DAG: cijlh %r3, 0,
33 ; CHECK-DAG: ciblh %r3, 0, 0(%r14)
3434 ; CHECK-DAG: vlgvf [[REG:%r[0-5]]], %v0, 0
3535 ; CHECK: stc [[REG]], 0(%r2)
3636 ; CHECK: br %r14
4646 ; ...and again with 16-bit memory.
4747 define void @f4(float %val, i16 *%ptr, i32 %which) {
4848 ; CHECK-LABEL: f4:
49 ; CHECK-DAG: cijlh %r3, 0,
49 ; CHECK-DAG: ciblh %r3, 0, 0(%r14)
5050 ; CHECK-DAG: vlgvf [[REG:%r[0-5]]], %v0, 0
5151 ; CHECK: sth [[REG]], 0(%r2)
5252 ; CHECK: br %r14
158158 ; CHECK-LABEL: f8:
159159 ; CHECK: sqebr %f0, %f2
160160 ; CHECK: cebr %f0, %f0
161 ; CHECK: jo [[LABEL:\.L.*]]
162 ; CHECK: br %r14
163 ; CHECK: [[LABEL]]:
161 ; CHECK: bnor %r14
164162 ; CHECK: ler %f0, %f2
165163 ; CHECK: jg sqrtf@PLT
166164 %res = tail call float @sqrtf(float %val)
160160 ; CHECK-LABEL: f8:
161161 ; CHECK: sqdbr %f0, %f2
162162 ; CHECK: cdbr %f0, %f0
163 ; CHECK: jo [[LABEL:\.L.*]]
164 ; CHECK: br %r14
165 ; CHECK: [[LABEL]]:
163 ; CHECK: bnor %r14
166164 ; CHECK: ldr %f0, %f2
167165 ; CHECK: jg sqrt@PLT
168166 %res = tail call double @sqrt(double %val)
6666 ; CHECK-NOT: stmg
6767 ; CHECK-NOT: std
6868 ; CHECK: tbegin 0, 65292
69 ; CHECK: jnh {{\.L*}}
69 ; CHECK: bnhr %r14
7070 ; CHECK: mvhi 0(%r2), 0
7171 ; CHECK: br %r14
7272 %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
8989 ; CHECK: tbegin 0, 65292
9090 ; CHECK: ipm %r2
9191 ; CHECK: srl %r2, 28
92 ; CHECK: cijlh %r2, 2, {{\.L*}}
92 ; CHECK: ciblh %r2, 2, 0(%r14)
9393 ; CHECK: mvhi 0(%r3), 0
9494 ; CHECK: br %r14
9595 %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
197197 define void @test_tend3(i32 *%ptr) {
198198 ; CHECK-LABEL: test_tend3:
199199 ; CHECK: tend
200 ; CHECK: je {{\.L*}}
200 ; CHECK: ber %r14
201201 ; CHECK: mvhi 0(%r2), 0
202202 ; CHECK: br %r14
203203 %res = call i32 @llvm.s390.tend()
218218 ; CHECK: tend
219219 ; CHECK: ipm %r2
220220 ; CHECK: srl %r2, 28
221 ; CHECK: cijlh %r2, 2, {{\.L*}}
221 ; CHECK: ciblh %r2, 2, 0(%r14)
222222 ; CHECK: mvhi 0(%r3), 0
223223 ; CHECK: br %r14
224224 %res = call i32 @llvm.s390.tend()
153153 define double @f11(double %a, double %b, i32 %rhs, i16 *%src) {
154154 ; CHECK-LABEL: f11:
155155 ; CHECK: ch %r2, 0(%r3)
156 ; CHECK-NEXT: jh {{\.L.*}}
156 ; CHECK-NEXT: bhr %r14
157157 ; CHECK: ldr %f0, %f2
158158 ; CHECK: br %r14
159159 %half = load i16 , i16 *%src
66 ; Check register comparison.
77 define double @f1(double %a, double %b, i32 %i1, i32 %i2) {
88 ; CHECK-LABEL: f1:
9 ; CHECK: crjl %r2, %r3
9 ; CHECK: crbl %r2, %r3, 0(%r14)
1010 ; CHECK: ldr %f0, %f2
1111 ; CHECK: br %r14
1212 %cond = icmp slt i32 %i1, %i2
1818 define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) {
1919 ; CHECK-LABEL: f2:
2020 ; CHECK: c %r2, 0(%r3)
21 ; CHECK-NEXT: jl
21 ; CHECK-NEXT: blr %r14
2222 ; CHECK: ldr %f0, %f2
2323 ; CHECK: br %r14
2424 %i2 = load i32 , i32 *%ptr
3131 define double @f3(double %a, double %b, i32 %i1, i32 *%base) {
3232 ; CHECK-LABEL: f3:
3333 ; CHECK: c %r2, 4092(%r3)
34 ; CHECK-NEXT: jl
34 ; CHECK-NEXT: blr %r14
3535 ; CHECK: ldr %f0, %f2
3636 ; CHECK: br %r14
3737 %ptr = getelementptr i32, i32 *%base, i64 1023
4545 define double @f4(double %a, double %b, i32 %i1, i32 *%base) {
4646 ; CHECK-LABEL: f4:
4747 ; CHECK: cy %r2, 4096(%r3)
48 ; CHECK-NEXT: jl
48 ; CHECK-NEXT: blr %r14
4949 ; CHECK: ldr %f0, %f2
5050 ; CHECK: br %r14
5151 %ptr = getelementptr i32, i32 *%base, i64 1024
5959 define double @f5(double %a, double %b, i32 %i1, i32 *%base) {
6060 ; CHECK-LABEL: f5:
6161 ; CHECK: cy %r2, 524284(%r3)
62 ; CHECK-NEXT: jl
62 ; CHECK-NEXT: blr %r14
6363 ; CHECK: ldr %f0, %f2
6464 ; CHECK: br %r14
6565 %ptr = getelementptr i32, i32 *%base, i64 131071
7575 ; CHECK-LABEL: f6:
7676 ; CHECK: agfi %r3, 524288
7777 ; CHECK: c %r2, 0(%r3)
78 ; CHECK-NEXT: jl
78 ; CHECK-NEXT: blr %r14
7979 ; CHECK: ldr %f0, %f2
8080 ; CHECK: br %r14
8181 %ptr = getelementptr i32, i32 *%base, i64 131072
8989 define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
9090 ; CHECK-LABEL: f7:
9191 ; CHECK: cy %r2, -4(%r3)
92 ; CHECK-NEXT: jl
92 ; CHECK-NEXT: blr %r14
9393 ; CHECK: ldr %f0, %f2
9494 ; CHECK: br %r14
9595 %ptr = getelementptr i32, i32 *%base, i64 -1
103103 define double @f8(double %a, double %b, i32 %i1, i32 *%base) {
104104 ; CHECK-LABEL: f8:
105105 ; CHECK: cy %r2, -524288(%r3)
106 ; CHECK-NEXT: jl
106 ; CHECK-NEXT: blr %r14
107107 ; CHECK: ldr %f0, %f2
108108 ; CHECK: br %r14
109109 %ptr = getelementptr i32, i32 *%base, i64 -131072
119119 ; CHECK-LABEL: f9:
120120 ; CHECK: agfi %r3, -524292
121121 ; CHECK: c %r2, 0(%r3)
122 ; CHECK-NEXT: jl
122 ; CHECK-NEXT: blr %r14
123123 ; CHECK: ldr %f0, %f2
124124 ; CHECK: br %r14
125125 %ptr = getelementptr i32, i32 *%base, i64 -131073
133133 define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
134134 ; CHECK-LABEL: f10:
135135 ; CHECK: c %r2, 4092({{%r4,%r3|%r3,%r4}})
136 ; CHECK-NEXT: jl
136 ; CHECK-NEXT: blr %r14
137137 ; CHECK: ldr %f0, %f2
138138 ; CHECK: br %r14
139139 %add1 = add i64 %base, %index
149149 define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
150150 ; CHECK-LABEL: f11:
151151 ; CHECK: cy %r2, 4096({{%r4,%r3|%r3,%r4}})
152 ; CHECK-NEXT: jl
152 ; CHECK-NEXT: blr %r14
153153 ; CHECK: ldr %f0, %f2
154154 ; CHECK: br %r14
155155 %add1 = add i64 %base, %index
185185 define double @f13(double %a, double %b, i32 %i2, i32 *%ptr) {
186186 ; CHECK-LABEL: f13:
187187 ; CHECK: c %r2, 0(%r3)
188 ; CHECK-NEXT: jh {{\.L.*}}
188 ; CHECK-NEXT: bhr %r14
189189 ; CHECK: ldr %f0, %f2
190190 ; CHECK: br %r14
191191 %i1 = load i32 , i32 *%ptr
44 ; Check register comparison.
55 define double @f1(double %a, double %b, i32 %i1, i32 %i2) {
66 ; CHECK-LABEL: f1:
7 ; CHECK: clrjl %r2, %r3
7 ; CHECK: clrbl %r2, %r3, 0(%r14)
88 ; CHECK: ldr %f0, %f2
99 ; CHECK: br %r14
1010 %cond = icmp ult i32 %i1, %i2
1616 define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) {
1717 ; CHECK-LABEL: f2:
1818 ; CHECK: cl %r2, 0(%r3)
19 ; CHECK-NEXT: jl
19 ; CHECK-NEXT: blr %r14
2020 ; CHECK: ldr %f0, %f2
2121 ; CHECK: br %r14
2222 %i2 = load i32 , i32 *%ptr
2929 define double @f3(double %a, double %b, i32 %i1, i32 *%base) {
3030 ; CHECK-LABEL: f3:
3131 ; CHECK: cl %r2, 4092(%r3)
32 ; CHECK-NEXT: jl
32 ; CHECK-NEXT: blr %r14
3333 ; CHECK: ldr %f0, %f2
3434 ; CHECK: br %r14
3535 %ptr = getelementptr i32, i32 *%base, i64 1023
4343 define double @f4(double %a, double %b, i32 %i1, i32 *%base) {
4444 ; CHECK-LABEL: f4:
4545 ; CHECK: cly %r2, 4096(%r3)
46 ; CHECK-NEXT: jl
46 ; CHECK-NEXT: blr %r14
4747 ; CHECK: ldr %f0, %f2
4848 ; CHECK: br %r14
4949 %ptr = getelementptr i32, i32 *%base, i64 1024
5757 define double @f5(double %a, double %b, i32 %i1, i32 *%base) {
5858 ; CHECK-LABEL: f5:
5959 ; CHECK: cly %r2, 524284(%r3)
60 ; CHECK-NEXT: jl
60 ; CHECK-NEXT: blr %r14
6161 ; CHECK: ldr %f0, %f2
6262 ; CHECK: br %r14
6363 %ptr = getelementptr i32, i32 *%base, i64 131071
7373 ; CHECK-LABEL: f6:
7474 ; CHECK: agfi %r3, 524288
7575 ; CHECK: cl %r2, 0(%r3)
76 ; CHECK-NEXT: jl
76 ; CHECK-NEXT: blr %r14
7777 ; CHECK: ldr %f0, %f2
7878 ; CHECK: br %r14
7979 %ptr = getelementptr i32, i32 *%base, i64 131072
8787 define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
8888 ; CHECK-LABEL: f7:
8989 ; CHECK: cly %r2, -4(%r3)
90 ; CHECK-NEXT: jl
90 ; CHECK-NEXT: blr %r14
9191 ; CHECK: ldr %f0, %f2
9292 ; CHECK: br %r14
9393 %ptr = getelementptr i32, i32 *%base, i64 -1
101101 define double @f8(double %a, double %b, i32 %i1, i32 *%base) {
102102 ; CHECK-LABEL: f8:
103103 ; CHECK: cly %r2, -524288(%r3)
104 ; CHECK-NEXT: jl
104 ; CHECK-NEXT: blr %r14
105105 ; CHECK: ldr %f0, %f2
106106 ; CHECK: br %r14
107107 %ptr = getelementptr i32, i32 *%base, i64 -131072
117117 ; CHECK-LABEL: f9:
118118 ; CHECK: agfi %r3, -524292
119119 ; CHECK: cl %r2, 0(%r3)
120 ; CHECK-NEXT: jl
120 ; CHECK-NEXT: blr %r14
121121 ; CHECK: ldr %f0, %f2
122122 ; CHECK: br %r14
123123 %ptr = getelementptr i32, i32 *%base, i64 -131073
131131 define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
132132 ; CHECK-LABEL: f10:
133133 ; CHECK: cl %r2, 4092({{%r4,%r3|%r3,%r4}})
134 ; CHECK-NEXT: jl
134 ; CHECK-NEXT: blr %r14
135135 ; CHECK: ldr %f0, %f2
136136 ; CHECK: br %r14
137137 %add1 = add i64 %base, %index
147147 define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
148148 ; CHECK-LABEL: f11:
149149 ; CHECK: cly %r2, 4096({{%r4,%r3|%r3,%r4}})
150 ; CHECK-NEXT: jl
150 ; CHECK-NEXT: blr %r14
151151 ; CHECK: ldr %f0, %f2
152152 ; CHECK: br %r14
153153 %add1 = add i64 %base, %index
163163 define double @f12(double %a, double %b, i32 %i2, i32 *%ptr) {
164164 ; CHECK-LABEL: f12:
165165 ; CHECK: cl %r2, 0(%r3)
166 ; CHECK-NEXT: jh {{\.L.*}}
166 ; CHECK-NEXT: bhr %r14
167167 ; CHECK: ldr %f0, %f2
168168 ; CHECK: br %r14
169169 %i1 = load i32 , i32 *%ptr
109109 define double @f8(double %a, double %b, i64 %rhs, i16 *%src) {
110110 ; CHECK-LABEL: f8:
111111 ; CHECK: cgh %r2, 0(%r3)
112 ; CHECK-NEXT: jh {{\.L.*}}
112 ; CHECK-NEXT: bhr %r14
113113 ; CHECK: ldr %f0, %f2
114114 ; CHECK: br %r14
115115 %half = load i16 , i16 *%src
77 define double @f1(double %a, double %b, i64 %i1, i32 %unext) {
88 ; CHECK-LABEL: f1:
99 ; CHECK: cgfr %r2, %r3
10 ; CHECK-NEXT: jl
10 ; CHECK-NEXT: blr %r14
1111 ; CHECK: ldr %f0, %f2
1212 ; CHECK: br %r14
1313 %i2 = sext i32 %unext to i64
3131 define double @f3(double %a, double %b, i64 %i1, i32 %unext) {
3232 ; CHECK-LABEL: f3:
3333 ; CHECK: cgfr %r2, %r3
34 ; CHECK-NEXT: je
34 ; CHECK-NEXT: ber %r14
3535 ; CHECK: ldr %f0, %f2
3636 ; CHECK: br %r14
3737 %i2 = sext i32 %unext to i64
4444 define double @f4(double %a, double %b, i64 %i1, i32 %unext) {
4545 ; CHECK-LABEL: f4:
4646 ; CHECK: cgfr %r2, %r3
47 ; CHECK-NEXT: jlh
47 ; CHECK-NEXT: blhr %r14
4848 ; CHECK: ldr %f0, %f2
4949 ; CHECK: br %r14
5050 %i2 = sext i32 %unext to i64
5757 define double @f5(double %a, double %b, i64 %i1, i32 *%ptr) {
5858 ; CHECK-LABEL: f5:
5959 ; CHECK: cgf %r2, 0(%r3)
60 ; CHECK-NEXT: jl
60 ; CHECK-NEXT: blr %r14
6161 ; CHECK: ldr %f0, %f2
6262 ; CHECK: br %r14
6363 %unext = load i32 , i32 *%ptr
8383 define double @f7(double %a, double %b, i64 %i1, i32 *%ptr) {
8484 ; CHECK-LABEL: f7:
8585 ; CHECK: cgf %r2, 0(%r3)
86 ; CHECK-NEXT: je
86 ; CHECK-NEXT: ber %r14
8787 ; CHECK: ldr %f0, %f2
8888 ; CHECK: br %r14
8989 %unext = load i32 , i32 *%ptr
9797 define double @f8(double %a, double %b, i64 %i1, i32 *%ptr) {
9898 ; CHECK-LABEL: f8:
9999 ; CHECK: cgf %r2, 0(%r3)
100 ; CHECK-NEXT: jlh
100 ; CHECK-NEXT: blhr %r14
101101 ; CHECK: ldr %f0, %f2
102102 ; CHECK: br %r14
103103 %unext = load i32 , i32 *%ptr
111111 define double @f9(double %a, double %b, i64 %i1, i32 *%base) {
112112 ; CHECK-LABEL: f9:
113113 ; CHECK: cgf %r2, 524284(%r3)
114 ; CHECK-NEXT: jl
114 ; CHECK-NEXT: blr %r14
115115 ; CHECK: ldr %f0, %f2
116116 ; CHECK: br %r14
117117 %ptr = getelementptr i32, i32 *%base, i64 131071
128128 ; CHECK-LABEL: f10:
129129 ; CHECK: agfi %r3, 524288
130130 ; CHECK: cgf %r2, 0(%r3)
131 ; CHECK-NEXT: jl
131 ; CHECK-NEXT: blr %r14
132132 ; CHECK: ldr %f0, %f2
133133 ; CHECK: br %r14
134134 %ptr = getelementptr i32, i32 *%base, i64 131072
143143 define double @f11(double %a, double %b, i64 %i1, i32 *%base) {
144144 ; CHECK-LABEL: f11:
145145 ; CHECK: cgf %r2, -4(%r3)
146 ; CHECK-NEXT: jl
146 ; CHECK-NEXT: blr %r14
147147 ; CHECK: ldr %f0, %f2
148148 ; CHECK: br %r14
149149 %ptr = getelementptr i32, i32 *%base, i64 -1
158158 define double @f12(double %a, double %b, i64 %i1, i32 *%base) {
159159 ; CHECK-LABEL: f12:
160160 ; CHECK: cgf %r2, -524288(%r3)
161 ; CHECK-NEXT: jl
161 ; CHECK-NEXT: blr %r14
162162 ; CHECK: ldr %f0, %f2
163163 ; CHECK: br %r14
164164 %ptr = getelementptr i32, i32 *%base, i64 -131072
175175 ; CHECK-LABEL: f13:
176176 ; CHECK: agfi %r3, -524292
177177 ; CHECK: cgf %r2, 0(%r3)
178 ; CHECK-NEXT: jl
178 ; CHECK-NEXT: blr %r14
179179 ; CHECK: ldr %f0, %f2
180180 ; CHECK: br %r14
181181 %ptr = getelementptr i32, i32 *%base, i64 -131073
190190 define double @f14(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
191191 ; CHECK-LABEL: f14:
192192 ; CHECK: cgf %r2, 524284({{%r4,%r3|%r3,%r4}})
193 ; CHECK-NEXT: jl
193 ; CHECK-NEXT: blr %r14
194194 ; CHECK: ldr %f0, %f2
195195 ; CHECK: br %r14
196196 %add1 = add i64 %base, %index
294294 define double @f16(double %a, double %b, i64 %i1, i32 %unext) {
295295 ; CHECK-LABEL: f16:
296296 ; CHECK: cgfr %r2, %r3
297 ; CHECK-NEXT: jh
297 ; CHECK-NEXT: bhr %r14
298298 ; CHECK: ldr %f0, %f2
299299 ; CHECK: br %r14
300300 %i2 = sext i32 %unext to i64
307307 define double @f17(double %a, double %b, i64 %i2, i32 *%ptr) {
308308 ; CHECK-LABEL: f17:
309309 ; CHECK: cgf %r2, 0(%r3)
310 ; CHECK-NEXT: jh {{\.L.*}}
310 ; CHECK-NEXT: bhr %r14
311311 ; CHECK: ldr %f0, %f2
312312 ; CHECK: br %r14
313313 %unext = load i32 , i32 *%ptr
77 define double @f1(double %a, double %b, i64 %i1, i32 %unext) {
88 ; CHECK-LABEL: f1:
99 ; CHECK: clgfr %r2, %r3
10 ; CHECK-NEXT: jl
10 ; CHECK-NEXT: blr %r14
1111 ; CHECK: ldr %f0, %f2
1212 ; CHECK: br %r14
1313 %i2 = zext i32 %unext to i64
2020 define double @f2(double %a, double %b, i64 %i1, i64 %unext) {
2121 ; CHECK-LABEL: f2:
2222 ; CHECK: clgfr %r2, %r3
23 ; CHECK-NEXT: jl
23 ; CHECK-NEXT: blr %r14
2424 ; CHECK: ldr %f0, %f2
2525 ; CHECK: br %r14
2626 %i2 = and i64 %unext, 4294967295
5555 define double @f5(double %a, double %b, i64 %i1, i32 %unext) {
5656 ; CHECK-LABEL: f5:
5757 ; CHECK: clgfr %r2, %r3
58 ; CHECK-NEXT: je
58 ; CHECK-NEXT: ber %r14
5959 ; CHECK: ldr %f0, %f2
6060 ; CHECK: br %r14
6161 %i2 = zext i32 %unext to i64
6868 define double @f6(double %a, double %b, i64 %i1, i64 %unext) {
6969 ; CHECK-LABEL: f6:
7070 ; CHECK: clgfr %r2, %r3
71 ; CHECK-NEXT: je
71 ; CHECK-NEXT: ber %r14
7272 ; CHECK: ldr %f0, %f2
7373 ; CHECK: br %r14
7474 %i2 = and i64 %unext, 4294967295
8181 define double @f7(double %a, double %b, i64 %i1, i32 %unext) {
8282 ; CHECK-LABEL: f7:
8383 ; CHECK: clgfr %r2, %r3
84 ; CHECK-NEXT: jlh
84 ; CHECK-NEXT: blhr %r14
8585 ; CHECK: ldr %f0, %f2
8686 ; CHECK: br %r14
8787 %i2 = zext i32 %unext to i64
9494 define double @f8(double %a, double %b, i64 %i1, i64 %unext) {
9595 ; CHECK-LABEL: f8:
9696 ; CHECK: clgfr %r2, %r3
97 ; CHECK-NEXT: jlh
97 ; CHECK-NEXT: blhr %r14
9898 ; CHECK: ldr %f0, %f2
9999 ; CHECK: br %r14
100100 %i2 = and i64 %unext, 4294967295
107107 define double @f9(double %a, double %b, i64 %i1, i32 *%ptr) {
108108 ; CHECK-LABEL: f9:
109109 ; CHECK: clgf %r2, 0(%r3)
110 ; CHECK-NEXT: jl
110 ; CHECK-NEXT: blr %r14
111111 ; CHECK: ldr %f0, %f2
112112 ; CHECK: br %r14
113113 %unext = load i32 , i32 *%ptr
133133 define double @f11(double %a, double %b, i64 %i1, i32 *%ptr) {
134134 ; CHECK-LABEL: f11:
135135 ; CHECK: clgf %r2, 0(%r3)
136 ; CHECK-NEXT: je
136 ; CHECK-NEXT: ber %r14
137137 ; CHECK: ldr %f0, %f2
138138 ; CHECK: br %r14
139139 %unext = load i32 , i32 *%ptr
147147 define double @f12(double %a, double %b, i64 %i1, i32 *%ptr) {
148148 ; CHECK-LABEL: f12:
149149 ; CHECK: clgf %r2, 0(%r3)
150 ; CHECK-NEXT: jlh
150 ; CHECK-NEXT: blhr %r14
151151 ; CHECK: ldr %f0, %f2
152152 ; CHECK: br %r14
153153 %unext = load i32 , i32 *%ptr
161161 define double @f13(double %a, double %b, i64 %i1, i32 *%base) {
162162 ; CHECK-LABEL: f13:
163163 ; CHECK: clgf %r2, 524284(%r3)
164 ; CHECK-NEXT: jl
164 ; CHECK-NEXT: blr %r14
165165 ; CHECK: ldr %f0, %f2
166166 ; CHECK: br %r14
167167 %ptr = getelementptr i32, i32 *%base, i64 131071
178178 ; CHECK-LABEL: f14:
179179 ; CHECK: agfi %r3, 524288
180180 ; CHECK: clgf %r2, 0(%r3)
181 ; CHECK-NEXT: jl
181 ; CHECK-NEXT: blr %r14
182182 ; CHECK: ldr %f0, %f2
183183 ; CHECK: br %r14
184184 %ptr = getelementptr i32, i32 *%base, i64 131072
193193 define double @f15(double %a, double %b, i64 %i1, i32 *%base) {
194194 ; CHECK-LABEL: f15:
195195 ; CHECK: clgf %r2, -4(%r3)
196 ; CHECK-NEXT: jl
196 ; CHECK-NEXT: blr %r14
197197 ; CHECK: ldr %f0, %f2
198198 ; CHECK: br %r14
199199 %ptr = getelementptr i32, i32 *%base, i64 -1
208208 define double @f16(double %a, double %b, i64 %i1, i32 *%base) {
209209 ; CHECK-LABEL: f16:
210210 ; CHECK: clgf %r2, -524288(%r3)
211 ; CHECK-NEXT: jl
211 ; CHECK-NEXT: blr %r14
212212 ; CHECK: ldr %f0, %f2
213213 ; CHECK: br %r14
214214 %ptr = getelementptr i32, i32 *%base, i64 -131072
225225 ; CHECK-LABEL: f17:
226226 ; CHECK: agfi %r3, -524292
227227 ; CHECK: clgf %r2, 0(%r3)
228 ; CHECK-NEXT: jl
228 ; CHECK-NEXT: blr %r14
229229 ; CHECK: ldr %f0, %f2
230230 ; CHECK: br %r14
231231 %ptr = getelementptr i32, i32 *%base, i64 -131073
240240 define double @f18(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
241241 ; CHECK-LABEL: f18:
242242 ; CHECK: clgf %r2, 524284({{%r4,%r3|%r3,%r4}})
243 ; CHECK-NEXT: jl
243 ; CHECK-NEXT: blr %r14
244244 ; CHECK: ldr %f0, %f2
245245 ; CHECK: br %r14
246246 %add1 = add i64 %base, %index
344344 define double @f20(double %a, double %b, i64 %i1, i32 %unext) {
345345 ; CHECK-LABEL: f20:
346346 ; CHECK: clgfr %r2, %r3
347 ; CHECK-NEXT: jh
347 ; CHECK-NEXT: bhr %r14
348348 ; CHECK: ldr %f0, %f2
349349 ; CHECK: br %r14
350350 %i2 = zext i32 %unext to i64
357357 define double @f21(double %a, double %b, i64 %i1, i64 %unext) {
358358 ; CHECK-LABEL: f21:
359359 ; CHECK: clgfr %r2, %r3
360 ; CHECK-NEXT: jh
360 ; CHECK-NEXT: bhr %r14
361361 ; CHECK: ldr %f0, %f2
362362 ; CHECK: br %r14
363363 %i2 = and i64 %unext, 4294967295
370370 define double @f22(double %a, double %b, i64 %i2, i32 *%ptr) {
371371 ; CHECK-LABEL: f22:
372372 ; CHECK: clgf %r2, 0(%r3)
373 ; CHECK-NEXT: jh {{\.L.*}}
373 ; CHECK-NEXT: bhr %r14
374374 ; CHECK: ldr %f0, %f2
375375 ; CHECK: br %r14
376376 %unext = load i32 , i32 *%ptr
44 ; Check CGR.
55 define double @f1(double %a, double %b, i64 %i1, i64 %i2) {
66 ; CHECK-LABEL: f1:
7 ; CHECK: cgrjl %r2, %r3
7 ; CHECK: cgrbl %r2, %r3, 0(%r14)
88 ; CHECK: ldr %f0, %f2
99 ; CHECK: br %r14
1010 %cond = icmp slt i64 %i1, %i2
1616 define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) {
1717 ; CHECK-LABEL: f2:
1818 ; CHECK: cg %r2, 0(%r3)
19 ; CHECK-NEXT: jl
19 ; CHECK-NEXT: blr %r14
2020 ; CHECK: ldr %f0, %f2
2121 ; CHECK: br %r14
2222 %i2 = load i64 , i64 *%ptr
2929 define double @f3(double %a, double %b, i64 %i1, i64 *%base) {
3030 ; CHECK-LABEL: f3:
3131 ; CHECK: cg %r2, 524280(%r3)
32 ; CHECK-NEXT: jl
32 ; CHECK-NEXT: blr %r14
3333 ; CHECK: ldr %f0, %f2
3434 ; CHECK: br %r14
3535 %ptr = getelementptr i64, i64 *%base, i64 65535
4545 ; CHECK-LABEL: f4:
4646 ; CHECK: agfi %r3, 524288
4747 ; CHECK: cg %r2, 0(%r3)
48 ; CHECK-NEXT: jl
48 ; CHECK-NEXT: blr %r14
4949 ; CHECK: ldr %f0, %f2
5050 ; CHECK: br %r14
5151 %ptr = getelementptr i64, i64 *%base, i64 65536
5959 define double @f5(double %a, double %b, i64 %i1, i64 *%base) {
6060 ; CHECK-LABEL: f5:
6161 ; CHECK: cg %r2, -8(%r3)
62 ; CHECK-NEXT: jl
62 ; CHECK-NEXT: blr %r14
6363 ; CHECK: ldr %f0, %f2
6464 ; CHECK: br %r14
6565 %ptr = getelementptr i64, i64 *%base, i64 -1
7373 define double @f6(double %a, double %b, i64 %i1, i64 *%base) {
7474 ; CHECK-LABEL: f6:
7575 ; CHECK: cg %r2, -524288(%r3)
76 ; CHECK-NEXT: jl
76 ; CHECK-NEXT: blr %r14
7777 ; CHECK: ldr %f0, %f2
7878 ; CHECK: br %r14
7979 %ptr = getelementptr i64, i64 *%base, i64 -65536
8989 ; CHECK-LABEL: f7:
9090 ; CHECK: agfi %r3, -524296
9191 ; CHECK: cg %r2, 0(%r3)
92 ; CHECK-NEXT: jl
92 ; CHECK-NEXT: blr %r14
9393 ; CHECK: ldr %f0, %f2
9494 ; CHECK: br %r14
9595 %ptr = getelementptr i64, i64 *%base, i64 -65537
103103 define double @f8(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
104104 ; CHECK-LABEL: f8:
105105 ; CHECK: cg %r2, 524280({{%r4,%r3|%r3,%r4}})
106 ; CHECK-NEXT: jl
106 ; CHECK-NEXT: blr %r14
107107 ; CHECK: ldr %f0, %f2
108108 ; CHECK: br %r14
109109 %add1 = add i64 %base, %index
119119 define double @f9(double %a, double %b, i64 %i2, i64 *%ptr) {
120120 ; CHECK-LABEL: f9:
121121 ; CHECK: cg %r2, 0(%r3)
122 ; CHECK-NEXT: jh {{\.L.*}}
122 ; CHECK-NEXT: bhr %r14
123123 ; CHECK: ldr %f0, %f2
124124 ; CHECK: br %r14
125125 %i1 = load i64 , i64 *%ptr
44 ; Check CLGR.
55 define double @f1(double %a, double %b, i64 %i1, i64 %i2) {
66 ; CHECK-LABEL: f1:
7 ; CHECK: clgrjl %r2, %r3
7 ; CHECK: clgrbl %r2, %r3, 0(%r14)
88 ; CHECK: ldr %f0, %f2
99 ; CHECK: br %r14
1010 %cond = icmp ult i64 %i1, %i2
1616 define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) {
1717 ; CHECK-LABEL: f2:
1818 ; CHECK: clg %r2, 0(%r3)
19 ; CHECK-NEXT: jl
19 ; CHECK-NEXT: blr %r14
2020 ; CHECK: ldr %f0, %f2
2121 ; CHECK: br %r14
2222 %i2 = load i64 , i64 *%ptr
2929 define double @f3(double %a, double %b, i64 %i1, i64 *%base) {
3030 ; CHECK-LABEL: f3:
3131 ; CHECK: clg %r2, 524280(%r3)
32 ; CHECK-NEXT: jl
32 ; CHECK-NEXT: blr %r14
3333 ; CHECK: ldr %f0, %f2
3434 ; CHECK: br %r14
3535 %ptr = getelementptr i64, i64 *%base, i64 65535
4545 ; CHECK-LABEL: f4:
4646 ; CHECK: agfi %r3, 524288
4747 ; CHECK: clg %r2, 0(%r3)
48 ; CHECK-NEXT: jl
48 ; CHECK-NEXT: blr %r14
4949 ; CHECK: ldr %f0, %f2
5050 ; CHECK: br %r14
5151 %ptr = getelementptr i64, i64 *%base, i64 65536
5959 define double @f5(double %a, double %b, i64 %i1, i64 *%base) {
6060 ; CHECK-LABEL: f5:
6161 ; CHECK: clg %r2, -8(%r3)
62 ; CHECK-NEXT: jl
62 ; CHECK-NEXT: blr %r14
6363 ; CHECK: ldr %f0, %f2
6464 ; CHECK: br %r14
6565 %ptr = getelementptr i64, i64 *%base, i64 -1
7373 define double @f6(double %a, double %b, i64 %i1, i64 *%base) {
7474 ; CHECK-LABEL: f6:
7575 ; CHECK: clg %r2, -524288(%r3)
76 ; CHECK-NEXT: jl
76 ; CHECK-NEXT: blr %r14
7777 ; CHECK: ldr %f0, %f2
7878 ; CHECK: br %r14
7979 %ptr = getelementptr i64, i64 *%base, i64 -65536
8989 ; CHECK-LABEL: f7:
9090 ; CHECK: agfi %r3, -524296
9191 ; CHECK: clg %r2, 0(%r3)
92 ; CHECK-NEXT: jl
92 ; CHECK-NEXT: blr %r14
9393 ; CHECK: ldr %f0, %f2
9494 ; CHECK: br %r14
9595 %ptr = getelementptr i64, i64 *%base, i64 -65537
103103 define double @f8(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
104104 ; CHECK-LABEL: f8:
105105 ; CHECK: clg %r2, 524280({{%r4,%r3|%r3,%r4}})
106 ; CHECK-NEXT: jl
106 ; CHECK-NEXT: blr %r14
107107 ; CHECK: ldr %f0, %f2
108108 ; CHECK: br %r14
109109 %add1 = add i64 %base, %index
119119 define double @f9(double %a, double %b, i64 %i2, i64 *%ptr) {
120120 ; CHECK-LABEL: f9:
121121 ; CHECK: clg %r2, 0(%r3)
122 ; CHECK-NEXT: jh {{\.L.*}}
122 ; CHECK-NEXT: bhr %r14
123123 ; CHECK: ldr %f0, %f2
124124 ; CHECK: br %r14
125125 %i1 = load i64 , i64 *%ptr
88 ; CHECK: ldr %f0, %f2
99 ; CHECK: br %r14
1010 %cond = icmp slt i32 %i1, 0
11 %res = select i1 %cond, double %a, double %b
11 %tmp = select i1 %cond, double %a, double %b
12 %res = fadd double %tmp, 1.0
1213 ret double %res
1314 }
1415
1920 ; CHECK: ldr %f0, %f2
2021 ; CHECK: br %r14
2122 %cond = icmp slt i32 %i1, 2
22 %res = select i1 %cond, double %a, double %b
23 %tmp = select i1 %cond, double %a, double %b
24 %res = fadd double %tmp, 1.0
2325 ret double %res
2426 }
2527
3032 ; CHECK: ldr %f0, %f2
3133 ; CHECK: br %r14
3234 %cond = icmp slt i32 %i1, 127
33 %res = select i1 %cond, double %a, double %b
35 %tmp = select i1 %cond, double %a, double %b
36 %res = fadd double %tmp, 1.0
3437 ret double %res
3538 }
3639
4245 ; CHECK: ldr %f0, %f2
4346 ; CHECK: br %r14
4447 %cond = icmp slt i32 %i1, 128
45 %res = select i1 %cond, double %a, double %b
48 %tmp = select i1 %cond, double %a, double %b
49 %res = fadd double %tmp, 1.0
4650 ret double %res
4751 }
4852
5458 ; CHECK: ldr %f0, %f2
5559 ; CHECK: br %r14
5660 %cond = icmp slt i32 %i1, 32767
57 %res = select i1 %cond, double %a, double %b
61 %tmp = select i1 %cond, double %a, double %b
62 %res = fadd double %tmp, 1.0
5863 ret double %res
5964 }
6065
6671 ; CHECK: ldr %f0, %f2
6772 ; CHECK: br %r14
6873 %cond = icmp slt i32 %i1, 32768
69 %res = select i1 %cond, double %a, double %b
74 %tmp = select i1 %cond, double %a, double %b
75 %res = fadd double %tmp, 1.0
7076 ret double %res
7177 }
7278
7884 ; CHECK: ldr %f0, %f2
7985 ; CHECK: br %r14
8086 %cond = icmp eq i32 %i1, 2147483647
81 %res = select i1 %cond, double %a, double %b
87 %tmp = select i1 %cond, double %a, double %b
88 %res = fadd double %tmp, 1.0
8289 ret double %res
8390 }
8491
9097 ; CHECK: ldr %f0, %f2
9198 ; CHECK: br %r14
9299 %cond = icmp eq i32 %i1, 2147483648
93 %res = select i1 %cond, double %a, double %b
100 %tmp = select i1 %cond, double %a, double %b
101 %res = fadd double %tmp, 1.0
94102 ret double %res
95103 }
96104
101109 ; CHECK: ldr %f0, %f2
102110 ; CHECK: br %r14
103111 %cond = icmp slt i32 %i1, -1
104 %res = select i1 %cond, double %a, double %b
112 %tmp = select i1 %cond, double %a, double %b
113 %res = fadd double %tmp, 1.0
105114 ret double %res
106115 }
107116
112121 ; CHECK: ldr %f0, %f2
113122 ; CHECK: br %r14
114123 %cond = icmp slt i32 %i1, -128
115 %res = select i1 %cond, double %a, double %b
124 %tmp = select i1 %cond, double %a, double %b
125 %res = fadd double %tmp, 1.0
116126 ret double %res
117127 }
118128
124134 ; CHECK: ldr %f0, %f2
125135 ; CHECK: br %r14
126136 %cond = icmp slt i32 %i1, -129
127 %res = select i1 %cond, double %a, double %b
137 %tmp = select i1 %cond, double %a, double %b
138 %res = fadd double %tmp, 1.0
128139 ret double %res
129140 }
130141
136147 ; CHECK: ldr %f0, %f2
137148 ; CHECK: br %r14
138149 %cond = icmp slt i32 %i1, -32768
139 %res = select i1 %cond, double %a, double %b
150 %tmp = select i1 %cond, double %a, double %b
151 %res = fadd double %tmp, 1.0
140152 ret double %res
141153 }
142154
148160 ; CHECK: ldr %f0, %f2
149161 ; CHECK: br %r14
150162 %cond = icmp slt i32 %i1, -32769
151 %res = select i1 %cond, double %a, double %b
163 %tmp = select i1 %cond, double %a, double %b
164 %res = fadd double %tmp, 1.0
152165 ret double %res
153166 }
154167
160173 ; CHECK: ldr %f0, %f2
161174 ; CHECK: br %r14
162175 %cond = icmp eq i32 %i1, -2147483648
163 %res = select i1 %cond, double %a, double %b
176 %tmp = select i1 %cond, double %a, double %b
177 %res = fadd double %tmp, 1.0
164178 ret double %res
165179 }
166180
172186 ; CHECK: ldr %f0, %f2
173187 ; CHECK: br %r14
174188 %cond = icmp eq i32 %i1, -2147483649
175 %res = select i1 %cond, double %a, double %b
189 %tmp = select i1 %cond, double %a, double %b
190 %res = fadd double %tmp, 1.0
176191 ret double %res
177192 }
178193
183198 ; CHECK: ldr %f0, %f2
184199 ; CHECK: br %r14
185200 %cond = icmp slt i32 %i1, 1
186 %res = select i1 %cond, double %a, double %b
201 %tmp = select i1 %cond, double %a, double %b
202 %res = fadd double %tmp, 1.0
187203 ret double %res
188204 }
189205
194210 ; CHECK: ldr %f0, %f2
195211 ; CHECK: br %r14
196212 %cond = icmp sge i32 %i1, 1
197 %res = select i1 %cond, double %a, double %b
213 %tmp = select i1 %cond, double %a, double %b
214 %res = fadd double %tmp, 1.0
198215 ret double %res
199216 }
200217
205222 ; CHECK: ldr %f0, %f2
206223 ; CHECK: br %r14
207224 %cond = icmp sgt i32 %i1, -1
208 %res = select i1 %cond, double %a, double %b
225 %tmp = select i1 %cond, double %a, double %b
226 %res = fadd double %tmp, 1.0
209227 ret double %res
210228 }
211229
216234 ; CHECK: ldr %f0, %f2
217235 ; CHECK: br %r14
218236 %cond = icmp sle i32 %i1, -1
219 %res = select i1 %cond, double %a, double %b
220 ret double %res
221 }
237 %tmp = select i1 %cond, double %a, double %b
238 %res = fadd double %tmp, 1.0
239 ret double %res
240 }
99 ; CHECK: ldr %f0, %f2
1010 ; CHECK: br %r14
1111 %cond = icmp ugt i32 %i1, 1
12 %res = select i1 %cond, double %a, double %b
12 %tmp = select i1 %cond, double %a, double %b
13 %res = fadd double %tmp, 1.0
1314 ret double %res
1415 }
1516
2021 ; CHECK: ldr %f0, %f2
2122 ; CHECK: br %r14
2223 %cond = icmp ult i32 %i1, 255
23 %res = select i1 %cond, double %a, double %b
24 %tmp = select i1 %cond, double %a, double %b
25 %res = fadd double %tmp, 1.0
2426 ret double %res
2527 }
2628
3234 ; CHECK: ldr %f0, %f2
3335 ; CHECK: br %r14
3436 %cond = icmp ult i32 %i1, 256
35 %res = select i1 %cond, double %a, double %b
37 %tmp = select i1 %cond, double %a, double %b
38 %res = fadd double %tmp, 1.0
3639 ret double %res
3740 }
3841
4447 ; CHECK: ldr %f0, %f2
4548 ; CHECK: br %r14
4649 %cond = icmp ult i32 %i1, 4294967280
47 %res = select i1 %cond, double %a, double %b
50 %tmp = select i1 %cond, double %a, double %b
51 %res = fadd double %tmp, 1.0
4852 ret double %res
4953 }
88 ; CHECK: ldr %f0, %f2
99 ; CHECK: br %r14
1010 %cond = icmp slt i64 %i1, 0
11 %res = select i1 %cond, double %a, double %b
11 %tmp = select i1 %cond, double %a, double %b
12 %res = fadd double %tmp, 1.0
1213 ret double %res
1314 }
1415
1920 ; CHECK: ldr %f0, %f2
2021 ; CHECK: br %r14
2122 %cond = icmp slt i64 %i1, 1
22 %res = select i1 %cond, double %a, double %b
23 %tmp = select i1 %cond, double %a, double %b
24 %res = fadd double %tmp, 1.0
2325 ret double %res
2426 }
2527
3032 ; CHECK: ldr %f0, %f2
3133 ; CHECK: br %r14
3234 %cond = icmp slt i64 %i1, 127
33 %res = select i1 %cond, double %a, double %b
35 %tmp = select i1 %cond, double %a, double %b
36 %res = fadd double %tmp, 1.0
3437 ret double %res
3538 }
3639
4245 ; CHECK: ldr %f0, %f2
4346 ; CHECK: br %r14
4447 %cond = icmp slt i64 %i1, 128
45 %res = select i1 %cond, double %a, double %b
48 %tmp = select i1 %cond, double %a, double %b
49 %res = fadd double %tmp, 1.0
4650 ret double %res
4751 }
4852
5458 ; CHECK: ldr %f0, %f2
5559 ; CHECK: br %r14
5660 %cond = icmp slt i64 %i1, 32767
57 %res = select i1 %cond, double %a, double %b
61 %tmp = select i1 %cond, double %a, double %b
62 %res = fadd double %tmp, 1.0
5863 ret double %res
5964 }
6065
6671 ; CHECK: ldr %f0, %f2
6772 ; CHECK: br %r14
6873 %cond = icmp slt i64 %i1, 32768
69 %res = select i1 %cond, double %a, double %b
74 %tmp = select i1 %cond, double %a, double %b
75 %res = fadd double %tmp, 1.0
7076 ret double %res
7177 }
7278
7884 ; CHECK: ldr %f0, %f2
7985 ; CHECK: br %r14
8086 %cond = icmp slt i64 %i1, 2147483647
81 %res = select i1 %cond, double %a, double %b
87 %tmp = select i1 %cond, double %a, double %b
88 %res = fadd double %tmp, 1.0
8289 ret double %res
8390 }
8491
8996 ; CHECK: ldr %f0, %f2
9097 ; CHECK: br %r14
9198 %cond = icmp slt i64 %i1, 2147483648
92 %res = select i1 %cond, double %a, double %b
99 %tmp = select i1 %cond, double %a, double %b
100 %res = fadd double %tmp, 1.0
93101 ret double %res
94102 }
95103
100108 ; CHECK: ldr %f0, %f2
101109 ; CHECK: br %r14
102110 %cond = icmp slt i64 %i1, -1
103 %res = select i1 %cond, double %a, double %b
111 %tmp = select i1 %cond, double %a, double %b
112 %res = fadd double %tmp, 1.0
104113 ret double %res
105114 }
106115
111120 ; CHECK: ldr %f0, %f2
112121 ; CHECK: br %r14
113122 %cond = icmp slt i64 %i1, -128
114 %res = select i1 %cond, double %a, double %b
123 %tmp = select i1 %cond, double %a, double %b
124 %res = fadd double %tmp, 1.0
115125 ret double %res
116126 }
117127
123133 ; CHECK: ldr %f0, %f2
124134 ; CHECK: br %r14
125135 %cond = icmp slt i64 %i1, -129
126 %res = select i1 %cond, double %a, double %b
136 %tmp = select i1 %cond, double %a, double %b
137 %res = fadd double %tmp, 1.0
127138 ret double %res
128139 }
129140
135146 ; CHECK: ldr %f0, %f2
136147 ; CHECK: br %r14
137148 %cond = icmp slt i64 %i1, -32768
138 %res = select i1 %cond, double %a, double %b
149 %tmp = select i1 %cond, double %a, double %b
150 %res = fadd double %tmp, 1.0
139151 ret double %res
140152 }
141153
147159 ; CHECK: ldr %f0, %f2
148160 ; CHECK: br %r14
149161 %cond = icmp slt i64 %i1, -32769
150 %res = select i1 %cond, double %a, double %b
162 %tmp = select i1 %cond, double %a, double %b
163 %res = fadd double %tmp, 1.0
151164 ret double %res
152165 }
153166
159172 ; CHECK: ldr %f0, %f2
160173 ; CHECK: br %r14
161174 %cond = icmp slt i64 %i1, -2147483648
162 %res = select i1 %cond, double %a, double %b
175 %tmp = select i1 %cond, double %a, double %b
176 %res = fadd double %tmp, 1.0
163177 ret double %res
164178 }
165179
170184 ; CHECK: ldr %f0, %f2
171185 ; CHECK: br %r14
172186 %cond = icmp slt i64 %i1, -2147483649
173 %res = select i1 %cond, double %a, double %b
187 %tmp = select i1 %cond, double %a, double %b
188 %res = fadd double %tmp, 1.0
174189 ret double %res
175190 }
99 ; CHECK: ldr %f0, %f2
1010 ; CHECK: br %r14
1111 %cond = icmp ugt i64 %i1, 1
12 %res = select i1 %cond, double %a, double %b
12 %tmp = select i1 %cond, double %a, double %b
13 %res = fadd double %tmp, 1.0
1314 ret double %res
1415 }
1516
2021 ; CHECK: ldr %f0, %f2
2122 ; CHECK: br %r14
2223 %cond = icmp ult i64 %i1, 255
23 %res = select i1 %cond, double %a, double %b
24 %tmp = select i1 %cond, double %a, double %b
25 %res = fadd double %tmp, 1.0
2426 ret double %res
2527 }
2628
3234 ; CHECK: ldr %f0, %f2
3335 ; CHECK: br %r14
3436 %cond = icmp ult i64 %i1, 256
35 %res = select i1 %cond, double %a, double %b
37 %tmp = select i1 %cond, double %a, double %b
38 %res = fadd double %tmp, 1.0
3639 ret double %res
3740 }
3841
4447 ; CHECK: ldr %f0, %f2
4548 ; CHECK: br %r14
4649 %cond = icmp ult i64 %i1, 4294967295
47 %res = select i1 %cond, double %a, double %b
50 %tmp = select i1 %cond, double %a, double %b
51 %res = fadd double %tmp, 1.0
4852 ret double %res
4953 }
5054
5660 ; CHECK: ldr %f0, %f2
5761 ; CHECK: br %r14
5862 %cond = icmp ult i64 %i1, 4294967296
59 %res = select i1 %cond, double %a, double %b
63 %tmp = select i1 %cond, double %a, double %b
64 %res = fadd double %tmp, 1.0
6065 ret double %res
6166 }
6267 ; Check the next value up, which must use a register comparison.
6671 ; CHECK: ldr %f0, %f2
6772 ; CHECK: br %r14
6873 %cond = icmp ult i64 %i1, 4294967297
69 %res = select i1 %cond, double %a, double %b
74 %tmp = select i1 %cond, double %a, double %b
75 %res = fadd double %tmp, 1.0
7076 ret double %res
7177 }
88 ; CHECK: ldr %f0, %f2
99 ; CHECK: br %r14
1010 %cond = icmp eq i64 %i1, 0
11 %res = select i1 %cond, double %a, double %b
11 %tmp = select i1 %cond, double %a, double %b
12 %res = fadd double %tmp, 1.0
1213 ret double %res
1314 }
1415
1920 ; CHECK: ldr %f0, %f2
2021 ; CHECK: br %r14
2122 %cond = icmp eq i64 %i1, 127
22 %res = select i1 %cond, double %a, double %b
23 %tmp = select i1 %cond, double %a, double %b
24 %res = fadd double %tmp, 1.0
2325 ret double %res
2426 }
2527
3133 ; CHECK: ldr %f0, %f2
3234 ; CHECK: br %r14
3335 %cond = icmp eq i64 %i1, 128
34 %res = select i1 %cond, double %a, double %b
36 %tmp = select i1 %cond, double %a, double %b
37 %res = fadd double %tmp, 1.0
3538 ret double %res
3639 }
3740
4346 ; CHECK: ldr %f0, %f2
4447 ; CHECK: br %r14
4548 %cond = icmp eq i64 %i1, 32767
46 %res = select i1 %cond, double %a, double %b
49 %tmp = select i1 %cond, double %a, double %b
50 %res = fadd double %tmp, 1.0
4751 ret double %res
4852 }