llvm.org GIT mirror llvm / 05ec712
Reintroduce VirtRegRewriter. OK, not really. We don't want to reintroduce the old rewriter hacks. This patch extracts virtual register rewriting as a separate pass that runs after the register allocator. This is possible now that CodeGen/Passes.cpp can configure the full optimizing register allocator pipeline. The rewriter pass uses register assignments in VirtRegMap to rewrite virtual registers to physical registers, and it inserts kill flags based on live intervals. These finalization steps are the same for the optimizing register allocators: RABasic, RAGreedy, and PBQP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158244 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 8 years ago
9 changed file(s) with 126 addition(s) and 78 deletion(s). Raw diff Collapse all Expand all
299299 /// basic blocks.
300300 extern char &SpillPlacementID;
301301
302 /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as
303 /// assigned in VirtRegMap.
304 extern char &VirtRegRewriterID;
305
302306 /// UnreachableMachineBlockElimination - This pass removes unreachable
303307 /// machine basic blocks.
304308 extern char &UnreachableMachineBlockElimID;
247247 void initializeUnreachableMachineBlockElimPass(PassRegistry&);
248248 void initializeVerifierPass(PassRegistry&);
249249 void initializeVirtRegMapPass(PassRegistry&);
250 void initializeVirtRegRewriterPass(PassRegistry&);
250251 void initializeInstSimplifierPass(PassRegistry&);
251252 void initializeUnpackMachineBundlesPass(PassRegistry&);
252253 void initializeFinalizeMachineBundlesPass(PassRegistry&);
6464 initializeUnreachableBlockElimPass(Registry);
6565 initializeUnreachableMachineBlockElimPass(Registry);
6666 initializeVirtRegMapPass(Registry);
67 initializeVirtRegRewriterPass(Registry);
6768 initializeLowerIntrinsicsPass(Registry);
6869 initializeMachineFunctionPrinterPassPass(Registry);
6970 }
608608 PM->add(RegAllocPass);
609609 printAndVerify("After Register Allocation");
610610
611 // Finally rewrite virtual registers.
612 addPass(VirtRegRewriterID);
613 printAndVerify("After Virtual Register Rewriter");
614
611615 // FinalizeRegAlloc is convenient until MachineInstrBundles is more mature,
612616 // but eventually, all users of it should probably be moved to addPostRA and
613617 // it can go away. Currently, it's the intended place for targets to run
145145 AU.addRequired();
146146 AU.addPreserved();
147147 AU.addRequired();
148 AU.addPreserved();
148149 AU.addPreserved();
149150 AU.addRequired();
150151 AU.addPreserved();
334335 }
335336 #endif // !NDEBUG
336337
337 // Run rewriter
338 VRM->rewrite(LIS->getSlotIndexes());
339
340 // Write out new DBG_VALUE instructions.
341 getAnalysis().emitDebugValues(VRM);
342
343 // All machine operands and other references to virtual registers have been
344 // replaced. Remove the virtual registers and release all the transient data.
345 VRM->clearAllVirt();
346 MRI->clearVirtRegs();
347338 releaseMemory();
348
349339 return true;
350340 }
351341
336336 AU.addRequired();
337337 AU.addPreserved();
338338 AU.addRequired();
339 AU.addPreserved();
339340 AU.addRequired();
340341 AU.addPreserved();
341342 AU.addRequired();
17521753
17531754 allocatePhysRegs();
17541755 addMBBLiveIns(MF);
1755 LIS->addKillFlags();
1756
1757 // Run rewriter
1758 {
1759 NamedRegionTimer T("Rewriter", TimerGroupName, TimePassesIsEnabled);
1760 VRM->rewrite(Indexes);
1761 }
1762
1763 // Write out new DBG_VALUE instructions.
1764 {
1765 NamedRegionTimer T("Emit Debug Info", TimerGroupName, TimePassesIsEnabled);
1766 DebugVars->emitDebugValues(VRM);
1767 }
1768
1769 // All machine operands and other references to virtual registers have been
1770 // replaced. Remove the virtual registers and release all the transient data.
1771 VRM->clearAllVirt();
1772 MRI->clearVirtRegs();
17731756 releaseMemory();
1774
17751757 return true;
17761758 }
723723
724724 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *vrm << "\n");
725725
726 // Run rewriter
727 vrm->rewrite(lis->getSlotIndexes());
728
729 // All machine operands and other references to virtual registers have been
730 // replaced. Remove the virtual registers.
731 vrm->clearAllVirt();
732 mri->clearVirtRegs();
733
734726 return true;
735727 }
736728
1717
1818 #define DEBUG_TYPE "regalloc"
1919 #include "VirtRegMap.h"
20 #include "LiveDebugVariables.h"
2021 #include "llvm/Function.h"
22 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
2123 #include "llvm/CodeGen/MachineFrameInfo.h"
2224 #include "llvm/CodeGen/MachineFunction.h"
2325 #include "llvm/CodeGen/MachineInstrBuilder.h"
2426 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SlotIndexes.h"
27 #include "llvm/CodeGen/Passes.h"
2628 #include "llvm/Target/TargetMachine.h"
2729 #include "llvm/Target/TargetInstrInfo.h"
2830 #include "llvm/Target/TargetRegisterInfo.h"
103105 Virt2StackSlotMap[virtReg] = SS;
104106 }
105107
106 void VirtRegMap::rewrite(SlotIndexes *Indexes) {
108 void VirtRegMap::print(raw_ostream &OS, const Module*) const {
109 OS << "********** REGISTER MAP **********\n";
110 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
111 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
112 if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
113 OS << '[' << PrintReg(Reg, TRI) << " -> "
114 << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
115 << MRI->getRegClass(Reg)->getName() << "\n";
116 }
117 }
118
119 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
120 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
121 if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
122 OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
123 << "] " << MRI->getRegClass(Reg)->getName() << "\n";
124 }
125 }
126 OS << '\n';
127 }
128
129 void VirtRegMap::dump() const {
130 print(dbgs());
131 }
132
133 //===----------------------------------------------------------------------===//
134 // VirtRegRewriter
135 //===----------------------------------------------------------------------===//
136 //
137 // The VirtRegRewriter is the last of the register allocator passes.
138 // It rewrites virtual registers to physical registers as specified in the
139 // VirtRegMap analysis. It also updates live-in information on basic blocks
140 // according to LiveIntervals.
141 //
142 namespace {
143 class VirtRegRewriter : public MachineFunctionPass {
144 MachineFunction *MF;
145 const TargetMachine *TM;
146 const TargetRegisterInfo *TRI;
147 const TargetInstrInfo *TII;
148 MachineRegisterInfo *MRI;
149 SlotIndexes *Indexes;
150 LiveIntervals *LIS;
151 VirtRegMap *VRM;
152
153 void rewrite();
154 void addMBBLiveIns();
155 public:
156 static char ID;
157 VirtRegRewriter() : MachineFunctionPass(ID) {}
158
159 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
160
161 virtual bool runOnMachineFunction(MachineFunction&);
162 };
163 } // end anonymous namespace
164
165 char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
166
167 INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
168 "Virtual Register Rewriter", false, false)
169 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
170 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
171 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
172 INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
173 INITIALIZE_PASS_END(VirtRegRewriter, "virtregrewriter",
174 "Virtual Register Rewriter", false, false)
175
176 char VirtRegRewriter::ID = 0;
177
178 void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
179 AU.setPreservesCFG();
180 AU.addRequired();
181 AU.addRequired();
182 AU.addPreserved();
183 AU.addRequired();
184 AU.addRequired();
185 MachineFunctionPass::getAnalysisUsage(AU);
186 }
187
188 bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
189 MF = &fn;
190 TM = &MF->getTarget();
191 TRI = TM->getRegisterInfo();
192 TII = TM->getInstrInfo();
193 MRI = &MF->getRegInfo();
194 Indexes = &getAnalysis();
195 LIS = &getAnalysis();
196 VRM = &getAnalysis();
107197 DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
108198 << "********** Function: "
109199 << MF->getFunction()->getName() << '\n');
110 DEBUG(dump());
200 DEBUG(VRM->dump());
201
202 // Add kill flags while we still have virtual registers.
203 LIS->addKillFlags();
204
205 // Rewrite virtual registers.
206 rewrite();
207
208 // Write out new DBG_VALUE instructions.
209 getAnalysis().emitDebugValues(VRM);
210
211 // All machine operands and other references to virtual registers have been
212 // replaced. Remove the virtual registers and release all the transient data.
213 VRM->clearAllVirt();
214 MRI->clearVirtRegs();
215 return true;
216 }
217
218 void VirtRegRewriter::rewrite() {
111219 SmallVector SuperDeads;
112220 SmallVector SuperDefs;
113221 SmallVector SuperKills;
134242 if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
135243 continue;
136244 unsigned VirtReg = MO.getReg();
137 unsigned PhysReg = getPhys(VirtReg);
138 assert(PhysReg != NO_PHYS_REG && "Instruction uses unmapped VirtReg");
245 unsigned PhysReg = VRM->getPhys(VirtReg);
246 assert(PhysReg != VirtRegMap::NO_PHYS_REG &&
247 "Instruction uses unmapped VirtReg");
139248 assert(!Reserved.test(PhysReg) && "Reserved register assignment");
140249
141250 // Preserve semantics of sub-register operands.
206315 if (!MRI->reg_nodbg_empty(Reg))
207316 MRI->setPhysRegUsed(Reg);
208317 }
209
210 void VirtRegMap::print(raw_ostream &OS, const Module* M) const {
211 const TargetRegisterInfo* TRI = MF->getTarget().getRegisterInfo();
212 const MachineRegisterInfo &MRI = MF->getRegInfo();
213
214 OS << "********** REGISTER MAP **********\n";
215 for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
216 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
217 if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
218 OS << '[' << PrintReg(Reg, TRI) << " -> "
219 << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
220 << MRI.getRegClass(Reg)->getName() << "\n";
221 }
222 }
223
224 for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
225 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
226 if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
227 OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
228 << "] " << MRI.getRegClass(Reg)->getName() << "\n";
229 }
230 }
231 OS << '\n';
232 }
233
234 void VirtRegMap::dump() const {
235 print(dbgs());
236 }
176176 /// the specified stack slot
177177 void assignVirt2StackSlot(unsigned virtReg, int frameIndex);
178178
179 /// rewrite - Rewrite all instructions in MF to use only physical registers
180 /// by mapping all virtual register operands to their assigned physical
181 /// registers.
182 ///
183 /// @param Indexes Optionally remove deleted instructions from indexes.
184 void rewrite(SlotIndexes *Indexes);
185
186179 void print(raw_ostream &OS, const Module* M = 0) const;
187180 void dump() const;
188181 };