llvm.org GIT mirror llvm / 05b523a
ARM: Initialize LoadStore passes in TargetMachine Initializing them in LLVMInitializeARMTarget() makes them visible early enough for "llc -run-pass usage". This required the pass to be renamed from "arm-load-store-opt" to "arm-ldst-opt", because there already exists an arm-load-store-opt cl::opt switch which would now clash with the passname getting added as a switch in opt. On the bright side the pass name now matches the DEBUG_TYPE name. Renamed "arm-prera-load-store-opt" to "arm-repra-ldst-opt" as well for consistency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275661 91177308-0d34-0410-b5e6-96231b3b80d8 Matthias Braun 4 years ago
3 changed file(s) with 13 addition(s) and 16 deletion(s). Raw diff Collapse all Expand all
2626 class ImmutablePass;
2727 class MachineInstr;
2828 class MCInst;
29 class PassRegistry;
2930 class TargetLowering;
3031 class TargetMachine;
3132
4445 void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
4546 ARMAsmPrinter &AP);
4647
48 void initializeARMLoadStoreOptPass(PassRegistry &);
49 void initializeARMPreAllocLoadStoreOptPass(PassRegistry &);
50
4751 } // end namespace llvm;
4852
4953 #endif
6868 AssumeMisalignedLoadStores("arm-assume-misaligned-load-store", cl::Hidden,
6969 cl::init(false), cl::desc("Be more conservative in ARM load/store opt"));
7070
71 namespace llvm {
72 void initializeARMLoadStoreOptPass(PassRegistry &);
73 }
74
7571 #define ARM_LOAD_STORE_OPT_NAME "ARM load / store optimization pass"
7672
7773 namespace {
7975 /// form ldm / stm instructions.
8076 struct ARMLoadStoreOpt : public MachineFunctionPass {
8177 static char ID;
82 ARMLoadStoreOpt() : MachineFunctionPass(ID) {
83 initializeARMLoadStoreOptPass(*PassRegistry::getPassRegistry());
84 }
78 ARMLoadStoreOpt() : MachineFunctionPass(ID) {}
8579
8680 const MachineFunction *MF;
8781 const TargetInstrInfo *TII;
171165 char ARMLoadStoreOpt::ID = 0;
172166 }
173167
174 INITIALIZE_PASS(ARMLoadStoreOpt, "arm-load-store-opt", ARM_LOAD_STORE_OPT_NAME, false, false)
168 INITIALIZE_PASS(ARMLoadStoreOpt, "arm-ldst-opt", ARM_LOAD_STORE_OPT_NAME, false,
169 false)
175170
176171 static bool definesCPSR(const MachineInstr &MI) {
177172 for (const auto &MO : MI.operands()) {
19381933 return Modified;
19391934 }
19401935
1941 namespace llvm {
1942 void initializeARMPreAllocLoadStoreOptPass(PassRegistry &);
1943 }
1944
19451936 #define ARM_PREALLOC_LOAD_STORE_OPT_NAME \
19461937 "ARM pre- register allocation load / store optimization pass"
19471938
19501941 /// locations close to make it more likely they will be combined later.
19511942 struct ARMPreAllocLoadStoreOpt : public MachineFunctionPass{
19521943 static char ID;
1953 ARMPreAllocLoadStoreOpt() : MachineFunctionPass(ID) {
1954 initializeARMPreAllocLoadStoreOptPass(*PassRegistry::getPassRegistry());
1955 }
1944 ARMPreAllocLoadStoreOpt() : MachineFunctionPass(ID) {}
19561945
19571946 const DataLayout *TD;
19581947 const TargetInstrInfo *TII;
19831972 char ARMPreAllocLoadStoreOpt::ID = 0;
19841973 }
19851974
1986 INITIALIZE_PASS(ARMPreAllocLoadStoreOpt, "arm-prera-load-store-opt",
1975 INITIALIZE_PASS(ARMPreAllocLoadStoreOpt, "arm-prera-ldst-opt",
19871976 ARM_PREALLOC_LOAD_STORE_OPT_NAME, false, false)
19881977
19891978 bool ARMPreAllocLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
5353 RegisterTargetMachine Y(TheARMBETarget);
5454 RegisterTargetMachine A(TheThumbLETarget);
5555 RegisterTargetMachine B(TheThumbBETarget);
56
57 PassRegistry &Registry = *PassRegistry::getPassRegistry();
58 initializeARMLoadStoreOptPass(Registry);
59 initializeARMPreAllocLoadStoreOptPass(Registry);
5660 }
5761
5862 static std::unique_ptr createTLOF(const Triple &TT) {