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Duh. Default to ARMCC::AL (always). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56301 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 11 years ago
1 changed file(s) with 63 addition(s) and 23 deletion(s). Raw diff Collapse all Expand all
2121 #include "llvm/Function.h"
2222 #include "llvm/PassManager.h"
2323 #include "llvm/CodeGen/MachineCodeEmitter.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
2425 #include "llvm/CodeGen/MachineFunctionPass.h"
2526 #include "llvm/CodeGen/MachineInstr.h"
2627 #include "llvm/CodeGen/Passes.h"
3334
3435 namespace {
3536 class VISIBILITY_HIDDEN ARMCodeEmitter : public MachineFunctionPass {
36 const ARMInstrInfo *II;
37 const TargetData *TD;
38 TargetMachine &TM;
39 MachineCodeEmitter &MCE;
37 ARMJITInfo *JTI;
38 const ARMInstrInfo *II;
39 const TargetData *TD;
40 TargetMachine &TM;
41 MachineCodeEmitter &MCE;
42 const MachineConstantPool *MCP;
4043 public:
4144 static char ID;
4245 explicit ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
43 : MachineFunctionPass(&ID), II(0), TD(0), TM(tm),
44 MCE(mce) {}
46 : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
47 MCE(mce), MCP(0) {}
4548 ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
4649 const ARMInstrInfo &ii, const TargetData &td)
47 : MachineFunctionPass(&ID), II(&ii), TD(&td), TM(tm),
48 MCE(mce) {}
50 : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
51 MCE(mce), MCP(0) {}
4952
5053 bool runOnMachineFunction(MachineFunction &MF);
5154
5659 void emitInstruction(const MachineInstr &MI);
5760
5861 private:
62
63 void emitConstPoolInstruction(const MachineInstr &MI);
64
65 void emitPseudoInstruction(const MachineInstr &MI);
66
5967 unsigned getAddrModeNoneInstrBinary(const MachineInstr &MI,
6068 const TargetInstrDesc &TID,
6169 unsigned Binary);
110118
111119 /// Routines that handle operands which add machine relocations which are
112120 /// fixed up by the JIT fixup stage.
113 void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
121 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
122 bool DoesntNeedStub);
114123 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
115124 void emitConstPoolAddress(unsigned CPI, unsigned Reloc,
116125 int Disp = 0, unsigned PCAdj = 0 );
117 void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
126 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc,
118127 unsigned PCAdj = 0);
119128 void emitGlobalConstant(const Constant *CV);
120129 void emitMachineBasicBlock(MachineBasicBlock *BB);
135144 "JIT relocation model must be set to static or default!");
136145 II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
137146 TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
147 JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
148 MCP = MF.getConstantPool();
138149
139150 do {
140151 DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
174185 else if (MO.isImmediate())
175186 return static_cast(MO.getImm());
176187 else if (MO.isGlobalAddress())
177 emitGlobalAddressForCall(MO.getGlobal(), false);
188 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, false);
178189 else if (MO.isExternalSymbol())
179190 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_relative);
180191 else if (MO.isConstantPoolIndex())
190201 return 0;
191202 }
192203
193 /// emitGlobalAddressForCall - Emit the specified address to the code stream
194 /// assuming this is part of a function call, which is PC relative.
204 /// emitGlobalAddress - Emit the specified address to the code stream.
195205 ///
196 void ARMCodeEmitter::emitGlobalAddressForCall(GlobalValue *GV,
197 bool DoesntNeedStub) {
206 void ARMCodeEmitter::emitGlobalAddress(GlobalValue *GV,
207 unsigned Reloc, bool DoesntNeedStub) {
198208 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
199 ARM::reloc_arm_branch, GV, 0,
200 DoesntNeedStub));
209 Reloc, GV, 0, DoesntNeedStub));
201210 }
202211
203212 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
221230 /// emitJumpTableAddress - Arrange for the address of a jump table to
222231 /// be emitted to the current location in the function, and allow it to be PC
223232 /// relative.
224 void ARMCodeEmitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
233 void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc,
225234 unsigned PCAdj /* = 0 */) {
226235 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
227 Reloc, JTI, PCAdj));
236 Reloc, JTIndex, PCAdj));
228237 }
229238
230239 /// emitMachineBasicBlock - Emit the specified address basic block.
237246 DOUT << MI;
238247
239248 NumEmitted++; // Keep track of the # of mi's emitted
240 MCE.emitWordLE(getInstrBinary(MI));
249 if ((MI.getDesc().TSFlags & ARMII::FormMask) == ARMII::Pseudo)
250 emitPseudoInstruction(MI);
251 else
252 MCE.emitWordLE(getInstrBinary(MI));
241253 }
242254
243255 unsigned ARMCodeEmitter::getAddrModeNoneInstrBinary(const MachineInstr &MI,
244256 const TargetInstrDesc &TID,
245257 unsigned Binary) {
258 // FIXME: Assume CC is AL for now.
259 Binary |= ARMCC::AL << 28;
260
246261 switch (TID.TSFlags & ARMII::FormMask) {
247262 default:
248263 assert(0 && "Unknown instruction subtype!");
341356 return 0;
342357 }
343358
359 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
360 // FIXME
361 }
362
363 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
364 unsigned Opcode = MI.getDesc().Opcode;
365 switch (Opcode) {
366 default:
367 abort(); // FIXME:
368 case ARM::CONSTPOOL_ENTRY: {
369 emitConstPoolInstruction(MI);
370 break;
371 }
372 }
373 }
374
344375 unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
345376 const TargetInstrDesc &TID,
346377 unsigned Binary) {
347 unsigned Format = TID.TSFlags & ARMII::FormMask;
348 if (Format == ARMII::Pseudo)
349 abort(); // FIXME
378 // FIXME: Assume CC is AL for now.
379 Binary |= ARMCC::AL << 28;
350380
351381 // Encode S bit if MI modifies CPSR.
352382 Binary |= getAddrMode1SBit(MI, TID);
360390 }
361391
362392 // Encode first non-shifter register operand if ther is one.
393 unsigned Format = TID.TSFlags & ARMII::FormMask;
363394 bool isUnary = (Format == ARMII::DPRdMisc ||
364395 Format == ARMII::DPRdIm ||
365396 Format == ARMII::DPRdReg ||
400431 unsigned ARMCodeEmitter::getAddrMode2InstrBinary(const MachineInstr &MI,
401432 const TargetInstrDesc &TID,
402433 unsigned Binary) {
434 // FIXME: Assume CC is AL for now.
435 Binary |= ARMCC::AL << 28;
436
403437 // Set first operand
404438 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
405439
438472 unsigned ARMCodeEmitter::getAddrMode3InstrBinary(const MachineInstr &MI,
439473 const TargetInstrDesc &TID,
440474 unsigned Binary) {
475 // FIXME: Assume CC is AL for now.
476 Binary |= ARMCC::AL << 28;
477
441478 // Set first operand
442479 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
443480
472509 unsigned ARMCodeEmitter::getAddrMode4InstrBinary(const MachineInstr &MI,
473510 const TargetInstrDesc &TID,
474511 unsigned Binary) {
512 // FIXME: Assume CC is AL for now.
513 Binary |= ARMCC::AL << 28;
514
475515 // Set first operand
476516 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
477517