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Merging r330037: ------------------------------------------------------------------------ r330037 | sdardis | 2018-04-13 09:09:07 -0700 (Fri, 13 Apr 2018) | 21 lines [mips] Materialize constants for multiplication Previously, the MIPS backend would alwyas break down constant multiplications into a series of shifts, adds, and subs. This patch changes that so the cost of doing so is estimated. The cost is estimated against worst case constant materialization and retrieving the results from the HI/LO registers. For cases where the value type of the multiplication is not legal, the cost of legalization is estimated and is accounted for before performing the optimization of breaking down the constant This resolves PR36884. Thanks to npl for reporting the issue! Reviewers: abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D45316 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@332782 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 1 year, 5 months ago
2 changed file(s) with 141 addition(s) and 227 deletion(s). Raw diff Collapse all Expand all
700700 return SDValue();
701701 }
702702
703 static bool shouldTransformMulToShiftsAddsSubs(APInt C, EVT VT,
704 SelectionDAG &DAG,
705 const MipsSubtarget &Subtarget) {
706 // Estimate the number of operations the below transform will turn a
707 // constant multiply into. The number is approximately how many powers
708 // of two summed together that the constant can be broken down into.
709
710 SmallVector WorkStack(1, C);
711 unsigned Steps = 0;
712 unsigned BitWidth = C.getBitWidth();
713
714 while (!WorkStack.empty()) {
715 APInt Val = WorkStack.pop_back_val();
716
717 if (Val == 0 || Val == 1)
718 continue;
719
720 if (Val.isPowerOf2()) {
721 ++Steps;
722 continue;
723 }
724
725 APInt Floor = APInt(BitWidth, 1) << Val.logBase2();
726 APInt Ceil = Val.isNegative() ? APInt(BitWidth, 0)
727 : APInt(BitWidth, 1) << C.ceilLogBase2();
728
729 if ((Val - Floor).ule(Ceil - Val)) {
730 WorkStack.push_back(Floor);
731 WorkStack.push_back(Val - Floor);
732 ++Steps;
733 continue;
734 }
735
736 WorkStack.push_back(Ceil);
737 WorkStack.push_back(Ceil - Val);
738 ++Steps;
739
740 // If we have taken more than 12[1] / 8[2] steps to attempt the
741 // optimization for a native sized value, it is more than likely that this
742 // optimization will make things worse.
743 //
744 // [1] MIPS64 requires 6 instructions at most to materialize any constant,
745 // multiplication requires at least 4 cycles, but another cycle (or two)
746 // to retrieve the result from the HI/LO registers.
747 //
748 // [2] For MIPS32, more than 8 steps is expensive as the constant could be
749 // materialized in 2 instructions, multiplication requires at least 4
750 // cycles, but another cycle (or two) to retrieve the result from the
751 // HI/LO registers.
752
753 if (Steps > 12 && (Subtarget.isABI_N32() || Subtarget.isABI_N64()))
754 return false;
755
756 if (Steps > 8 && Subtarget.isABI_O32())
757 return false;
758 }
759
760 // If the value being multiplied is not supported natively, we have to pay
761 // an additional legalization cost, conservatively assume an increase in the
762 // cost of 3 instructions per step. This values for this heuristic were
763 // determined experimentally.
764 unsigned RegisterSize = DAG.getTargetLoweringInfo()
765 .getRegisterType(*DAG.getContext(), VT)
766 .getSizeInBits();
767 Steps *= (VT.getSizeInBits() != RegisterSize) * 3;
768 if (Steps > 27)
769 return false;
770
771 return true;
772 }
773
703774 static SDValue genConstMult(SDValue X, APInt C, const SDLoc &DL, EVT VT,
704775 EVT ShiftTy, SelectionDAG &DAG) {
705776 // Return 0.
738809
739810 static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
740811 const TargetLowering::DAGCombinerInfo &DCI,
741 const MipsSETargetLowering *TL) {
812 const MipsSETargetLowering *TL,
813 const MipsSubtarget &Subtarget) {
742814 EVT VT = N->getValueType(0);
743815
744816 if (ConstantSDNode *C = dyn_cast(N->getOperand(1)))
745 if (!VT.isVector())
817 if (!VT.isVector() && shouldTransformMulToShiftsAddsSubs(
818 C->getAPIntValue(), VT, DAG, Subtarget))
746819 return genConstMult(N->getOperand(0), C->getAPIntValue(), SDLoc(N), VT,
747820 TL->getScalarShiftAmountTy(DAG.getDataLayout(), VT),
748821 DAG);
9821055 Val = performORCombine(N, DAG, DCI, Subtarget);
9831056 break;
9841057 case ISD::MUL:
985 return performMULCombine(N, DAG, DCI, this);
1058 return performMULCombine(N, DAG, DCI, this, Subtarget);
9861059 case ISD::SHL:
9871060 Val = performSHLCombine(N, DAG, DCI, Subtarget);
9881061 break;
256256 define i64 @mul42949673_64(i64 %a) {
257257 ; MIPS32-LABEL: mul42949673_64:
258258 ; MIPS32: # %bb.0: # %entry
259 ; MIPS32-NEXT: addiu $sp, $sp, -8
260 ; MIPS32-NEXT: .cfi_def_cfa_offset 8
261 ; MIPS32-NEXT: sw $16, 4($sp) # 4-byte Folded Spill
262 ; MIPS32-NEXT: .cfi_offset 16, -4
263 ; MIPS32-NEXT: sll $1, $4, 3
264 ; MIPS32-NEXT: addu $2, $1, $4
265 ; MIPS32-NEXT: sltu $1, $2, $1
266 ; MIPS32-NEXT: srl $3, $4, 29
267 ; MIPS32-NEXT: sll $6, $5, 3
268 ; MIPS32-NEXT: or $3, $6, $3
259 ; MIPS32-NEXT: lui $1, 655
260 ; MIPS32-NEXT: ori $1, $1, 23593
261 ; MIPS32-NEXT: multu $4, $1
262 ; MIPS32-NEXT: mflo $2
263 ; MIPS32-NEXT: mfhi $1
264 ; MIPS32-NEXT: sll $3, $5, 3
269265 ; MIPS32-NEXT: addu $3, $3, $5
270 ; MIPS32-NEXT: addu $1, $3, $1
271 ; MIPS32-NEXT: srl $3, $4, 27
272 ; MIPS32-NEXT: sll $6, $5, 5
273 ; MIPS32-NEXT: or $3, $6, $3
274 ; MIPS32-NEXT: addu $1, $3, $1
275 ; MIPS32-NEXT: sll $3, $4, 5
276 ; MIPS32-NEXT: addu $2, $3, $2
277 ; MIPS32-NEXT: sll $6, $4, 10
278 ; MIPS32-NEXT: subu $7, $6, $2
279 ; MIPS32-NEXT: sltu $3, $2, $3
280 ; MIPS32-NEXT: sll $8, $4, 13
281 ; MIPS32-NEXT: addu $1, $1, $3
282 ; MIPS32-NEXT: addu $3, $8, $7
283 ; MIPS32-NEXT: sll $7, $4, 15
284 ; MIPS32-NEXT: addu $9, $7, $3
285 ; MIPS32-NEXT: srl $10, $4, 22
286 ; MIPS32-NEXT: sll $11, $5, 10
287 ; MIPS32-NEXT: or $10, $11, $10
288 ; MIPS32-NEXT: sll $11, $4, 20
289 ; MIPS32-NEXT: subu $1, $10, $1
290 ; MIPS32-NEXT: subu $10, $11, $9
291 ; MIPS32-NEXT: sltu $2, $6, $2
292 ; MIPS32-NEXT: srl $6, $4, 17
293 ; MIPS32-NEXT: sll $12, $5, 15
294 ; MIPS32-NEXT: srl $13, $4, 12
295 ; MIPS32-NEXT: sll $14, $5, 20
296 ; MIPS32-NEXT: srl $15, $4, 9
297 ; MIPS32-NEXT: sll $24, $5, 23
298 ; MIPS32-NEXT: sll $25, $4, 23
299 ; MIPS32-NEXT: srl $gp, $4, 7
300 ; MIPS32-NEXT: sll $16, $5, 25
301 ; MIPS32-NEXT: or $gp, $16, $gp
302 ; MIPS32-NEXT: sll $16, $4, 25
303 ; MIPS32-NEXT: subu $1, $1, $2
304 ; MIPS32-NEXT: addu $10, $25, $10
305 ; MIPS32-NEXT: or $2, $24, $15
306 ; MIPS32-NEXT: or $13, $14, $13
307 ; MIPS32-NEXT: or $6, $12, $6
308 ; MIPS32-NEXT: srl $4, $4, 19
309 ; MIPS32-NEXT: sll $5, $5, 13
310 ; MIPS32-NEXT: or $4, $5, $4
311 ; MIPS32-NEXT: addu $1, $4, $1
312 ; MIPS32-NEXT: sltu $3, $3, $8
313 ; MIPS32-NEXT: addu $1, $1, $3
314 ; MIPS32-NEXT: addu $1, $6, $1
315 ; MIPS32-NEXT: sltu $3, $9, $7
316 ; MIPS32-NEXT: addu $1, $1, $3
317 ; MIPS32-NEXT: subu $1, $13, $1
318 ; MIPS32-NEXT: sltu $3, $11, $9
319 ; MIPS32-NEXT: subu $1, $1, $3
320 ; MIPS32-NEXT: addu $1, $2, $1
321 ; MIPS32-NEXT: addu $2, $16, $10
322 ; MIPS32-NEXT: sltu $3, $10, $25
323 ; MIPS32-NEXT: addu $1, $1, $3
324 ; MIPS32-NEXT: sltu $3, $2, $16
325 ; MIPS32-NEXT: addu $1, $gp, $1
266 ; MIPS32-NEXT: sll $4, $5, 5
267 ; MIPS32-NEXT: addu $3, $4, $3
268 ; MIPS32-NEXT: sll $4, $5, 10
269 ; MIPS32-NEXT: subu $3, $4, $3
270 ; MIPS32-NEXT: sll $4, $5, 13
271 ; MIPS32-NEXT: addu $3, $4, $3
272 ; MIPS32-NEXT: sll $4, $5, 15
273 ; MIPS32-NEXT: addu $3, $4, $3
274 ; MIPS32-NEXT: sll $4, $5, 20
275 ; MIPS32-NEXT: subu $3, $4, $3
276 ; MIPS32-NEXT: sll $4, $5, 25
277 ; MIPS32-NEXT: sll $5, $5, 23
278 ; MIPS32-NEXT: addu $3, $5, $3
279 ; MIPS32-NEXT: addu $3, $4, $3
280 ; MIPS32-NEXT: jr $ra
326281 ; MIPS32-NEXT: addu $3, $1, $3
327 ; MIPS32-NEXT: lw $16, 4($sp) # 4-byte Folded Reload
328 ; MIPS32-NEXT: jr $ra
329 ; MIPS32-NEXT: addiu $sp, $sp, 8
330282 ;
331283 ; MIPS64-LABEL: mul42949673_64:
332284 ; MIPS64: # %bb.0: # %entry
411363 define i64 @mul22224078_64(i64 %a) {
412364 ; MIPS32-LABEL: mul22224078_64:
413365 ; MIPS32: # %bb.0: # %entry
414 ; MIPS32-NEXT: addiu $sp, $sp, -32
415 ; MIPS32-NEXT: .cfi_def_cfa_offset 32
416 ; MIPS32-NEXT: sw $22, 28($sp) # 4-byte Folded Spill
417 ; MIPS32-NEXT: sw $21, 24($sp) # 4-byte Folded Spill
418 ; MIPS32-NEXT: sw $20, 20($sp) # 4-byte Folded Spill
419 ; MIPS32-NEXT: sw $19, 16($sp) # 4-byte Folded Spill
420 ; MIPS32-NEXT: sw $18, 12($sp) # 4-byte Folded Spill
421 ; MIPS32-NEXT: sw $17, 8($sp) # 4-byte Folded Spill
422 ; MIPS32-NEXT: sw $16, 4($sp) # 4-byte Folded Spill
423 ; MIPS32-NEXT: .cfi_offset 22, -4
424 ; MIPS32-NEXT: .cfi_offset 21, -8
425 ; MIPS32-NEXT: .cfi_offset 20, -12
426 ; MIPS32-NEXT: .cfi_offset 19, -16
427 ; MIPS32-NEXT: .cfi_offset 18, -20
428 ; MIPS32-NEXT: .cfi_offset 17, -24
429 ; MIPS32-NEXT: .cfi_offset 16, -28
430 ; MIPS32-NEXT: srl $1, $4, 31
431 ; MIPS32-NEXT: sll $2, $5, 1
432 ; MIPS32-NEXT: or $1, $2, $1
433 ; MIPS32-NEXT: srl $2, $4, 28
434 ; MIPS32-NEXT: sll $3, $5, 4
435 ; MIPS32-NEXT: or $2, $3, $2
436 ; MIPS32-NEXT: subu $1, $2, $1
437 ; MIPS32-NEXT: sll $2, $4, 1
438 ; MIPS32-NEXT: sll $3, $4, 4
439 ; MIPS32-NEXT: sltu $6, $3, $2
440 ; MIPS32-NEXT: subu $1, $1, $6
441 ; MIPS32-NEXT: subu $2, $3, $2
442 ; MIPS32-NEXT: sll $3, $4, 6
443 ; MIPS32-NEXT: subu $6, $3, $2
444 ; MIPS32-NEXT: srl $7, $4, 26
445 ; MIPS32-NEXT: sll $8, $5, 6
446 ; MIPS32-NEXT: or $7, $8, $7
447 ; MIPS32-NEXT: sll $8, $4, 8
448 ; MIPS32-NEXT: subu $1, $7, $1
449 ; MIPS32-NEXT: subu $7, $8, $6
450 ; MIPS32-NEXT: sll $9, $4, 10
451 ; MIPS32-NEXT: subu $10, $9, $7
452 ; MIPS32-NEXT: sltu $2, $3, $2
453 ; MIPS32-NEXT: sll $3, $4, 13
454 ; MIPS32-NEXT: srl $11, $4, 24
455 ; MIPS32-NEXT: sll $12, $5, 8
456 ; MIPS32-NEXT: subu $1, $1, $2
457 ; MIPS32-NEXT: or $2, $12, $11
458 ; MIPS32-NEXT: subu $11, $3, $10
459 ; MIPS32-NEXT: srl $12, $4, 22
460 ; MIPS32-NEXT: sll $13, $5, 10
461 ; MIPS32-NEXT: sll $14, $4, 16
462 ; MIPS32-NEXT: subu $15, $14, $11
463 ; MIPS32-NEXT: srl $24, $4, 14
464 ; MIPS32-NEXT: srl $25, $4, 12
465 ; MIPS32-NEXT: srl $gp, $4, 10
466 ; MIPS32-NEXT: srl $16, $4, 8
467 ; MIPS32-NEXT: subu $1, $2, $1
468 ; MIPS32-NEXT: or $2, $13, $12
469 ; MIPS32-NEXT: sltu $6, $8, $6
470 ; MIPS32-NEXT: srl $8, $4, 19
471 ; MIPS32-NEXT: sll $12, $5, 13
472 ; MIPS32-NEXT: srl $13, $4, 16
473 ; MIPS32-NEXT: sll $17, $5, 16
474 ; MIPS32-NEXT: sll $18, $5, 18
475 ; MIPS32-NEXT: sll $19, $5, 20
476 ; MIPS32-NEXT: sll $20, $5, 22
477 ; MIPS32-NEXT: sll $5, $5, 24
478 ; MIPS32-NEXT: sll $21, $4, 18
479 ; MIPS32-NEXT: subu $22, $21, $15
480 ; MIPS32-NEXT: or $5, $5, $16
481 ; MIPS32-NEXT: or $gp, $20, $gp
482 ; MIPS32-NEXT: or $25, $19, $25
483 ; MIPS32-NEXT: or $24, $18, $24
484 ; MIPS32-NEXT: or $13, $17, $13
485 ; MIPS32-NEXT: or $8, $12, $8
486 ; MIPS32-NEXT: sll $12, $4, 24
487 ; MIPS32-NEXT: sll $16, $4, 22
488 ; MIPS32-NEXT: sll $4, $4, 20
489 ; MIPS32-NEXT: subu $1, $1, $6
490 ; MIPS32-NEXT: subu $1, $2, $1
491 ; MIPS32-NEXT: sltu $2, $9, $7
492 ; MIPS32-NEXT: subu $1, $1, $2
493 ; MIPS32-NEXT: subu $1, $8, $1
494 ; MIPS32-NEXT: sltu $2, $3, $10
495 ; MIPS32-NEXT: subu $1, $1, $2
496 ; MIPS32-NEXT: subu $1, $13, $1
497 ; MIPS32-NEXT: sltu $2, $14, $11
498 ; MIPS32-NEXT: subu $1, $1, $2
499 ; MIPS32-NEXT: subu $1, $24, $1
500 ; MIPS32-NEXT: addu $3, $4, $22
501 ; MIPS32-NEXT: sltu $2, $21, $15
502 ; MIPS32-NEXT: subu $1, $1, $2
503 ; MIPS32-NEXT: addu $6, $16, $3
504 ; MIPS32-NEXT: addu $1, $25, $1
505 ; MIPS32-NEXT: addu $2, $12, $6
506 ; MIPS32-NEXT: sltu $7, $2, $12
507 ; MIPS32-NEXT: sltu $6, $6, $16
508 ; MIPS32-NEXT: sltu $3, $3, $4
509 ; MIPS32-NEXT: addu $1, $1, $3
510 ; MIPS32-NEXT: addu $1, $gp, $1
511 ; MIPS32-NEXT: addu $1, $1, $6
512 ; MIPS32-NEXT: addu $1, $5, $1
513 ; MIPS32-NEXT: addu $3, $1, $7
514 ; MIPS32-NEXT: lw $16, 4($sp) # 4-byte Folded Reload
515 ; MIPS32-NEXT: lw $17, 8($sp) # 4-byte Folded Reload
516 ; MIPS32-NEXT: lw $18, 12($sp) # 4-byte Folded Reload
517 ; MIPS32-NEXT: lw $19, 16($sp) # 4-byte Folded Reload
518 ; MIPS32-NEXT: lw $20, 20($sp) # 4-byte Folded Reload
519 ; MIPS32-NEXT: lw $21, 24($sp) # 4-byte Folded Reload
520 ; MIPS32-NEXT: lw $22, 28($sp) # 4-byte Folded Reload
521 ; MIPS32-NEXT: jr $ra
522 ; MIPS32-NEXT: addiu $sp, $sp, 32
366 ; MIPS32-NEXT: lui $1, 339
367 ; MIPS32-NEXT: ori $1, $1, 7374
368 ; MIPS32-NEXT: multu $4, $1
369 ; MIPS32-NEXT: mflo $2
370 ; MIPS32-NEXT: mfhi $1
371 ; MIPS32-NEXT: sll $3, $5, 1
372 ; MIPS32-NEXT: sll $4, $5, 4
373 ; MIPS32-NEXT: subu $3, $4, $3
374 ; MIPS32-NEXT: sll $4, $5, 6
375 ; MIPS32-NEXT: subu $3, $4, $3
376 ; MIPS32-NEXT: sll $4, $5, 8
377 ; MIPS32-NEXT: subu $3, $4, $3
378 ; MIPS32-NEXT: sll $4, $5, 10
379 ; MIPS32-NEXT: subu $3, $4, $3
380 ; MIPS32-NEXT: sll $4, $5, 13
381 ; MIPS32-NEXT: subu $3, $4, $3
382 ; MIPS32-NEXT: sll $4, $5, 16
383 ; MIPS32-NEXT: subu $3, $4, $3
384 ; MIPS32-NEXT: sll $4, $5, 24
385 ; MIPS32-NEXT: sll $6, $5, 22
386 ; MIPS32-NEXT: sll $7, $5, 20
387 ; MIPS32-NEXT: sll $5, $5, 18
388 ; MIPS32-NEXT: subu $3, $5, $3
389 ; MIPS32-NEXT: addu $3, $7, $3
390 ; MIPS32-NEXT: addu $3, $6, $3
391 ; MIPS32-NEXT: addu $3, $4, $3
392 ; MIPS32-NEXT: jr $ra
393 ; MIPS32-NEXT: addu $3, $1, $3
523394 ;
524395 ; MIPS64-LABEL: mul22224078_64:
525396 ; MIPS64: # %bb.0: # %entry
591462 define i64 @mul22245375_64(i64 %a) {
592463 ; MIPS32-LABEL: mul22245375_64:
593464 ; MIPS32: # %bb.0: # %entry
594 ; MIPS32-NEXT: sll $1, $4, 12
595 ; MIPS32-NEXT: addu $2, $1, $4
596 ; MIPS32-NEXT: sltu $1, $2, $1
597 ; MIPS32-NEXT: srl $3, $4, 20
598 ; MIPS32-NEXT: sll $6, $5, 12
599 ; MIPS32-NEXT: or $3, $6, $3
465 ; MIPS32-NEXT: lui $1, 339
466 ; MIPS32-NEXT: ori $1, $1, 28671
467 ; MIPS32-NEXT: multu $4, $1
468 ; MIPS32-NEXT: mflo $2
469 ; MIPS32-NEXT: mfhi $1
470 ; MIPS32-NEXT: sll $3, $5, 12
600471 ; MIPS32-NEXT: addu $3, $3, $5
601 ; MIPS32-NEXT: addu $1, $3, $1
602 ; MIPS32-NEXT: srl $3, $4, 17
603 ; MIPS32-NEXT: sll $6, $5, 15
604 ; MIPS32-NEXT: or $3, $6, $3
605 ; MIPS32-NEXT: addu $1, $3, $1
606 ; MIPS32-NEXT: sll $3, $4, 15
607 ; MIPS32-NEXT: addu $2, $3, $2
608 ; MIPS32-NEXT: sltu $3, $2, $3
609 ; MIPS32-NEXT: addu $1, $1, $3
610 ; MIPS32-NEXT: srl $3, $4, 14
611 ; MIPS32-NEXT: sll $6, $5, 18
612 ; MIPS32-NEXT: or $3, $6, $3
613 ; MIPS32-NEXT: srl $6, $4, 12
614 ; MIPS32-NEXT: sll $7, $5, 20
615 ; MIPS32-NEXT: subu $1, $3, $1
616 ; MIPS32-NEXT: or $3, $7, $6
617 ; MIPS32-NEXT: sll $6, $4, 18
618 ; MIPS32-NEXT: srl $7, $4, 10
619 ; MIPS32-NEXT: sll $8, $5, 22
620 ; MIPS32-NEXT: srl $9, $4, 8
621 ; MIPS32-NEXT: sll $5, $5, 24
622 ; MIPS32-NEXT: or $5, $5, $9
623 ; MIPS32-NEXT: or $7, $8, $7
624 ; MIPS32-NEXT: sltu $8, $6, $2
625 ; MIPS32-NEXT: sll $9, $4, 24
626 ; MIPS32-NEXT: sll $10, $4, 22
627 ; MIPS32-NEXT: sll $4, $4, 20
628 ; MIPS32-NEXT: subu $1, $1, $8
629 ; MIPS32-NEXT: addu $1, $3, $1
630 ; MIPS32-NEXT: subu $2, $6, $2
631 ; MIPS32-NEXT: addu $2, $4, $2
632 ; MIPS32-NEXT: sltu $3, $2, $4
633 ; MIPS32-NEXT: addu $1, $1, $3
634 ; MIPS32-NEXT: addu $1, $7, $1
635 ; MIPS32-NEXT: addu $2, $10, $2
636 ; MIPS32-NEXT: sltu $3, $2, $10
637 ; MIPS32-NEXT: addu $1, $1, $3
638 ; MIPS32-NEXT: addu $1, $5, $1
639 ; MIPS32-NEXT: addu $2, $9, $2
640 ; MIPS32-NEXT: sltu $3, $2, $9
472 ; MIPS32-NEXT: sll $4, $5, 15
473 ; MIPS32-NEXT: addu $3, $4, $3
474 ; MIPS32-NEXT: sll $4, $5, 18
475 ; MIPS32-NEXT: subu $3, $4, $3
476 ; MIPS32-NEXT: sll $4, $5, 20
477 ; MIPS32-NEXT: addu $3, $4, $3
478 ; MIPS32-NEXT: sll $4, $5, 22
479 ; MIPS32-NEXT: addu $3, $4, $3
480 ; MIPS32-NEXT: sll $4, $5, 24
481 ; MIPS32-NEXT: addu $3, $4, $3
641482 ; MIPS32-NEXT: jr $ra
642483 ; MIPS32-NEXT: addu $3, $1, $3
643484 ;