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AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.cvt.pkrtz Patch by Tom Stellard git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326490 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 2 years ago
2 changed file(s) with 79 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
204204 unsigned Size0 = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
205205 OpdsMapping[OpdIdx++] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size0);
206206
207 unsigned Reg1 = MI.getOperand(1).getReg();
207 if (MI.getOperand(OpdIdx).isIntrinsicID())
208 OpdsMapping[OpdIdx++] = nullptr;
209
210 unsigned Reg1 = MI.getOperand(OpdIdx).getReg();
208211 unsigned Size1 = getSizeInBits(Reg1, MRI, *TRI);
209212 unsigned Bank1 = getRegBankID(Reg1, MRI, *TRI);
210213 OpdsMapping[OpdIdx++] = AMDGPU::getValueMapping(Bank1, Size1);
341344 OpdsMapping[1] = nullptr; // Predicate Operand.
342345 OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size);
343346 OpdsMapping[3] = AMDGPU::getValueMapping(Op3Bank, Size);
347 break;
348 }
349 case AMDGPU::G_INTRINSIC: {
350 switch(MI.getOperand(1).getIntrinsicID()) {
351 default:
352 return getInvalidInstructionMapping();
353 case Intrinsic::amdgcn_cvt_pkrtz:
354 return getDefaultMappingVOP(MI);
355 }
344356 break;
345357 }
346358 case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: {
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
2 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
3
4 ---
5 name: cvt_pkrtz_ss
6 legalized: true
7
8 body: |
9 bb.0:
10 liveins: $sgpr0, $sgpr1
11 ; CHECK-LABEL: name: cvt_pkrtz_ss
12 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
13 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
14 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
15 ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), [[COPY]](s32), [[COPY2]](s32)
16 %0:_(s32) = COPY $sgpr0
17 %1:_(s32) = COPY $sgpr1
18 %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1
19 ...
20 ---
21 name: cvt_pkrtz_sv
22 legalized: true
23
24 body: |
25 bb.0:
26 liveins: $sgpr0, $vgpr0
27 ; CHECK-LABEL: name: cvt_pkrtz_sv
28 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
29 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
30 ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), [[COPY]](s32), [[COPY1]](s32)
31 %0:_(s32) = COPY $sgpr0
32 %1:_(s32) = COPY $vgpr0
33 %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1
34 ...
35 ---
36 name: cvt_pkrtz_vs
37 legalized: true
38
39 body: |
40 bb.0:
41 liveins: $sgpr0, $vgpr0
42 ; CHECK-LABEL: name: cvt_pkrtz_vs
43 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
44 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
45 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
46 ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), [[COPY1]](s32), [[COPY2]](s32)
47 %0:_(s32) = COPY $sgpr0
48 %1:_(s32) = COPY $vgpr0
49 %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %1, %0
50 ...
51 ---
52 name: cvt_pkrtz_vv
53 legalized: true
54
55 body: |
56 bb.0:
57 liveins: $vgpr0, $vgpr1
58 ; CHECK-LABEL: name: cvt_pkrtz_vv
59 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
60 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
61 ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), [[COPY]](s32), [[COPY1]](s32)
62 %0:_(s32) = COPY $vgpr0
63 %1:_(s32) = COPY $vgpr1
64 %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1
65 ...