llvm.org GIT mirror llvm / 054a744
Move PPCFrameLowering into PPCSubtarget from PPCTargetMachine. Use the initializeSubtargetDependencies code to obtain an initialized subtarget and migrate a couple of subtarget using functions to the .cpp file to avoid circular includes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210822 91177308-0d34-0410-b5e6-96231b3b80d8 Eric Christopher 5 years ago
6 changed file(s) with 211 addition(s) and 196 deletion(s). Raw diff Collapse all Expand all
1414 #include "PPCInstrBuilder.h"
1515 #include "PPCInstrInfo.h"
1616 #include "PPCMachineFunctionInfo.h"
17 #include "PPCSubtarget.h"
1718 #include "llvm/CodeGen/MachineFrameInfo.h"
1819 #include "llvm/CodeGen/MachineFunction.h"
1920 #include "llvm/CodeGen/MachineInstrBuilder.h"
3334 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
3435 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
3536 };
37
38 PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI)
39 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
40 (STI.hasQPX() || STI.isBGQ()) ? 32 : 16, 0),
41 Subtarget(STI) {}
42
43 unsigned PPCFrameLowering::getMinCallArgumentsSize(bool isPPC64,
44 bool isDarwinABI) {
45 // For the Darwin ABI / 64-bit SVR4 ABI:
46 // The prolog code of the callee may store up to 8 GPR argument registers to
47 // the stack, allowing va_start to index over them in memory if its varargs.
48 // Because we cannot tell if this is needed on the caller side, we have to
49 // conservatively assume that it is needed. As such, make sure we have at
50 // least enough stack space for the caller to store the 8 GPRs.
51 if (isDarwinABI || isPPC64)
52 return 8 * (isPPC64 ? 8 : 4);
53
54 // 32-bit SVR4 ABI:
55 // There is no default stack allocated for the 8 first GPR arguments.
56 return 0;
57 }
58
59 /// getMinCallFrameSize - Return the minimum size a call frame can be using
60 /// the PowerPC ABI.
61 unsigned PPCFrameLowering::getMinCallFrameSize(bool isPPC64, bool isDarwinABI) {
62 // The call frame needs to be at least big enough for linkage and 8 args.
63 return PPCFrameLowering::getLinkageSize(isPPC64, isDarwinABI) +
64 PPCFrameLowering::getMinCallArgumentsSize(isPPC64, isDarwinABI);
65 }
66
67 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
68 const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots(
69 unsigned &NumEntries) const {
70 if (Subtarget.isDarwinABI()) {
71 NumEntries = 1;
72 if (Subtarget.isPPC64()) {
73 static const SpillSlot darwin64Offsets = {PPC::X31, -8};
74 return &darwin64Offsets;
75 } else {
76 static const SpillSlot darwinOffsets = {PPC::R31, -4};
77 return &darwinOffsets;
78 }
79 }
80
81 // Early exit if not using the SVR4 ABI.
82 if (!Subtarget.isSVR4ABI()) {
83 NumEntries = 0;
84 return nullptr;
85 }
86
87 // Note that the offsets here overlap, but this is fixed up in
88 // processFunctionBeforeFrameFinalized.
89
90 static const SpillSlot Offsets[] = {
91 // Floating-point register save area offsets.
92 {PPC::F31, -8},
93 {PPC::F30, -16},
94 {PPC::F29, -24},
95 {PPC::F28, -32},
96 {PPC::F27, -40},
97 {PPC::F26, -48},
98 {PPC::F25, -56},
99 {PPC::F24, -64},
100 {PPC::F23, -72},
101 {PPC::F22, -80},
102 {PPC::F21, -88},
103 {PPC::F20, -96},
104 {PPC::F19, -104},
105 {PPC::F18, -112},
106 {PPC::F17, -120},
107 {PPC::F16, -128},
108 {PPC::F15, -136},
109 {PPC::F14, -144},
110
111 // General register save area offsets.
112 {PPC::R31, -4},
113 {PPC::R30, -8},
114 {PPC::R29, -12},
115 {PPC::R28, -16},
116 {PPC::R27, -20},
117 {PPC::R26, -24},
118 {PPC::R25, -28},
119 {PPC::R24, -32},
120 {PPC::R23, -36},
121 {PPC::R22, -40},
122 {PPC::R21, -44},
123 {PPC::R20, -48},
124 {PPC::R19, -52},
125 {PPC::R18, -56},
126 {PPC::R17, -60},
127 {PPC::R16, -64},
128 {PPC::R15, -68},
129 {PPC::R14, -72},
130
131 // CR save area offset. We map each of the nonvolatile CR fields
132 // to the slot for CR2, which is the first of the nonvolatile CR
133 // fields to be assigned, so that we only allocate one save slot.
134 // See PPCRegisterInfo::hasReservedSpillSlot() for more information.
135 {PPC::CR2, -4},
136
137 // VRSAVE save area offset.
138 {PPC::VRSAVE, -4},
139
140 // Vector register save area
141 {PPC::V31, -16},
142 {PPC::V30, -32},
143 {PPC::V29, -48},
144 {PPC::V28, -64},
145 {PPC::V27, -80},
146 {PPC::V26, -96},
147 {PPC::V25, -112},
148 {PPC::V24, -128},
149 {PPC::V23, -144},
150 {PPC::V22, -160},
151 {PPC::V21, -176},
152 {PPC::V20, -192}};
153
154 static const SpillSlot Offsets64[] = {
155 // Floating-point register save area offsets.
156 {PPC::F31, -8},
157 {PPC::F30, -16},
158 {PPC::F29, -24},
159 {PPC::F28, -32},
160 {PPC::F27, -40},
161 {PPC::F26, -48},
162 {PPC::F25, -56},
163 {PPC::F24, -64},
164 {PPC::F23, -72},
165 {PPC::F22, -80},
166 {PPC::F21, -88},
167 {PPC::F20, -96},
168 {PPC::F19, -104},
169 {PPC::F18, -112},
170 {PPC::F17, -120},
171 {PPC::F16, -128},
172 {PPC::F15, -136},
173 {PPC::F14, -144},
174
175 // General register save area offsets.
176 {PPC::X31, -8},
177 {PPC::X30, -16},
178 {PPC::X29, -24},
179 {PPC::X28, -32},
180 {PPC::X27, -40},
181 {PPC::X26, -48},
182 {PPC::X25, -56},
183 {PPC::X24, -64},
184 {PPC::X23, -72},
185 {PPC::X22, -80},
186 {PPC::X21, -88},
187 {PPC::X20, -96},
188 {PPC::X19, -104},
189 {PPC::X18, -112},
190 {PPC::X17, -120},
191 {PPC::X16, -128},
192 {PPC::X15, -136},
193 {PPC::X14, -144},
194
195 // VRSAVE save area offset.
196 {PPC::VRSAVE, -4},
197
198 // Vector register save area
199 {PPC::V31, -16},
200 {PPC::V30, -32},
201 {PPC::V29, -48},
202 {PPC::V28, -64},
203 {PPC::V27, -80},
204 {PPC::V26, -96},
205 {PPC::V25, -112},
206 {PPC::V24, -128},
207 {PPC::V23, -144},
208 {PPC::V22, -160},
209 {PPC::V21, -176},
210 {PPC::V20, -192}};
211
212 if (Subtarget.isPPC64()) {
213 NumEntries = array_lengthof(Offsets64);
214
215 return Offsets64;
216 } else {
217 NumEntries = array_lengthof(Offsets);
218
219 return Offsets;
220 }
221 }
36222
37223 /// RemoveVRSaveCode - We have found that this function does not need any code
38224 /// to manipulate the VRSAVE register, even though it uses vector registers.
1313 #define POWERPC_FRAMEINFO_H
1414
1515 #include "PPC.h"
16 #include "PPCSubtarget.h"
1716 #include "llvm/ADT/STLExtras.h"
1817 #include "llvm/Target/TargetFrameLowering.h"
1918 #include "llvm/Target/TargetMachine.h"
2019
2120 namespace llvm {
22 class PPCSubtarget;
21 class PPCSubtarget;
2322
2423 class PPCFrameLowering: public TargetFrameLowering {
2524 const PPCSubtarget &Subtarget;
2625
2726 public:
28 PPCFrameLowering(const PPCSubtarget &sti)
29 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
30 (sti.hasQPX() || sti.isBGQ()) ? 32 : 16, 0),
31 Subtarget(sti) {
32 }
27 PPCFrameLowering(const PPCSubtarget &STI);
3328
3429 unsigned determineFrameLayout(MachineFunction &MF,
3530 bool UpdateMF = true,
115110
116111 /// getMinCallArgumentsSize - Return the size of the minium PowerPC ABI
117112 /// argument area.
118 static unsigned getMinCallArgumentsSize(bool isPPC64, bool isDarwinABI) {
119 // For the Darwin ABI / 64-bit SVR4 ABI:
120 // The prolog code of the callee may store up to 8 GPR argument registers to
121 // the stack, allowing va_start to index over them in memory if its varargs.
122 // Because we cannot tell if this is needed on the caller side, we have to
123 // conservatively assume that it is needed. As such, make sure we have at
124 // least enough stack space for the caller to store the 8 GPRs.
125 if (isDarwinABI || isPPC64)
126 return 8 * (isPPC64 ? 8 : 4);
127
128 // 32-bit SVR4 ABI:
129 // There is no default stack allocated for the 8 first GPR arguments.
130 return 0;
131 }
132
133 /// getMinCallFrameSize - Return the minimum size a call frame can be using
134 /// the PowerPC ABI.
135 static unsigned getMinCallFrameSize(bool isPPC64, bool isDarwinABI) {
136 // The call frame needs to be at least big enough for linkage and 8 args.
137 return getLinkageSize(isPPC64, isDarwinABI) +
138 getMinCallArgumentsSize(isPPC64, isDarwinABI);
139 }
140
141 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
113 static unsigned getMinCallArgumentsSize(bool isPPC64, bool isDarwinABI);
142114 const SpillSlot *
143 getCalleeSavedSpillSlots(unsigned &NumEntries) const override {
144 if (Subtarget.isDarwinABI()) {
145 NumEntries = 1;
146 if (Subtarget.isPPC64()) {
147 static const SpillSlot darwin64Offsets = {PPC::X31, -8};
148 return &darwin64Offsets;
149 } else {
150 static const SpillSlot darwinOffsets = {PPC::R31, -4};
151 return &darwinOffsets;
152 }
153 }
154
155 // Early exit if not using the SVR4 ABI.
156 if (!Subtarget.isSVR4ABI()) {
157 NumEntries = 0;
158 return nullptr;
159 }
160
161 // Note that the offsets here overlap, but this is fixed up in
162 // processFunctionBeforeFrameFinalized.
163
164 static const SpillSlot Offsets[] = {
165 // Floating-point register save area offsets.
166 {PPC::F31, -8},
167 {PPC::F30, -16},
168 {PPC::F29, -24},
169 {PPC::F28, -32},
170 {PPC::F27, -40},
171 {PPC::F26, -48},
172 {PPC::F25, -56},
173 {PPC::F24, -64},
174 {PPC::F23, -72},
175 {PPC::F22, -80},
176 {PPC::F21, -88},
177 {PPC::F20, -96},
178 {PPC::F19, -104},
179 {PPC::F18, -112},
180 {PPC::F17, -120},
181 {PPC::F16, -128},
182 {PPC::F15, -136},
183 {PPC::F14, -144},
184
185 // General register save area offsets.
186 {PPC::R31, -4},
187 {PPC::R30, -8},
188 {PPC::R29, -12},
189 {PPC::R28, -16},
190 {PPC::R27, -20},
191 {PPC::R26, -24},
192 {PPC::R25, -28},
193 {PPC::R24, -32},
194 {PPC::R23, -36},
195 {PPC::R22, -40},
196 {PPC::R21, -44},
197 {PPC::R20, -48},
198 {PPC::R19, -52},
199 {PPC::R18, -56},
200 {PPC::R17, -60},
201 {PPC::R16, -64},
202 {PPC::R15, -68},
203 {PPC::R14, -72},
204
205 // CR save area offset. We map each of the nonvolatile CR fields
206 // to the slot for CR2, which is the first of the nonvolatile CR
207 // fields to be assigned, so that we only allocate one save slot.
208 // See PPCRegisterInfo::hasReservedSpillSlot() for more information.
209 {PPC::CR2, -4},
210
211 // VRSAVE save area offset.
212 {PPC::VRSAVE, -4},
213
214 // Vector register save area
215 {PPC::V31, -16},
216 {PPC::V30, -32},
217 {PPC::V29, -48},
218 {PPC::V28, -64},
219 {PPC::V27, -80},
220 {PPC::V26, -96},
221 {PPC::V25, -112},
222 {PPC::V24, -128},
223 {PPC::V23, -144},
224 {PPC::V22, -160},
225 {PPC::V21, -176},
226 {PPC::V20, -192}
227 };
228
229 static const SpillSlot Offsets64[] = {
230 // Floating-point register save area offsets.
231 {PPC::F31, -8},
232 {PPC::F30, -16},
233 {PPC::F29, -24},
234 {PPC::F28, -32},
235 {PPC::F27, -40},
236 {PPC::F26, -48},
237 {PPC::F25, -56},
238 {PPC::F24, -64},
239 {PPC::F23, -72},
240 {PPC::F22, -80},
241 {PPC::F21, -88},
242 {PPC::F20, -96},
243 {PPC::F19, -104},
244 {PPC::F18, -112},
245 {PPC::F17, -120},
246 {PPC::F16, -128},
247 {PPC::F15, -136},
248 {PPC::F14, -144},
249
250 // General register save area offsets.
251 {PPC::X31, -8},
252 {PPC::X30, -16},
253 {PPC::X29, -24},
254 {PPC::X28, -32},
255 {PPC::X27, -40},
256 {PPC::X26, -48},
257 {PPC::X25, -56},
258 {PPC::X24, -64},
259 {PPC::X23, -72},
260 {PPC::X22, -80},
261 {PPC::X21, -88},
262 {PPC::X20, -96},
263 {PPC::X19, -104},
264 {PPC::X18, -112},
265 {PPC::X17, -120},
266 {PPC::X16, -128},
267 {PPC::X15, -136},
268 {PPC::X14, -144},
269
270 // VRSAVE save area offset.
271 {PPC::VRSAVE, -4},
272
273 // Vector register save area
274 {PPC::V31, -16},
275 {PPC::V30, -32},
276 {PPC::V29, -48},
277 {PPC::V28, -64},
278 {PPC::V27, -80},
279 {PPC::V26, -96},
280 {PPC::V25, -112},
281 {PPC::V24, -128},
282 {PPC::V23, -144},
283 {PPC::V22, -160},
284 {PPC::V21, -176},
285 {PPC::V20, -192}
286 };
287
288 if (Subtarget.isPPC64()) {
289 NumEntries = array_lengthof(Offsets64);
290
291 return Offsets64;
292 } else {
293 NumEntries = array_lengthof(Offsets);
294
295 return Offsets;
296 }
297 }
115 getCalleeSavedSpillSlots(unsigned &NumEntries) const override;
116 static unsigned getMinCallFrameSize(bool isPPC64, bool isDarwinABI);
298117 };
299
300118 } // End llvm namespace
301119
302120 #endif
3131 #define GET_SUBTARGETINFO_CTOR
3232 #include "PPCGenSubtargetInfo.inc"
3333
34 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
35 StringRef FS) {
36 initializeEnvironment();
37 resetSubtargetFeatures(CPU, FS);
38 return *this;
39 }
40
3441 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
3542 const std::string &FS, bool is64Bit,
3643 CodeGenOpt::Level OptLevel)
3744 : PPCGenSubtargetInfo(TT, CPU, FS), IsPPC64(is64Bit), TargetTriple(TT),
38 OptLevel(OptLevel) {
39 initializeEnvironment();
40 resetSubtargetFeatures(CPU, FS);
41 }
45 OptLevel(OptLevel),
46 FrameLowering(initializeSubtargetDependencies(CPU, FS)) {}
4247
4348 /// SetJITMode - This is called to inform the subtarget info that we are
4449 /// producing code for the JIT.
1313 #ifndef POWERPCSUBTARGET_H
1414 #define POWERPCSUBTARGET_H
1515
16 #include "PPCFrameLowering.h"
1617 #include "llvm/ADT/Triple.h"
1718 #include "llvm/MC/MCInstrItineraries.h"
1819 #include "llvm/Target/TargetSubtargetInfo.h"
101102 /// OptLevel - What default optimization level we're emitting code for.
102103 CodeGenOpt::Level OptLevel;
103104
105 PPCFrameLowering FrameLowering;
104106 public:
105107 /// This constructor initializes the data members to match that
106108 /// of the specified triple.
129131 /// getInstrItins - Return the instruction itineraies based on subtarget
130132 /// selection.
131133 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
134
135 const PPCFrameLowering *getFrameLowering() const { return &FrameLowering; }
136
137 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
138 /// so that we can use initializer lists for subtarget initialization.
139 PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
132140
133141 /// \brief Reset the features for the PowerPC target.
134142 void resetSubtargetFeatures(const MachineFunction *MF) override;
7777 CodeGenOpt::Level OL, bool is64Bit)
7878 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
7979 Subtarget(TT, CPU, FS, is64Bit, OL), DL(getDataLayoutString(Subtarget)),
80 InstrInfo(*this), FrameLowering(Subtarget), JITInfo(*this, is64Bit),
81 TLInfo(*this), TSInfo(*this) {
80 InstrInfo(*this), JITInfo(*this, is64Bit), TLInfo(*this), TSInfo(*this) {
8281 initAsmInfo();
8382 }
8483
3030 PPCSubtarget Subtarget;
3131 const DataLayout DL; // Calculates type size & alignment
3232 PPCInstrInfo InstrInfo;
33 PPCFrameLowering FrameLowering;
3433 PPCJITInfo JITInfo;
3534 PPCTargetLowering TLInfo;
3635 PPCSelectionDAGInfo TSInfo;
4241 CodeGenOpt::Level OL, bool is64Bit);
4342
4443 const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
45 const PPCFrameLowering *getFrameLowering() const override {
46 return &FrameLowering;
44 const PPCFrameLowering *getFrameLowering() const override {
45 return getSubtargetImpl()->getFrameLowering();
4746 }
4847 PPCJITInfo *getJITInfo() override { return &JITInfo; }
4948 const PPCTargetLowering *getTargetLowering() const override {