llvm.org GIT mirror llvm / 04c528a
Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway. TII::isMoveInstr is going tobe completely removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108507 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 10 years ago
15 changed file(s) with 75 addition(s) and 229 deletion(s). Raw diff Collapse all Expand all
509509 }
510510
511511 // Check for spill-induced copies
512 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
513 if (TM.getInstrInfo()->isMoveInstr(MI, SrcReg, DstReg,
514 SrcSubIdx, DstSubIdx)) {
515 if (MI.getAsmPrinterFlag(MachineInstr::ReloadReuse))
516 CommentOS << " Reload Reuse\n";
517 }
512 if (MI.getAsmPrinterFlag(MachineInstr::ReloadReuse))
513 CommentOS << " Reload Reuse\n";
518514 }
519515
520516 /// EmitImplicitDef - This method emits the specified machine instruction
187187 const MachineInstr &MI = *I;
188188
189189 // Allow copies to and from li.reg
190 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
191 if (tii_->isMoveInstr(MI, SrcReg, DstReg, SrcSubReg, DstSubReg))
192 if (SrcReg == li.reg || DstReg == li.reg)
193 continue;
194190 if (MI.isCopy())
195191 if (MI.getOperand(0).getReg() == li.reg ||
196192 MI.getOperand(1).getReg() == li.reg)
323319 mi->addRegisterDefined(interval.reg);
324320
325321 MachineInstr *CopyMI = NULL;
326 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
327 if (mi->isCopyLike() ||
328 tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
322 if (mi->isCopyLike()) {
329323 CopyMI = mi;
330324 }
331325
453447 OldValNo->setCopy(0);
454448
455449 // A re-def may be a copy. e.g. %reg1030:6 = VMOVD %reg1026, ...
456 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
457 if (PartReDef && (mi->isCopyLike() ||
458 tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg)))
450 if (PartReDef && mi->isCopyLike())
459451 OldValNo->setCopy(&*mi);
460452
461453 // Add the new live interval which replaces the range for the input copy.
484476
485477 VNInfo *ValNo;
486478 MachineInstr *CopyMI = NULL;
487 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
488 if (mi->isCopyLike() ||
489 tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg))
479 if (mi->isCopyLike())
490480 CopyMI = mi;
491481 ValNo = interval.getNextValue(defIndex, CopyMI, true, VNInfoAllocator);
492482
601591 getOrCreateInterval(MO.getReg()));
602592 else if (allocatableRegs_[MO.getReg()]) {
603593 MachineInstr *CopyMI = NULL;
604 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
605 if (MI->isCopyLike() ||
606 tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg))
594 if (MI->isCopyLike())
607595 CopyMI = MI;
608596 handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
609597 getOrCreateInterval(MO.getReg()), CopyMI);
106106 MachineInstr *DefMI = MRI->getVRegDef(Reg);
107107 if (DefMI->getParent() != MBB)
108108 continue;
109 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
110 if (TII->isMoveInstr(*DefMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
111 TargetRegisterInfo::isVirtualRegister(SrcReg) &&
112 !SrcSubIdx && !DstSubIdx) {
113 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
114 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
115 const TargetRegisterClass *NewRC = getCommonSubClass(RC, SRC);
116 if (!NewRC)
117 continue;
118 DEBUG(dbgs() << "Coalescing: " << *DefMI);
119 DEBUG(dbgs() << "*** to: " << *MI);
120 MO.setReg(SrcReg);
121 MRI->clearKillFlags(SrcReg);
122 if (NewRC != SRC)
123 MRI->setRegClass(SrcReg, NewRC);
124 DefMI->eraseFromParent();
125 ++NumCoalesces;
126 Changed = true;
127 }
128
129109 if (!DefMI->isCopy())
130110 continue;
131 SrcReg = DefMI->getOperand(1).getReg();
111 unsigned SrcReg = DefMI->getOperand(1).getReg();
132112 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
133113 continue;
134114 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg())
260240 return false;
261241 }
262242
263 static bool isCopy(const MachineInstr *MI, const TargetInstrInfo *TII) {
264 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
265 return MI->isCopyLike() ||
266 TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
267 }
268
269243 bool MachineCSE::isCSECandidate(MachineInstr *MI) {
270244 if (MI->isLabel() || MI->isPHI() || MI->isImplicitDef() ||
271245 MI->isKill() || MI->isInlineAsm() || MI->isDebugValue())
272246 return false;
273247
274248 // Ignore copies.
275 if (isCopy(MI, TII))
249 if (MI->isCopyLike())
276250 return false;
277251
278252 // Ignore stuff that we obviously can't move.
328302 E = MRI->use_nodbg_end(); I != E; ++I) {
329303 MachineInstr *Use = &*I;
330304 // Ignore copies.
331 if (!isCopy(Use, TII)) {
305 if (!Use->isCopyLike()) {
332306 HasNonCopyUse = true;
333307 break;
334308 }
384358 // Look for trivial copy coalescing opportunities.
385359 if (PerformTrivialCoalescing(MI, MBB)) {
386360 // After coalescing MI itself may become a copy.
387 if (isCopy(MI, TII))
361 if (MI->isCopyLike())
388362 continue;
389363 FoundCSE = VNT.count(MI);
390364 }
100100 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
101101
102102 // Skip over register-to-register moves.
103 unsigned MvSrcReg, MvDstReg, SrcSubIdx, DstSubIdx;
104 if (SrcMI &&
105 TII->isMoveInstr(*SrcMI, MvSrcReg, MvDstReg, SrcSubIdx, DstSubIdx) &&
106 SrcSubIdx == 0 && DstSubIdx == 0 &&
107 TargetRegisterInfo::isVirtualRegister(MvSrcReg))
108 SrcMI = MRI->getVRegDef(MvSrcReg);
109 else if (SrcMI && SrcMI->isCopy() &&
110 !SrcMI->getOperand(0).getSubReg() &&
111 !SrcMI->getOperand(1).getSubReg() &&
112 TargetRegisterInfo::isVirtualRegister(SrcMI->getOperand(1).getReg()))
103 if (SrcMI && SrcMI->isCopy() &&
104 !SrcMI->getOperand(0).getSubReg() &&
105 !SrcMI->getOperand(1).getSubReg() &&
106 TargetRegisterInfo::isVirtualRegister(SrcMI->getOperand(1).getReg()))
113107 SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
114108 if (!SrcMI)
115109 return false;
675675 VNInfo* NewVN = LI->getNextValue(DefIdx, 0, true, Alloc);
676676
677677 // If the def is a move, set the copy field.
678 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
679 if (TII->isMoveInstr(*DI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
680 if (DstReg == LI->reg)
681 NewVN->setCopy(&*DI);
682 } else if (DI->isCopyLike() && DI->getOperand(0).getReg() == LI->reg)
678 if (DI->isCopyLike() && DI->getOperand(0).getReg() == LI->reg)
683679 NewVN->setCopy(&*DI);
684680
685681 NewVNs[&*DI] = NewVN;
4545 unsigned Reg, unsigned OpIdx,
4646 const TargetInstrInfo *tii_,
4747 SmallSet &ImpDefRegs) {
48 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
49 if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
50 Reg == SrcReg &&
51 (DstSubReg == 0 || ImpDefRegs.count(DstReg)))
52 return true;
53
5448 switch(OpIdx) {
5549 case 1:
5650 return MI->isCopy() && (MI->getOperand(0).getSubReg() == 0 ||
7367 if (!MO0.getSubReg() || ImpDefRegs.count(MO0.getReg()))
7468 return true;
7569 return false;
76 }
77
78 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
79 if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
80 if (Reg != SrcReg)
81 return false;
82 if (DstSubReg == 0 || ImpDefRegs.count(DstReg))
83 return true;
8470 }
8571 return false;
8672 }
519519 if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) &&
520520 MRI->hasOneNonDBGUse(VirtReg)) {
521521 const MachineInstr &UseMI = *MRI->use_nodbg_begin(VirtReg);
522 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
523522 // It's a copy, use the destination register as a hint.
524523 if (UseMI.isCopyLike())
525524 Hint = UseMI.getOperand(0).getReg();
526 else if (TII->isMoveInstr(UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
527 Hint = DstReg;
528525 }
529526 allocVirtReg(MI, *LRI, Hint);
530527 } else if (LR.LastUse) {
788785 }
789786
790787 // If this is a copy, we may be able to coalesce.
791 unsigned CopySrc, CopyDst, CopySrcSub, CopyDstSub;
788 unsigned CopySrc = 0, CopyDst = 0, CopySrcSub = 0, CopyDstSub = 0;
792789 if (MI->isCopy()) {
793790 CopyDst = MI->getOperand(0).getReg();
794791 CopySrc = MI->getOperand(1).getReg();
795792 CopyDstSub = MI->getOperand(0).getSubReg();
796793 CopySrcSub = MI->getOperand(1).getSubReg();
797 } else if (!TII->isMoveInstr(*MI, CopySrc, CopyDst, CopySrcSub, CopyDstSub))
798 CopySrc = CopyDst = 0;
794 }
799795
800796 // Track registers used by instruction.
801797 UsedInInstr.reset();
418418 unsigned CandReg;
419419 {
420420 MachineInstr *CopyMI;
421 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
422421 if (vni->def != SlotIndex() && vni->isDefAccurate() &&
423 (CopyMI = li_->getInstructionFromIndex(vni->def)) &&
424 (CopyMI->isCopy() ||
425 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)))
422 (CopyMI = li_->getInstructionFromIndex(vni->def)) && CopyMI->isCopy())
426423 // Defined by a copy, try to extend SrcReg forward
427 CandReg = CopyMI->isCopy() ? CopyMI->getOperand(1).getReg() : SrcReg;
424 CandReg = CopyMI->getOperand(1).getReg();
428425 else if (TrivCoalesceEnds &&
429 (CopyMI =
430 li_->getInstructionFromIndex(range.end.getBaseIndex())) &&
431 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
432 cur.reg == SrcReg)
426 (CopyMI = li_->getInstructionFromIndex(range.end.getBaseIndex())) &&
427 CopyMI->isCopy() && cur.reg == CopyMI->getOperand(1).getReg())
433428 // Only used by a copy, try to extend DstReg backwards
434 CandReg = DstReg;
429 CandReg = CopyMI->getOperand(0).getReg();
435430 else
436431 return Reg;
437432 }
977972 if ((vni->def != SlotIndex()) && !vni->isUnused() &&
978973 vni->isDefAccurate()) {
979974 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
980 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
981 if (CopyMI &&
982 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
983 unsigned Reg = 0;
984 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
985 Reg = SrcReg;
986 else if (vrm_->isAssignedReg(SrcReg))
987 Reg = vrm_->getPhys(SrcReg);
988 if (Reg) {
989 if (SrcSubReg)
990 Reg = tri_->getSubReg(Reg, SrcSubReg);
991 if (DstSubReg)
992 Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
993 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
994 mri_->setRegAllocationHint(cur->reg, 0, Reg);
995 }
996 } else if (CopyMI && CopyMI->isCopy()) {
997 DstReg = CopyMI->getOperand(0).getReg();
998 DstSubReg = CopyMI->getOperand(0).getSubReg();
999 SrcReg = CopyMI->getOperand(1).getReg();
1000 SrcSubReg = CopyMI->getOperand(1).getSubReg();
975 if (CopyMI && CopyMI->isCopy()) {
976 unsigned DstSubReg = CopyMI->getOperand(0).getSubReg();
977 unsigned SrcReg = CopyMI->getOperand(1).getReg();
978 unsigned SrcSubReg = CopyMI->getOperand(1).getSubReg();
1001979 unsigned Reg = 0;
1002980 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
1003981 Reg = SrcReg;
378378 iItr != iEnd; ++iItr) {
379379
380380 const MachineInstr *instr = &*iItr;
381 unsigned srcReg, dstReg, srcSubReg, dstSubReg;
382381
383382 // If this isn't a copy then continue to the next instruction.
384 if (!tii->isMoveInstr(*instr, srcReg, dstReg, srcSubReg, dstSubReg))
383 if (!instr->isCopy())
385384 continue;
385
386 unsigned srcReg = instr->getOperand(1).getReg();
387 unsigned dstReg = instr->getOperand(0).getReg();
386388
387389 // If the registers are already the same our job is nice and easy.
388390 if (dstReg == srcReg)
5353 DstSub = compose(MI->getOperand(0).getSubReg(), MI->getOperand(3).getImm());
5454 Src = MI->getOperand(2).getReg();
5555 SrcSub = MI->getOperand(2).getSubReg();
56 } else if (!tii_.isMoveInstr(*MI, Src, Dst, SrcSub, DstSub)) {
56 } else
5757 return false;
58 }
5958 return true;
6059 }
6160
469469 if (Extended)
470470 UseMO.setIsKill(false);
471471 }
472 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
473 if (UseMI->isCopy()) {
474 if (UseMI->getOperand(0).getReg() != IntB.reg ||
475 UseMI->getOperand(0).getSubReg())
476 continue;
477 } else if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){
478 if (DstReg != IntB.reg || DstSubIdx)
479 continue;
480 } else
472 if (!UseMI->isCopy())
481473 continue;
474 if (UseMI->getOperand(0).getReg() != IntB.reg ||
475 UseMI->getOperand(0).getSubReg())
476 continue;
477
482478 // This copy will become a noop. If it's defining a new val#,
483479 // remove that val# as well. However this live range is being
484480 // extended to the end of the existing live range defined by the copy.
627623 if (DefMO.getReg() == li.reg && !DefMO.getSubReg())
628624 DefMO.setIsDead();
629625 }
630 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
631 if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
632 DstReg == li.reg && DstSubIdx == 0) {
633 // Last use is itself an identity code.
634 int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg,
635 false, false, tri_);
636 LastUseMI->getOperand(DeadIdx).setIsDead();
637 }
638626 return true;
639627 }
640628
771759 // A PhysReg copy that won't be coalesced can perhaps be rematerialized
772760 // instead.
773761 if (DstIsPhys) {
774 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
775 if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
776 CopySrcSubIdx, CopyDstSubIdx) &&
777 CopySrcSubIdx == 0 && CopyDstSubIdx == 0 &&
778 CopySrcReg != CopyDstReg && CopySrcReg == SrcReg &&
779 CopyDstReg != DstReg && !JoinedCopies.count(UseMI) &&
780 ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg, 0,
781 UseMI))
782 continue;
783
784762 if (UseMI->isCopy() &&
785763 !UseMI->getOperand(1).getSubReg() &&
786764 !UseMI->getOperand(0).getSubReg() &&
833811 dbgs() << li_->getInstructionIndex(UseMI) << "\t";
834812 dbgs() << *UseMI;
835813 });
836
837
838 // After updating the operand, check if the machine instruction has
839 // become a copy. If so, update its val# information.
840 const TargetInstrDesc &TID = UseMI->getDesc();
841 if (DstIsPhys || TID.getNumDefs() != 1 || TID.getNumOperands() <= 2)
842 continue;
843
844 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
845 if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
846 CopySrcSubIdx, CopyDstSubIdx) &&
847 CopySrcReg != CopyDstReg &&
848 (TargetRegisterInfo::isVirtualRegister(CopyDstReg) ||
849 allocatableRegs_[CopyDstReg])) {
850 LiveInterval &LI = li_->getInterval(CopyDstReg);
851 SlotIndex DefIdx =
852 li_->getInstructionIndex(UseMI).getDefIndex();
853 if (const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx)) {
854 if (DLR->valno->def == DefIdx)
855 DLR->valno->setCopy(UseMI);
856 }
857 }
858814 }
859815 }
860816
15421498 MachineInstr *Inst = MII++;
15431499
15441500 // If this isn't a copy nor a extract_subreg, we can't join intervals.
1545 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1546 bool isInsUndef = false;
1501 unsigned SrcReg, DstReg;
15471502 if (Inst->isCopy()) {
15481503 DstReg = Inst->getOperand(0).getReg();
15491504 SrcReg = Inst->getOperand(1).getReg();
15501505 } else if (Inst->isSubregToReg()) {
15511506 DstReg = Inst->getOperand(0).getReg();
15521507 SrcReg = Inst->getOperand(2).getReg();
1553 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
1508 } else
15541509 continue;
15551510
15561511 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
15571512 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1558 if (isInsUndef ||
1559 (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty()))
1513 if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
15601514 ImpDefCopies.push_back(CopyRec(Inst, 0));
15611515 else if (SrcIsPhys || DstIsPhys)
15621516 PhysCopies.push_back(CopyRec(Inst, 0));
16781632 MachineInstr *UseMI = Use.getParent();
16791633 if (UseMI->isIdentityCopy())
16801634 continue;
1681 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1682 if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
1683 SrcReg == DstReg && SrcSubIdx == DstSubIdx)
1684 // Ignore identity copies.
1685 continue;
16861635 SlotIndex Idx = li_->getInstructionIndex(UseMI);
16871636 // FIXME: Should this be Idx != UseIdx? SlotIndex() will return something
16881637 // that compares higher than any other interval.
17071656 return NULL;
17081657
17091658 // Ignore identity copies.
1710 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1711 if (!MI->isIdentityCopy() &&
1712 !(tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
1713 SrcReg == DstReg && SrcSubIdx == DstSubIdx))
1659 if (!MI->isIdentityCopy())
17141660 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
17151661 MachineOperand &Use = MI->getOperand(i);
17161662 if (Use.isReg() && Use.isUse() && Use.getReg() &&
17741720 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
17751721 mii != mie; ) {
17761722 MachineInstr *MI = mii;
1777 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
17781723 if (JoinedCopies.count(MI)) {
17791724 // Delete all coalesced copies.
17801725 bool DoDelete = true;
1781 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
1782 assert(MI->isCopyLike() && "Unrecognized copy instruction");
1783 SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg();
1784 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
1785 // Do not delete extract_subreg, insert_subreg of physical
1786 // registers unless the definition is dead. e.g.
1787 // %DO = INSERT_SUBREG %D0, %S0, 1
1788 // or else the scavenger may complain. LowerSubregs will
1789 // delete them later.
1790 DoDelete = false;
1791 }
1726 assert(MI->isCopyLike() && "Unrecognized copy instruction");
1727 unsigned SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg();
1728 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
1729 // Do not delete extract_subreg, insert_subreg of physical
1730 // registers unless the definition is dead. e.g.
1731 // %DO = INSERT_SUBREG %D0, %S0, 1
1732 // or else the scavenger may complain. LowerSubregs will
1733 // delete them later.
1734 DoDelete = false;
1735
17921736 if (MI->allDefsAreDead()) {
17931737 LiveInterval &li = li_->getInterval(SrcReg);
17941738 if (!ShortenDeadCopySrcLiveRange(li, MI))
18391783 }
18401784
18411785 // If the move will be an identity move delete it
1842 bool isMove= tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
1843 if (MI->isIdentityCopy() ||
1844 (isMove && SrcReg == DstReg && SrcSubIdx == DstSubIdx)) {
1786 if (MI->isIdentityCopy()) {
1787 unsigned SrcReg = MI->getOperand(1).getReg();
18451788 if (li_->hasInterval(SrcReg)) {
18461789 LiveInterval &RegInt = li_->getInterval(SrcReg);
18471790 // If def of this move instruction is dead, remove its live range
253253 // SSA form.
254254 for (unsigned i = 0, e = Copies.size(); i != e; ++i) {
255255 MachineInstr *Copy = Copies[i];
256 unsigned Src, Dst, SrcSR, DstSR;
257 if (TII->isMoveInstr(*Copy, Src, Dst, SrcSR, DstSR)) {
258 MachineRegisterInfo::use_iterator UI = MRI->use_begin(Src);
259 if (++UI == MRI->use_end()) {
260 // Copy is the only use. Do trivial copy propagation here.
261 MRI->replaceRegWith(Dst, Src);
262 Copy->eraseFromParent();
263 }
256 if (!Copy->isCopy())
257 continue;
258 unsigned Dst = Copy->getOperand(0).getReg();
259 unsigned Src = Copy->getOperand(1).getReg();
260 MachineRegisterInfo::use_iterator UI = MRI->use_begin(Src);
261 if (++UI == MRI->use_end()) {
262 // Copy is the only use. Do trivial copy propagation here.
263 MRI->replaceRegWith(Dst, Src);
264 Copy->eraseFromParent();
264265 }
265266 }
266267
379379 bool &IsSrcPhys, bool &IsDstPhys) {
380380 SrcReg = 0;
381381 DstReg = 0;
382 unsigned SrcSubIdx, DstSubIdx;
383 if (!TII->isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
384 if (MI.isCopy()) {
385 DstReg = MI.getOperand(0).getReg();
386 SrcReg = MI.getOperand(1).getReg();
387 } else if (MI.isInsertSubreg()) {
388 DstReg = MI.getOperand(0).getReg();
389 SrcReg = MI.getOperand(2).getReg();
390 } else if (MI.isSubregToReg()) {
391 DstReg = MI.getOperand(0).getReg();
392 SrcReg = MI.getOperand(2).getReg();
393 }
394 }
395
396 if (DstReg) {
397 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
398 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
399 return true;
400 }
401 return false;
382 if (MI.isCopy()) {
383 DstReg = MI.getOperand(0).getReg();
384 SrcReg = MI.getOperand(1).getReg();
385 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
386 DstReg = MI.getOperand(0).getReg();
387 SrcReg = MI.getOperand(2).getReg();
388 } else
389 return false;
390
391 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
392 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
393 return true;
402394 }
403395
404396 /// isKilled - Test if the given register value, which is used by the given
0 ../../test-suite
1111 ; RUN: grep rotqby %t2.s | count 5
1212 ; RUN: grep lqd %t2.s | count 13
1313 ; RUN: grep ilhu %t2.s | count 2
14 ; RUN: grep ai %t2.s | count 8
14 ; RUN: grep ai %t2.s | count 9
1515 ; RUN: grep dispatch_tab %t2.s | count 6
1616
1717 ; ModuleID = 'call_indirect.bc'