llvm.org GIT mirror llvm / 0470a16
[PowerPC] Eliminate integer compare instructions - vol. 1 This patch is the first in a series of patches to provide code gen for doing compares in GPRs when the compare result is required in a GPR. It adds the infrastructure to select GPR sequences for i1->i32 and i1->i64 extensions. This first patch handles equality comparison on i32 operands with the result sign or zero extended. Differential Revision: https://reviews.llvm.org/D31847 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302810 91177308-0d34-0410-b5e6-96231b3b80d8 Nemanja Ivanovic 3 years ago
18 changed file(s) with 1943 addition(s) and 12 deletion(s). Raw diff Collapse all Expand all
9494 return;
9595 }
9696
97 if (MI->getOpcode() == PPC::RLDICR) {
97 if (MI->getOpcode() == PPC::RLDICR ||
98 MI->getOpcode() == PPC::RLDICR_32) {
9899 unsigned char SH = MI->getOperand(2).getImm();
99100 unsigned char ME = MI->getOperand(3).getImm();
100101 // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
22452245 }
22462246
22472247 case PPC::EXTSW:
2248 case PPC::EXTSW_32:
22482249 case PPC::EXTSW_32_64: {
22492250 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8)
22502251 return false;
5353 #include "llvm/Support/raw_ostream.h"
5454 #include "llvm/Target/TargetInstrInfo.h"
5555 #include "llvm/Target/TargetRegisterInfo.h"
56 #include "llvm/ADT/Statistic.h"
5657 #include
5758 #include
5859 #include
6768
6869 #define DEBUG_TYPE "ppc-codegen"
6970
71 STATISTIC(NumSextSetcc,
72 "Number of (sext(setcc)) nodes expanded into GPR sequence.");
73 STATISTIC(NumZextSetcc,
74 "Number of (zext(setcc)) nodes expanded into GPR sequence.");
75 STATISTIC(SignExtensionsAdded,
76 "Number of sign extensions for compare inputs added.");
77 STATISTIC(ZeroExtensionsAdded,
78 "Number of zero extensions for compare inputs added.");
7079 // FIXME: Remove this once the bug has been fixed!
7180 cl::opt ANDIGlueBug("expose-ppc-andi-glue-bug",
7281 cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden);
251260 #include "PPCGenDAGISel.inc"
252261
253262 private:
263 // Conversion type for interpreting results of a 32-bit instruction as
264 // a 64-bit value or vice versa.
265 enum ExtOrTruncConversion { Ext, Trunc };
266
267 // Modifiers to guide how an ISD::SETCC node's result is to be computed
268 // in a GPR.
269 // ZExtOrig - use the original condition code, zero-extend value
270 // ZExtInvert - invert the condition code, zero-extend value
271 // SExtOrig - use the original condition code, sign-extend value
272 // SExtInvert - invert the condition code, sign-extend value
273 enum SetccInGPROpts { ZExtOrig, ZExtInvert, SExtOrig, SExtInvert };
274
254275 bool trySETCC(SDNode *N);
276 bool tryEXTEND(SDNode *N);
277 SDValue signExtendInputIfNeeded(SDValue Input);
278 SDValue zeroExtendInputIfNeeded(SDValue Input);
279 SDValue addExtOrTrunc(SDValue NatWidthRes, ExtOrTruncConversion Conv);
280 SDValue get32BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
281 int64_t RHSValue, SDLoc dl);
282 SDValue get32BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
283 int64_t RHSValue, SDLoc dl);
284 SDValue getSETCCInGPR(SDValue Compare, SetccInGPROpts ConvOpts);
255285
256286 void PeepholePPC64();
257287 void PeepholePPC64ZExt();
24702500 return true;
24712501 }
24722502
2503 /// If this node is a sign/zero extension of an integer comparison,
2504 /// it can usually be computed in GPR's rather than using comparison
2505 /// instructions and ISEL. We only do this on 64-bit targets for now
2506 /// as the code is specialized for 64-bit (it uses 64-bit instructions
2507 /// and assumes 64-bit registers).
2508 bool PPCDAGToDAGISel::tryEXTEND(SDNode *N) {
2509 if (TM.getOptLevel() == CodeGenOpt::None || !TM.isPPC64())
2510 return false;
2511 assert((N->getOpcode() == ISD::ZERO_EXTEND ||
2512 N->getOpcode() == ISD::SIGN_EXTEND) &&
2513 "Expecting a zero/sign extend node!");
2514
2515 if (N->getOperand(0).getOpcode() != ISD::SETCC)
2516 return false;
2517
2518 SDValue WideRes =
2519 getSETCCInGPR(N->getOperand(0),
2520 N->getOpcode() == ISD::SIGN_EXTEND ?
2521 SetccInGPROpts::SExtOrig : SetccInGPROpts::ZExtOrig);
2522
2523 if (!WideRes)
2524 return false;
2525
2526 SDLoc dl(N);
2527 bool Inputs32Bit = N->getOperand(0).getOperand(0).getValueType() == MVT::i32;
2528 bool Output32Bit = N->getValueType(0) == MVT::i32;
2529
2530 NumSextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 1 : 0;
2531 NumZextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 0 : 1;
2532
2533 SDValue ConvOp = WideRes;
2534 if (Inputs32Bit != Output32Bit)
2535 ConvOp = addExtOrTrunc(WideRes, Inputs32Bit ? ExtOrTruncConversion::Ext :
2536 ExtOrTruncConversion::Trunc);
2537 ReplaceNode(N, ConvOp.getNode());
2538
2539 return true;
2540 }
2541
2542 /// If the value isn't guaranteed to be sign-extended to 64-bits, extend it.
2543 /// Useful when emitting comparison code for 32-bit values without using
2544 /// the compare instruction (which only considers the lower 32-bits).
2545 SDValue PPCDAGToDAGISel::signExtendInputIfNeeded(SDValue Input) {
2546 assert(Input.getValueType() == MVT::i32 &&
2547 "Can only sign-extend 32-bit values here.");
2548 unsigned Opc = Input.getOpcode();
2549
2550 // The value was sign extended and then truncated to 32-bits. No need to
2551 // sign extend it again.
2552 if (Opc == ISD::TRUNCATE &&
2553 (Input.getOperand(0).getOpcode() == ISD::AssertSext ||
2554 Input.getOperand(0).getOpcode() == ISD::SIGN_EXTEND))
2555 return Input;
2556
2557 LoadSDNode *InputLoad = dyn_cast(Input);
2558 // The input is a sign-extending load. No reason to sign-extend.
2559 if (InputLoad && InputLoad->getExtensionType() == ISD::SEXTLOAD)
2560 return Input;
2561
2562 ConstantSDNode *InputConst = dyn_cast(Input);
2563 // We don't sign-extend constants and already sign-extended values.
2564 if (InputConst || Opc == ISD::AssertSext || Opc == ISD::SIGN_EXTEND_INREG ||
2565 Opc == ISD::SIGN_EXTEND)
2566 return Input;
2567
2568 SDLoc dl(Input);
2569 SignExtensionsAdded++;
2570 return SDValue(CurDAG->getMachineNode(PPC::EXTSW_32, dl, MVT::i32, Input), 0);
2571 }
2572
2573 /// If the value isn't guaranteed to be zero-extended to 64-bits, extend it.
2574 /// Useful when emitting comparison code for 32-bit values without using
2575 /// the compare instruction (which only considers the lower 32-bits).
2576 SDValue PPCDAGToDAGISel::zeroExtendInputIfNeeded(SDValue Input) {
2577 assert(Input.getValueType() == MVT::i32 &&
2578 "Can only zero-extend 32-bit values here.");
2579 LoadSDNode *InputLoad = dyn_cast(Input);
2580 unsigned Opc = Input.getOpcode();
2581
2582 // No need to zero-extend loaded values (unless they're loaded with
2583 // a sign-extending load).
2584 if (InputLoad && InputLoad->getExtensionType() != ISD::SEXTLOAD)
2585 return Input;
2586
2587 ConstantSDNode *InputConst = dyn_cast(Input);
2588 bool InputZExtConst = InputConst && InputConst->getSExtValue() >= 0;
2589 // An ISD::TRUNCATE will be lowered to an EXTRACT_SUBREG so we have
2590 // to conservatively actually clear the high bits. We also don't need to
2591 // zero-extend constants or values that are already zero-extended.
2592 if (InputZExtConst || Opc == ISD::AssertZext || Opc == ISD::ZERO_EXTEND)
2593 return Input;
2594
2595 SDLoc dl(Input);
2596 ZeroExtensionsAdded++;
2597 return SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32, Input,
2598 getI64Imm(0, dl), getI64Imm(32, dl)),
2599 0);
2600 }
2601
2602 // Handle a 32-bit value in a 64-bit register and vice-versa. These are of
2603 // course not actual zero/sign extensions that will generate machine code,
2604 // they're just a way to reinterpret a 32 bit value in a register as a
2605 // 64 bit value and vice-versa.
2606 SDValue PPCDAGToDAGISel::addExtOrTrunc(SDValue NatWidthRes,
2607 ExtOrTruncConversion Conv) {
2608 SDLoc dl(NatWidthRes);
2609
2610 // For reinterpreting 32-bit values as 64 bit values, we generate
2611 // INSERT_SUBREG IMPLICIT_DEF:i64, , TargetConstant:i32<1>
2612 if (Conv == ExtOrTruncConversion::Ext) {
2613 SDValue ImDef(CurDAG->getMachineNode(PPC::IMPLICIT_DEF, dl, MVT::i64), 0);
2614 SDValue SubRegIdx =
2615 CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32);
2616 return SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl, MVT::i64,
2617 ImDef, NatWidthRes, SubRegIdx), 0);
2618 }
2619
2620 assert(Conv == ExtOrTruncConversion::Trunc &&
2621 "Unknown convertion between 32 and 64 bit values.");
2622 // For reinterpreting 64-bit values as 32-bit values, we just need to
2623 // EXTRACT_SUBREG (i.e. extract the low word).
2624 SDValue SubRegIdx =
2625 CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32);
2626 return SDValue(CurDAG->getMachineNode(PPC::EXTRACT_SUBREG, dl, MVT::i32,
2627 NatWidthRes, SubRegIdx), 0);
2628 }
2629
2630 /// Produces a zero-extended result of comparing two 32-bit values according to
2631 /// the passed condition code.
2632 SDValue PPCDAGToDAGISel::get32BitZExtCompare(SDValue LHS, SDValue RHS,
2633 ISD::CondCode CC,
2634 int64_t RHSValue, SDLoc dl) {
2635 bool IsRHSZero = RHSValue == 0;
2636 switch (CC) {
2637 default: return SDValue();
2638 case ISD::SETEQ: {
2639 // (zext (setcc %a, %b, seteq)) -> (lshr (cntlzw (xor %a, %b)), 5)
2640 // (zext (setcc %a, 0, seteq)) -> (lshr (cntlzw %a), 5)
2641 SDValue Xor = IsRHSZero ? LHS :
2642 SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
2643 SDValue Clz =
2644 SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
2645 SDValue ShiftOps[] = { Clz, getI32Imm(27, dl), getI32Imm(5, dl),
2646 getI32Imm(31, dl) };
2647 return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
2648 ShiftOps), 0);
2649 }
2650 }
2651 }
2652
2653 /// Produces a sign-extended result of comparing two 32-bit values according to
2654 /// the passed condition code.
2655 SDValue PPCDAGToDAGISel::get32BitSExtCompare(SDValue LHS, SDValue RHS,
2656 ISD::CondCode CC,
2657 int64_t RHSValue, SDLoc dl) {
2658 bool IsRHSZero = RHSValue == 0;
2659 switch (CC) {
2660 default: return SDValue();
2661 case ISD::SETEQ: {
2662 // (sext (setcc %a, %b, seteq)) ->
2663 // (ashr (shl (ctlz (xor %a, %b)), 58), 63)
2664 // (sext (setcc %a, 0, seteq)) ->
2665 // (ashr (shl (ctlz %a), 58), 63)
2666 SDValue CountInput = IsRHSZero ? LHS :
2667 SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
2668 SDValue Cntlzw =
2669 SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, CountInput), 0);
2670 SDValue SHLOps[] = { Cntlzw, getI32Imm(58, dl), getI32Imm(0, dl) };
2671 SDValue Sldi =
2672 SDValue(CurDAG->getMachineNode(PPC::RLDICR_32, dl, MVT::i32, SHLOps), 0);
2673 return SDValue(CurDAG->getMachineNode(PPC::SRADI_32, dl, MVT::i32, Sldi,
2674 getI32Imm(63, dl)), 0);
2675 }
2676 }
2677 }
2678
2679 /// Returns an equivalent of a SETCC node but with the result the same width as
2680 /// the inputs. This can nalso be used for SELECT_CC if either the true or false
2681 /// values is a power of two while the other is zero.
2682 SDValue PPCDAGToDAGISel::getSETCCInGPR(SDValue Compare,
2683 SetccInGPROpts ConvOpts) {
2684 assert((Compare.getOpcode() == ISD::SETCC ||
2685 Compare.getOpcode() == ISD::SELECT_CC) &&
2686 "An ISD::SETCC node required here.");
2687
2688 SDValue LHS = Compare.getOperand(0);
2689 SDValue RHS = Compare.getOperand(1);
2690
2691 // The condition code is operand 2 for SETCC and operand 4 for SELECT_CC.
2692 int CCOpNum = Compare.getOpcode() == ISD::SELECT_CC ? 4 : 2;
2693 ISD::CondCode CC =
2694 cast(Compare.getOperand(CCOpNum))->get();
2695 EVT InputVT = LHS.getValueType();
2696 if (InputVT != MVT::i32)
2697 return SDValue();
2698
2699 SDLoc dl(Compare);
2700 ConstantSDNode *RHSConst = dyn_cast(RHS);
2701 int64_t RHSValue = RHSConst ? RHSConst->getSExtValue() : INT64_MAX;
2702
2703 if (ConvOpts == SetccInGPROpts::ZExtInvert ||
2704 ConvOpts == SetccInGPROpts::SExtInvert)
2705 CC = ISD::getSetCCInverse(CC, true);
2706
2707 if (ISD::isSignedIntSetCC(CC)) {
2708 LHS = signExtendInputIfNeeded(LHS);
2709 RHS = signExtendInputIfNeeded(RHS);
2710 } else if (ISD::isUnsignedIntSetCC(CC)) {
2711 LHS = zeroExtendInputIfNeeded(LHS);
2712 RHS = zeroExtendInputIfNeeded(RHS);
2713 }
2714
2715 bool IsSext = ConvOpts == SetccInGPROpts::SExtOrig ||
2716 ConvOpts == SetccInGPROpts::SExtInvert;
2717 if (IsSext)
2718 return get32BitSExtCompare(LHS, RHS, CC, RHSValue, dl);
2719 return get32BitZExtCompare(LHS, RHS, CC, RHSValue, dl);
2720 }
2721
24732722 void PPCDAGToDAGISel::transferMemOperands(SDNode *N, SDNode *Result) {
24742723 // Transfer memoperands.
24752724 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
25052754 ReplaceNode(N, getInt64(CurDAG, N));
25062755 return;
25072756 }
2757 break;
2758
2759 case ISD::ZERO_EXTEND:
2760 case ISD::SIGN_EXTEND:
2761 if (tryEXTEND(N))
2762 return;
25082763 break;
25092764
25102765 case ISD::SETCC:
633633 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
634634 "extsw", "$rA, $rS", IIC_IntSimple,
635635 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
636 let isCodeGenOnly = 1 in
637 def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS),
638 "extsw $rA, $rS", IIC_IntSimple,
639 []>, isPPC64;
636640
637641 defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
638642 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI,
639643 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
644 // For fast-isel:
645 let isCodeGenOnly = 1 in
646 def SRADI_32 : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH),
647 "sradi $rA, $rS, $SH", IIC_IntRotateDI, []>, isPPC64;
648
640649 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
641650 "cntlzd", "$rA, $rS", IIC_IntGeneral,
642651 [(set i64:$rA, (ctlz i64:$rS))]>;
720729 // For fast-isel:
721730 let isCodeGenOnly = 1 in
722731 def RLDICL_32_64 : MDForm_1<30, 0,
723 (outs g8rc:$rA),
724 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
725 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI,
726 []>, isPPC64;
732 (outs g8rc:$rA),
733 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
734 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI,
735 []>, isPPC64;
727736 // End fast-isel.
737 let isCodeGenOnly = 1 in
738 def RLDICL_32 : MDForm_1<30, 0,
739 (outs gprc:$rA),
740 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
741 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI,
742 []>, isPPC64;
728743 defm RLDICR : MDForm_1r<30, 1,
729744 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
730745 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
731746 []>, isPPC64;
747 let isCodeGenOnly = 1 in
748 def RLDICR_32 : MDForm_1<30, 1,
749 (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
750 "rldicr $rA, $rS, $SH, $MBE", IIC_IntRotateDI,
751 []>, isPPC64;
732752 defm RLDIC : MDForm_1r<30, 2,
733753 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
734754 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
41654165 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
41664166 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
41674167 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
4168 def : InstAlias<"clrldi $rA, $rS, $n",
4169 (RLDICL_32 gprc:$rA, gprc:$rS, 0, u6imm:$n)>;
41684170 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
41694171
41704172 def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b",
55 ; CHECK: # BB#0:
66 ; CHECK-NEXT: or 3, 3, 4
77 ; CHECK-NEXT: cntlzw 3, 3
8 ; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31
8 ; CHECK-NEXT: srwi 3, 3, 5
99 ; CHECK-NEXT: blr
1010 %a = icmp eq i32 %P, 0
1111 %b = icmp eq i32 %Q, 0
2929 define zeroext i1 @all_bits_set(i32 %P, i32 %Q) {
3030 ; CHECK-LABEL: all_bits_set:
3131 ; CHECK: # BB#0:
32 ; CHECK-NEXT: and 3, 3, 4
33 ; CHECK-NEXT: li 5, 0
34 ; CHECK-NEXT: li 12, 1
35 ; CHECK-NEXT: cmpwi 0, 3, -1
36 ; CHECK-NEXT: isel 3, 12, 5, 2
32 ; CHECK-NEXT: li 5, -1
33 ; CHECK-NEXT: and 3, 3, 4
34 ; CHECK-NEXT: xor 3, 3, 5
35 ; CHECK-NEXT: cntlzw 3, 3
36 ; CHECK-NEXT: srwi 3, 3, 5
3737 ; CHECK-NEXT: blr
3838 %a = icmp eq i32 %P, -1
3939 %b = icmp eq i32 %Q, -1
436436 ; CHECK-NEXT: xor 3, 3, 4
437437 ; CHECK-NEXT: or 3, 3, 5
438438 ; CHECK-NEXT: cntlzw 3, 3
439 ; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31
439 ; CHECK-NEXT: srwi 3, 3, 5
440440 ; CHECK-NEXT: blr
441441 %cmp1 = icmp eq i16 %a, %b
442442 %cmp2 = icmp eq i16 %c, %d
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
7 ; ModuleID = 'ComparisonTestCases/testComparesieqsc.c'
8
9 @glob = common local_unnamed_addr global i8 0, align 1
10
11 ; Function Attrs: norecurse nounwind readnone
12 define signext i32 @test_ieqsc(i8 signext %a, i8 signext %b) {
13 ; CHECK-LABEL: test_ieqsc:
14 ; CHECK: # BB#0: # %entry
15 ; CHECK-NEXT: xor r3, r3, r4
16 ; CHECK-NEXT: cntlzw r3, r3
17 ; CHECK-NEXT: srwi r3, r3, 5
18 ; CHECK-NEXT: blr
19 entry:
20 %cmp = icmp eq i8 %a, %b
21 %conv2 = zext i1 %cmp to i32
22 ret i32 %conv2
23 }
24
25 ; Function Attrs: norecurse nounwind readnone
26 define signext i32 @test_ieqsc_sext(i8 signext %a, i8 signext %b) {
27 ; CHECK-LABEL: test_ieqsc_sext:
28 ; CHECK: # BB#0: # %entry
29 ; CHECK-NEXT: xor r3, r3, r4
30 ; CHECK-NEXT: cntlzw r3, r3
31 ; CHECK-NEXT: rldicr r3, r3, 58, 0
32 ; CHECK-NEXT: sradi r3, r3, 63
33 ; CHECK-NEXT: blr
34 entry:
35 %cmp = icmp eq i8 %a, %b
36 %sub = sext i1 %cmp to i32
37 ret i32 %sub
38 }
39
40 ; Function Attrs: norecurse nounwind readnone
41 define signext i32 @test_ieqsc_z(i8 signext %a) {
42 ; CHECK-LABEL: test_ieqsc_z:
43 ; CHECK: # BB#0: # %entry
44 ; CHECK-NEXT: cntlzw r3, r3
45 ; CHECK-NEXT: srwi r3, r3, 5
46 ; CHECK-NEXT: blr
47 entry:
48 %cmp = icmp eq i8 %a, 0
49 %conv1 = zext i1 %cmp to i32
50 ret i32 %conv1
51 }
52
53 ; Function Attrs: norecurse nounwind readnone
54 define signext i32 @test_ieqsc_sext_z(i8 signext %a) {
55 ; CHECK-LABEL: test_ieqsc_sext_z:
56 ; CHECK: # BB#0: # %entry
57 ; CHECK-NEXT: cntlzw r3, r3
58 ; CHECK-NEXT: rldicr r3, r3, 58, 0
59 ; CHECK-NEXT: sradi r3, r3, 63
60 ; CHECK-NEXT: blr
61 entry:
62 %cmp = icmp eq i8 %a, 0
63 %sub = sext i1 %cmp to i32
64 ret i32 %sub
65 }
66
67 ; Function Attrs: norecurse nounwind
68 define void @test_ieqsc_store(i8 signext %a, i8 signext %b) {
69 ; CHECK-LABEL: test_ieqsc_store:
70 ; CHECK: # BB#0: # %entry
71 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
72 ; CHECK-NEXT: xor r3, r3, r4
73 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
74 ; CHECK-NEXT: cntlzw r3, r3
75 ; CHECK-NEXT: srwi r3, r3, 5
76 ; CHECK-NEXT: stb r3, 0(r12)
77 ; CHECK-NEXT: blr
78 entry:
79 %cmp = icmp eq i8 %a, %b
80 %conv3 = zext i1 %cmp to i8
81 store i8 %conv3, i8* @glob, align 1
82 ret void
83 }
84
85 ; Function Attrs: norecurse nounwind
86 define void @test_ieqsc_sext_store(i8 signext %a, i8 signext %b) {
87 ; CHECK-LABEL: test_ieqsc_sext_store:
88 ; CHECK: # BB#0: # %entry
89 ; CHECK-NEXT: xor r3, r3, r4
90 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
91 ; CHECK-NEXT: cntlzw r3, r3
92 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
93 ; CHECK-NEXT: rldicr r3, r3, 58, 0
94 ; CHECK-NEXT: sradi r3, r3, 63
95 ; CHECK-NEXT: stb r3, 0(r4)
96 ; CHECK-NEXT: blr
97 entry:
98 %cmp = icmp eq i8 %a, %b
99 %conv3 = sext i1 %cmp to i8
100 store i8 %conv3, i8* @glob, align 1
101 ret void
102 }
103
104 ; Function Attrs: norecurse nounwind
105 define void @test_ieqsc_z_store(i8 signext %a) {
106 ; CHECK-LABEL: test_ieqsc_z_store:
107 ; CHECK: # BB#0: # %entry
108 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
109 ; CHECK-NEXT: cntlzw r3, r3
110 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
111 ; CHECK-NEXT: srwi r3, r3, 5
112 ; CHECK-NEXT: stb r3, 0(r4)
113 ; CHECK-NEXT: blr
114 entry:
115 %cmp = icmp eq i8 %a, 0
116 %conv2 = zext i1 %cmp to i8
117 store i8 %conv2, i8* @glob, align 1
118 ret void
119 }
120
121 ; Function Attrs: norecurse nounwind
122 define void @test_ieqsc_sext_z_store(i8 signext %a) {
123 ; CHECK-LABEL: test_ieqsc_sext_z_store:
124 ; CHECK: # BB#0: # %entry
125 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
126 ; CHECK-NEXT: cntlzw r3, r3
127 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
128 ; CHECK-NEXT: rldicr r3, r3, 58, 0
129 ; CHECK-NEXT: sradi r3, r3, 63
130 ; CHECK-NEXT: stb r3, 0(r4)
131 ; CHECK-NEXT: blr
132 entry:
133 %cmp = icmp eq i8 %a, 0
134 %conv2 = sext i1 %cmp to i8
135 store i8 %conv2, i8* @glob, align 1
136 ret void
137 }
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
7 ; ModuleID = 'ComparisonTestCases/testComparesieqsi.c'
8
9 @glob = common local_unnamed_addr global i32 0, align 4
10
11 ; Function Attrs: norecurse nounwind readnone
12 define signext i32 @test_ieqsi(i32 signext %a, i32 signext %b) {
13 ; CHECK-LABEL: test_ieqsi:
14 ; CHECK: # BB#0: # %entry
15 ; CHECK-NEXT: xor r3, r3, r4
16 ; CHECK-NEXT: cntlzw r3, r3
17 ; CHECK-NEXT: srwi r3, r3, 5
18 ; CHECK-NEXT: blr
19 entry:
20 %cmp = icmp eq i32 %a, %b
21 %conv = zext i1 %cmp to i32
22 ret i32 %conv
23 }
24
25 ; Function Attrs: norecurse nounwind readnone
26 define signext i32 @test_ieqsi_sext(i32 signext %a, i32 signext %b) {
27 ; CHECK-LABEL: test_ieqsi_sext:
28 ; CHECK: # BB#0: # %entry
29 ; CHECK-NEXT: xor r3, r3, r4
30 ; CHECK-NEXT: cntlzw r3, r3
31 ; CHECK-NEXT: rldicr r3, r3, 58, 0
32 ; CHECK-NEXT: sradi r3, r3, 63
33 ; CHECK-NEXT: blr
34 entry:
35 %cmp = icmp eq i32 %a, %b
36 %sub = sext i1 %cmp to i32
37 ret i32 %sub
38 }
39
40 ; Function Attrs: norecurse nounwind readnone
41 define signext i32 @test_ieqsi_z(i32 signext %a) {
42 ; CHECK-LABEL: test_ieqsi_z:
43 ; CHECK: # BB#0: # %entry
44 ; CHECK-NEXT: cntlzw r3, r3
45 ; CHECK-NEXT: srwi r3, r3, 5
46 ; CHECK-NEXT: blr
47 entry:
48 %cmp = icmp eq i32 %a, 0
49 %conv = zext i1 %cmp to i32
50 ret i32 %conv
51 }
52
53 ; Function Attrs: norecurse nounwind readnone
54 define signext i32 @test_ieqsi_sext_z(i32 signext %a) {
55 ; CHECK-LABEL: test_ieqsi_sext_z:
56 ; CHECK: # BB#0: # %entry
57 ; CHECK-NEXT: cntlzw r3, r3
58 ; CHECK-NEXT: rldicr r3, r3, 58, 0
59 ; CHECK-NEXT: sradi r3, r3, 63
60 ; CHECK-NEXT: blr
61 entry:
62 %cmp = icmp eq i32 %a, 0
63 %sub = sext i1 %cmp to i32
64 ret i32 %sub
65 }
66
67 ; Function Attrs: norecurse nounwind
68 define void @test_ieqsi_store(i32 signext %a, i32 signext %b) {
69 ; CHECK-LABEL: test_ieqsi_store:
70 ; CHECK: # BB#0: # %entry
71 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
72 ; CHECK-NEXT: xor r3, r3, r4
73 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
74 ; CHECK-NEXT: cntlzw r3, r3
75 ; CHECK-NEXT: srwi r3, r3, 5
76 ; CHECK-NEXT: stw r3, 0(r12)
77 ; CHECK-NEXT: blr
78 entry:
79 %cmp = icmp eq i32 %a, %b
80 %conv = zext i1 %cmp to i32
81 store i32 %conv, i32* @glob, align 4
82 ret void
83 }
84
85 ; Function Attrs: norecurse nounwind
86 define void @test_ieqsi_sext_store(i32 signext %a, i32 signext %b) {
87 ; CHECK-LABEL: test_ieqsi_sext_store:
88 ; CHECK: # BB#0: # %entry
89 ; CHECK-NEXT: xor r3, r3, r4
90 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
91 ; CHECK-NEXT: cntlzw r3, r3
92 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
93 ; CHECK-NEXT: rldicr r3, r3, 58, 0
94 ; CHECK-NEXT: sradi r3, r3, 63
95 ; CHECK-NEXT: stw r3, 0(r4)
96 ; CHECK-NEXT: blr
97 entry:
98 %cmp = icmp eq i32 %a, %b
99 %sub = sext i1 %cmp to i32
100 store i32 %sub, i32* @glob, align 4
101 ret void
102 }
103
104 ; Function Attrs: norecurse nounwind
105 define void @test_ieqsi_z_store(i32 signext %a) {
106 ; CHECK-LABEL: test_ieqsi_z_store:
107 ; CHECK: # BB#0: # %entry
108 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
109 ; CHECK-NEXT: cntlzw r3, r3
110 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
111 ; CHECK-NEXT: srwi r3, r3, 5
112 ; CHECK-NEXT: stw r3, 0(r4)
113 ; CHECK-NEXT: blr
114 entry:
115 %cmp = icmp eq i32 %a, 0
116 %conv = zext i1 %cmp to i32
117 store i32 %conv, i32* @glob, align 4
118 ret void
119 }
120
121 ; Function Attrs: norecurse nounwind
122 define void @test_ieqsi_sext_z_store(i32 signext %a) {
123 ; CHECK-LABEL: test_ieqsi_sext_z_store:
124 ; CHECK: # BB#0: # %entry
125 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
126 ; CHECK-NEXT: cntlzw r3, r3
127 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
128 ; CHECK-NEXT: rldicr r3, r3, 58, 0
129 ; CHECK-NEXT: sradi r3, r3, 63
130 ; CHECK-NEXT: stw r3, 0(r4)
131 ; CHECK-NEXT: blr
132 entry:
133 %cmp = icmp eq i32 %a, 0
134 %sub = sext i1 %cmp to i32
135 store i32 %sub, i32* @glob, align 4
136 ret void
137 }
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
7 ; ModuleID = 'ComparisonTestCases/testComparesieqss.c'
8
9 @glob = common local_unnamed_addr global i16 0, align 2
10
11 ; Function Attrs: norecurse nounwind readnone
12 define signext i32 @test_ieqss(i16 signext %a, i16 signext %b) {
13 ; CHECK-LABEL: test_ieqss:
14 ; CHECK: # BB#0: # %entry
15 ; CHECK-NEXT: xor r3, r3, r4
16 ; CHECK-NEXT: cntlzw r3, r3
17 ; CHECK-NEXT: srwi r3, r3, 5
18 ; CHECK-NEXT: blr
19 entry:
20 %cmp = icmp eq i16 %a, %b
21 %conv2 = zext i1 %cmp to i32
22 ret i32 %conv2
23 }
24
25 ; Function Attrs: norecurse nounwind readnone
26 define signext i32 @test_ieqss_sext(i16 signext %a, i16 signext %b) {
27 ; CHECK-LABEL: test_ieqss_sext:
28 ; CHECK: # BB#0: # %entry
29 ; CHECK-NEXT: xor r3, r3, r4
30 ; CHECK-NEXT: cntlzw r3, r3
31 ; CHECK-NEXT: rldicr r3, r3, 58, 0
32 ; CHECK-NEXT: sradi r3, r3, 63
33 ; CHECK-NEXT: blr
34 entry:
35 %cmp = icmp eq i16 %a, %b
36 %sub = sext i1 %cmp to i32
37 ret i32 %sub
38 }
39
40 ; Function Attrs: norecurse nounwind readnone
41 define signext i32 @test_ieqss_z(i16 signext %a) {
42 ; CHECK-LABEL: test_ieqss_z:
43 ; CHECK: # BB#0: # %entry
44 ; CHECK-NEXT: cntlzw r3, r3
45 ; CHECK-NEXT: srwi r3, r3, 5
46 ; CHECK-NEXT: blr
47 entry:
48 %cmp = icmp eq i16 %a, 0
49 %conv1 = zext i1 %cmp to i32
50 ret i32 %conv1
51 }
52
53 ; Function Attrs: norecurse nounwind readnone
54 define signext i32 @test_ieqss_sext_z(i16 signext %a) {
55 ; CHECK-LABEL: test_ieqss_sext_z:
56 ; CHECK: # BB#0: # %entry
57 ; CHECK-NEXT: cntlzw r3, r3
58 ; CHECK-NEXT: rldicr r3, r3, 58, 0
59 ; CHECK-NEXT: sradi r3, r3, 63
60 ; CHECK-NEXT: blr
61 entry:
62 %cmp = icmp eq i16 %a, 0
63 %sub = sext i1 %cmp to i32
64 ret i32 %sub
65 }
66
67 ; Function Attrs: norecurse nounwind
68 define void @test_ieqss_store(i16 signext %a, i16 signext %b) {
69 ; CHECK-LABEL: test_ieqss_store:
70 ; CHECK: # BB#0: # %entry
71 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
72 ; CHECK-NEXT: xor r3, r3, r4
73 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
74 ; CHECK-NEXT: cntlzw r3, r3
75 ; CHECK-NEXT: srwi r3, r3, 5
76 ; CHECK-NEXT: sth r3, 0(r12)
77 ; CHECK-NEXT: blr
78 entry:
79 %cmp = icmp eq i16 %a, %b
80 %conv3 = zext i1 %cmp to i16
81 store i16 %conv3, i16* @glob, align 2
82 ret void
83 }
84
85 ; Function Attrs: norecurse nounwind
86 define void @test_ieqss_sext_store(i16 signext %a, i16 signext %b) {
87 ; CHECK-LABEL: test_ieqss_sext_store:
88 ; CHECK: # BB#0: # %entry
89 ; CHECK-NEXT: xor r3, r3, r4
90 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
91 ; CHECK-NEXT: cntlzw r3, r3
92 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
93 ; CHECK-NEXT: rldicr r3, r3, 58, 0
94 ; CHECK-NEXT: sradi r3, r3, 63
95 ; CHECK-NEXT: sth r3, 0(r4)
96 ; CHECK-NEXT: blr
97 entry:
98 %cmp = icmp eq i16 %a, %b
99 %conv3 = sext i1 %cmp to i16
100 store i16 %conv3, i16* @glob, align 2
101 ret void
102 }
103
104 ; Function Attrs: norecurse nounwind
105 define void @test_ieqss_z_store(i16 signext %a) {
106 ; CHECK-LABEL: test_ieqss_z_store:
107 ; CHECK: # BB#0: # %entry
108 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
109 ; CHECK-NEXT: cntlzw r3, r3
110 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
111 ; CHECK-NEXT: srwi r3, r3, 5
112 ; CHECK-NEXT: sth r3, 0(r4)
113 ; CHECK-NEXT: blr
114 entry:
115 %cmp = icmp eq i16 %a, 0
116 %conv2 = zext i1 %cmp to i16
117 store i16 %conv2, i16* @glob, align 2
118 ret void
119 }
120
121 ; Function Attrs: norecurse nounwind
122 define void @test_ieqss_sext_z_store(i16 signext %a) {
123 ; CHECK-LABEL: test_ieqss_sext_z_store:
124 ; CHECK: # BB#0: # %entry
125 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
126 ; CHECK-NEXT: cntlzw r3, r3
127 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
128 ; CHECK-NEXT: rldicr r3, r3, 58, 0
129 ; CHECK-NEXT: sradi r3, r3, 63
130 ; CHECK-NEXT: sth r3, 0(r4)
131 ; CHECK-NEXT: blr
132 entry:
133 %cmp = icmp eq i16 %a, 0
134 %conv2 = sext i1 %cmp to i16
135 store i16 %conv2, i16* @glob, align 2
136 ret void
137 }
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
7 ; ModuleID = 'ComparisonTestCases/testComparesiequc.c'
8
9 @glob = common local_unnamed_addr global i8 0, align 1
10
11 ; Function Attrs: norecurse nounwind readnone
12 define signext i32 @test_iequc(i8 zeroext %a, i8 zeroext %b) {
13 ; CHECK-LABEL: test_iequc:
14 ; CHECK: # BB#0: # %entry
15 ; CHECK-NEXT: xor r3, r3, r4
16 ; CHECK-NEXT: cntlzw r3, r3
17 ; CHECK-NEXT: srwi r3, r3, 5
18 ; CHECK-NEXT: blr
19 entry:
20 %cmp = icmp eq i8 %a, %b
21 %conv2 = zext i1 %cmp to i32
22 ret i32 %conv2
23 }
24
25 ; Function Attrs: norecurse nounwind readnone
26 define signext i32 @test_iequc_sext(i8 zeroext %a, i8 zeroext %b) {
27 ; CHECK-LABEL: test_iequc_sext:
28 ; CHECK: # BB#0: # %entry
29 ; CHECK-NEXT: xor r3, r3, r4
30 ; CHECK-NEXT: cntlzw r3, r3
31 ; CHECK-NEXT: rldicr r3, r3, 58, 0
32 ; CHECK-NEXT: sradi r3, r3, 63
33 ; CHECK-NEXT: blr
34 entry:
35 %cmp = icmp eq i8 %a, %b
36 %sub = sext i1 %cmp to i32
37 ret i32 %sub
38 }
39
40 ; Function Attrs: norecurse nounwind readnone
41 define signext i32 @test_iequc_z(i8 zeroext %a) {
42 ; CHECK-LABEL: test_iequc_z:
43 ; CHECK: # BB#0: # %entry
44 ; CHECK-NEXT: cntlzw r3, r3
45 ; CHECK-NEXT: srwi r3, r3, 5
46 ; CHECK-NEXT: blr
47 entry:
48 %cmp = icmp eq i8 %a, 0
49 %conv1 = zext i1 %cmp to i32
50 ret i32 %conv1
51 }
52
53 ; Function Attrs: norecurse nounwind readnone
54 define signext i32 @test_iequc_sext_z(i8 zeroext %a) {
55 ; CHECK-LABEL: test_iequc_sext_z:
56 ; CHECK: # BB#0: # %entry
57 ; CHECK-NEXT: cntlzw r3, r3
58 ; CHECK-NEXT: rldicr r3, r3, 58, 0
59 ; CHECK-NEXT: sradi r3, r3, 63
60 ; CHECK-NEXT: blr
61 entry:
62 %cmp = icmp eq i8 %a, 0
63 %sub = sext i1 %cmp to i32
64 ret i32 %sub
65 }
66
67 ; Function Attrs: norecurse nounwind
68 define void @test_iequc_store(i8 zeroext %a, i8 zeroext %b) {
69 ; CHECK-LABEL: test_iequc_store:
70 ; CHECK: # BB#0: # %entry
71 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
72 ; CHECK-NEXT: xor r3, r3, r4
73 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
74 ; CHECK-NEXT: cntlzw r3, r3
75 ; CHECK-NEXT: srwi r3, r3, 5
76 ; CHECK-NEXT: stb r3, 0(r12)
77 ; CHECK-NEXT: blr
78 entry:
79 %cmp = icmp eq i8 %a, %b
80 %conv3 = zext i1 %cmp to i8
81 store i8 %conv3, i8* @glob, align 1
82 ret void
83 }
84
85 ; Function Attrs: norecurse nounwind
86 define void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
87 ; CHECK-LABEL: test_iequc_sext_store:
88 ; CHECK: # BB#0: # %entry
89 ; CHECK-NEXT: xor r3, r3, r4
90 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
91 ; CHECK-NEXT: cntlzw r3, r3
92 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
93 ; CHECK-NEXT: rldicr r3, r3, 58, 0
94 ; CHECK-NEXT: sradi r3, r3, 63
95 ; CHECK-NEXT: stb r3, 0(r4)
96 ; CHECK-NEXT: blr
97 entry:
98 %cmp = icmp eq i8 %a, %b
99 %conv3 = sext i1 %cmp to i8
100 store i8 %conv3, i8* @glob, align 1
101 ret void
102 }
103
104 ; Function Attrs: norecurse nounwind
105 define void @test_iequc_z_store(i8 zeroext %a) {
106 ; CHECK-LABEL: test_iequc_z_store:
107 ; CHECK: # BB#0: # %entry
108 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
109 ; CHECK-NEXT: cntlzw r3, r3
110 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
111 ; CHECK-NEXT: srwi r3, r3, 5
112 ; CHECK-NEXT: stb r3, 0(r4)
113 ; CHECK-NEXT: blr
114 entry:
115 %cmp = icmp eq i8 %a, 0
116 %conv2 = zext i1 %cmp to i8
117 store i8 %conv2, i8* @glob, align 1
118 ret void
119 }
120
121 ; Function Attrs: norecurse nounwind
122 define void @test_iequc_sext_z_store(i8 zeroext %a) {
123 ; CHECK-LABEL: test_iequc_sext_z_store:
124 ; CHECK: # BB#0: # %entry
125 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
126 ; CHECK-NEXT: cntlzw r3, r3
127 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
128 ; CHECK-NEXT: rldicr r3, r3, 58, 0
129 ; CHECK-NEXT: sradi r3, r3, 63
130 ; CHECK-NEXT: stb r3, 0(r4)
131 ; CHECK-NEXT: blr
132 entry:
133 %cmp = icmp eq i8 %a, 0
134 %conv2 = sext i1 %cmp to i8
135 store i8 %conv2, i8* @glob, align 1
136 ret void
137 }
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
7 ; ModuleID = 'ComparisonTestCases/testComparesiequi.c'
8
9 @glob = common local_unnamed_addr global i32 0, align 4
10
11 ; Function Attrs: norecurse nounwind readnone
12 define signext i32 @test_iequi(i32 zeroext %a, i32 zeroext %b) {
13 ; CHECK-LABEL: test_iequi:
14 ; CHECK: # BB#0: # %entry
15 ; CHECK-NEXT: xor r3, r3, r4
16 ; CHECK-NEXT: cntlzw r3, r3
17 ; CHECK-NEXT: srwi r3, r3, 5
18 ; CHECK-NEXT: blr
19 entry:
20 %cmp = icmp eq i32 %a, %b
21 %conv = zext i1 %cmp to i32
22 ret i32 %conv
23 }
24
25 ; Function Attrs: norecurse nounwind readnone
26 define signext i32 @test_iequi_sext(i32 zeroext %a, i32 zeroext %b) {
27 ; CHECK-LABEL: test_iequi_sext:
28 ; CHECK: # BB#0: # %entry
29 ; CHECK-NEXT: xor r3, r3, r4
30 ; CHECK-NEXT: cntlzw r3, r3
31 ; CHECK-NEXT: rldicr r3, r3, 58, 0
32 ; CHECK-NEXT: sradi r3, r3, 63
33 ; CHECK-NEXT: blr
34 entry:
35 %cmp = icmp eq i32 %a, %b
36 %sub = sext i1 %cmp to i32
37 ret i32 %sub
38 }
39
40 ; Function Attrs: norecurse nounwind readnone
41 define signext i32 @test_iequi_z(i32 zeroext %a) {
42 ; CHECK-LABEL: test_iequi_z:
43 ; CHECK: # BB#0: # %entry
44 ; CHECK-NEXT: cntlzw r3, r3
45 ; CHECK-NEXT: srwi r3, r3, 5
46 ; CHECK-NEXT: blr
47 entry:
48 %cmp = icmp eq i32 %a, 0
49 %conv = zext i1 %cmp to i32
50 ret i32 %conv
51 }
52
53 ; Function Attrs: norecurse nounwind readnone
54 define signext i32 @test_iequi_sext_z(i32 zeroext %a) {
55 ; CHECK-LABEL: test_iequi_sext_z:
56 ; CHECK: # BB#0: # %entry
57 ; CHECK-NEXT: cntlzw r3, r3
58 ; CHECK-NEXT: rldicr r3, r3, 58, 0
59 ; CHECK-NEXT: sradi r3, r3, 63
60 ; CHECK-NEXT: blr
61 entry:
62 %cmp = icmp eq i32 %a, 0
63 %sub = sext i1 %cmp to i32
64 ret i32 %sub
65 }
66
67 ; Function Attrs: norecurse nounwind
68 define void @test_iequi_store(i32 zeroext %a, i32 zeroext %b) {
69 ; CHECK-LABEL: test_iequi_store:
70 ; CHECK: # BB#0: # %entry
71 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
72 ; CHECK-NEXT: xor r3, r3, r4
73 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
74 ; CHECK-NEXT: cntlzw r3, r3
75 ; CHECK-NEXT: srwi r3, r3, 5
76 ; CHECK-NEXT: stw r3, 0(r12)
77 ; CHECK-NEXT: blr
78 entry:
79 %cmp = icmp eq i32 %a, %b
80 %conv = zext i1 %cmp to i32
81 store i32 %conv, i32* @glob, align 4
82 ret void
83 }
84
85 ; Function Attrs: norecurse nounwind
86 define void @test_iequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
87 ; CHECK-LABEL: test_iequi_sext_store:
88 ; CHECK: # BB#0: # %entry
89 ; CHECK-NEXT: xor r3, r3, r4
90 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
91 ; CHECK-NEXT: cntlzw r3, r3
92 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
93 ; CHECK-NEXT: rldicr r3, r3, 58, 0
94 ; CHECK-NEXT: sradi r3, r3, 63
95 ; CHECK-NEXT: stw r3, 0(r4)
96 ; CHECK-NEXT: blr
97 entry:
98 %cmp = icmp eq i32 %a, %b
99 %sub = sext i1 %cmp to i32
100 store i32 %sub, i32* @glob, align 4
101 ret void
102 }
103
104 ; Function Attrs: norecurse nounwind
105 define void @test_iequi_z_store(i32 zeroext %a) {
106 ; CHECK-LABEL: test_iequi_z_store:
107 ; CHECK: # BB#0: # %entry
108 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
109 ; CHECK-NEXT: cntlzw r3, r3
110 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
111 ; CHECK-NEXT: srwi r3, r3, 5
112 ; CHECK-NEXT: stw r3, 0(r4)
113 ; CHECK-NEXT: blr
114 entry:
115 %cmp = icmp eq i32 %a, 0
116 %conv = zext i1 %cmp to i32
117 store i32 %conv, i32* @glob, align 4
118 ret void
119 }
120
121 ; Function Attrs: norecurse nounwind
122 define void @test_iequi_sext_z_store(i32 zeroext %a) {
123 ; CHECK-LABEL: test_iequi_sext_z_store:
124 ; CHECK: # BB#0: # %entry
125 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
126 ; CHECK-NEXT: cntlzw r3, r3
127 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
128 ; CHECK-NEXT: rldicr r3, r3, 58, 0
129 ; CHECK-NEXT: sradi r3, r3, 63
130 ; CHECK-NEXT: stw r3, 0(r4)
131 ; CHECK-NEXT: blr
132 entry:
133 %cmp = icmp eq i32 %a, 0
134 %sub = sext i1 %cmp to i32
135 store i32 %sub, i32* @glob, align 4
136 ret void
137 }
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
7 ; ModuleID = 'ComparisonTestCases/testComparesiequs.c'
8
9 @glob = common local_unnamed_addr global i16 0, align 2
10
11 ; Function Attrs: norecurse nounwind readnone
12 define signext i32 @test_iequs(i16 zeroext %a, i16 zeroext %b) {
13 ; CHECK-LABEL: test_iequs:
14 ; CHECK: # BB#0: # %entry
15 ; CHECK-NEXT: xor r3, r3, r4
16 ; CHECK-NEXT: cntlzw r3, r3
17 ; CHECK-NEXT: srwi r3, r3, 5
18 ; CHECK-NEXT: blr
19 entry:
20 %cmp = icmp eq i16 %a, %b
21 %conv2 = zext i1 %cmp to i32
22 ret i32 %conv2
23 }
24
25 ; Function Attrs: norecurse nounwind readnone
26 define signext i32 @test_iequs_sext(i16 zeroext %a, i16 zeroext %b) {
27 ; CHECK-LABEL: test_iequs_sext:
28 ; CHECK: # BB#0: # %entry
29 ; CHECK-NEXT: xor r3, r3, r4
30 ; CHECK-NEXT: cntlzw r3, r3
31 ; CHECK-NEXT: rldicr r3, r3, 58, 0
32 ; CHECK-NEXT: sradi r3, r3, 63
33 ; CHECK-NEXT: blr
34 entry:
35 %cmp = icmp eq i16 %a, %b
36 %sub = sext i1 %cmp to i32
37 ret i32 %sub
38 }
39
40 ; Function Attrs: norecurse nounwind readnone
41 define signext i32 @test_iequs_z(i16 zeroext %a) {
42 ; CHECK-LABEL: test_iequs_z:
43 ; CHECK: # BB#0: # %entry
44 ; CHECK-NEXT: cntlzw r3, r3
45 ; CHECK-NEXT: srwi r3, r3, 5
46 ; CHECK-NEXT: blr
47 entry:
48 %cmp = icmp eq i16 %a, 0
49 %conv1 = zext i1 %cmp to i32
50 ret i32 %conv1
51 }
52
53 ; Function Attrs: norecurse nounwind readnone
54 define signext i32 @test_iequs_sext_z(i16 zeroext %a) {
55 ; CHECK-LABEL: test_iequs_sext_z:
56 ; CHECK: # BB#0: # %entry
57 ; CHECK-NEXT: cntlzw r3, r3
58 ; CHECK-NEXT: rldicr r3, r3, 58, 0
59 ; CHECK-NEXT: sradi r3, r3, 63
60 ; CHECK-NEXT: blr
61 entry:
62 %cmp = icmp eq i16 %a, 0
63 %sub = sext i1 %cmp to i32
64 ret i32 %sub
65 }
66
67 ; Function Attrs: norecurse nounwind
68 define void @test_iequs_store(i16 zeroext %a, i16 zeroext %b) {
69 ; CHECK-LABEL: test_iequs_store:
70 ; CHECK: # BB#0: # %entry
71 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
72 ; CHECK-NEXT: xor r3, r3, r4
73 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
74 ; CHECK-NEXT: cntlzw r3, r3
75 ; CHECK-NEXT: srwi r3, r3, 5
76 ; CHECK-NEXT: sth r3, 0(r12)
77 ; CHECK-NEXT: blr
78 entry:
79 %cmp = icmp eq i16 %a, %b
80 %conv3 = zext i1 %cmp to i16
81 store i16 %conv3, i16* @glob, align 2
82 ret void
83 }
84
85 ; Function Attrs: norecurse nounwind
86 define void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
87 ; CHECK-LABEL: test_iequs_sext_store:
88 ; CHECK: # BB#0: # %entry
89 ; CHECK-NEXT: xor r3, r3, r4
90 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
91 ; CHECK-NEXT: cntlzw r3, r3
92 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
93 ; CHECK-NEXT: rldicr r3, r3, 58, 0
94 ; CHECK-NEXT: sradi r3, r3, 63
95 ; CHECK-NEXT: sth r3, 0(r4)
96 ; CHECK-NEXT: blr
97 entry:
98 %cmp = icmp eq i16 %a, %b
99 %conv3 = sext i1 %cmp to i16
100 store i16 %conv3, i16* @glob, align 2
101 ret void
102 }
103
104 ; Function Attrs: norecurse nounwind
105 define void @test_iequs_z_store(i16 zeroext %a) {
106 ; CHECK-LABEL: test_iequs_z_store:
107 ; CHECK: # BB#0: # %entry
108 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
109 ; CHECK-NEXT: cntlzw r3, r3
110 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
111 ; CHECK-NEXT: srwi r3, r3, 5
112 ; CHECK-NEXT: sth r3, 0(r4)
113 ; CHECK-NEXT: blr
114 entry:
115 %cmp = icmp eq i16 %a, 0
116 %conv2 = zext i1 %cmp to i16
117 store i16 %conv2, i16* @glob, align 2
118 ret void
119 }
120
121 ; Function Attrs: norecurse nounwind
122 define void @test_iequs_sext_z_store(i16 zeroext %a) {
123 ; CHECK-LABEL: test_iequs_sext_z_store:
124 ; CHECK: # BB#0: # %entry
125 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
126 ; CHECK-NEXT: cntlzw r3, r3
127 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
128 ; CHECK-NEXT: rldicr r3, r3, 58, 0
129 ; CHECK-NEXT: sradi r3, r3, 63
130 ; CHECK-NEXT: sth r3, 0(r4)
131 ; CHECK-NEXT: blr
132 entry:
133 %cmp = icmp eq i16 %a, 0
134 %conv2 = sext i1 %cmp to i16
135 store i16 %conv2, i16* @glob, align 2
136 ret void
137 }
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
7 ; ModuleID = 'ComparisonTestCases/testCompareslleqsc.c'
8
9 @glob = common local_unnamed_addr global i8 0, align 1
10
11 ; Function Attrs: norecurse nounwind readnone
12 define i64 @test_lleqsc(i8 signext %a, i8 signext %b) {
13 ; CHECK-LABEL: test_lleqsc:
14 ; CHECK: # BB#0: # %entry
15 ; CHECK-NEXT: xor r3, r3, r4
16 ; CHECK-NEXT: cntlzw r3, r3
17 ; CHECK-NEXT: srwi r3, r3, 5
18 ; CHECK-NEXT: blr
19 entry:
20 %cmp = icmp eq i8 %a, %b
21 %conv3 = zext i1 %cmp to i64
22 ret i64 %conv3
23 }
24
25 ; Function Attrs: norecurse nounwind readnone
26 define i64 @test_lleqsc_sext(i8 signext %a, i8 signext %b) {
27 ; CHECK-LABEL: test_lleqsc_sext:
28 ; CHECK: # BB#0: # %entry
29 ; CHECK-NEXT: xor r3, r3, r4
30 ; CHECK-NEXT: cntlzw r3, r3
31 ; CHECK-NEXT: rldicr r3, r3, 58, 0
32 ; CHECK-NEXT: sradi r3, r3, 63
33 ; CHECK-NEXT: blr
34 entry:
35 %cmp = icmp eq i8 %a, %b
36 %conv3 = sext i1 %cmp to i64
37 ret i64 %conv3
38 }
39
40 ; Function Attrs: norecurse nounwind readnone
41 define i64 @test_lleqsc_z(i8 signext %a) {
42 ; CHECK-LABEL: test_lleqsc_z:
43 ; CHECK: # BB#0: # %entry
44 ; CHECK-NEXT: cntlzw r3, r3
45 ; CHECK-NEXT: srwi r3, r3, 5
46 ; CHECK-NEXT: blr
47 entry:
48 %cmp = icmp eq i8 %a, 0
49 %conv2 = zext i1 %cmp to i64
50 ret i64 %conv2
51 }
52
53 ; Function Attrs: norecurse nounwind readnone
54 define i64 @test_lleqsc_sext_z(i8 signext %a) {
55 ; CHECK-LABEL: test_lleqsc_sext_z:
56 ; CHECK: # BB#0: # %entry
57 ; CHECK-NEXT: cntlzw r3, r3
58 ; CHECK-NEXT: rldicr r3, r3, 58, 0
59 ; CHECK-NEXT: sradi r3, r3, 63
60 ; CHECK-NEXT: blr
61 entry:
62 %cmp = icmp eq i8 %a, 0
63 %conv2 = sext i1 %cmp to i64
64 ret i64 %conv2
65 }
66
67 ; Function Attrs: norecurse nounwind
68 define void @test_lleqsc_store(i8 signext %a, i8 signext %b) {
69 ; CHECK-LABEL: test_lleqsc_store:
70 ; CHECK: # BB#0: # %entry
71 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
72 ; CHECK-NEXT: xor r3, r3, r4
73 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
74 ; CHECK-NEXT: cntlzw r3, r3
75 ; CHECK-NEXT: srwi r3, r3, 5
76 ; CHECK-NEXT: stb r3, 0(r12)
77 ; CHECK-NEXT: blr
78 entry:
79 %cmp = icmp eq i8 %a, %b
80 %conv3 = zext i1 %cmp to i8
81 store i8 %conv3, i8* @glob, align 1
82 ret void
83 }
84
85 ; Function Attrs: norecurse nounwind
86 define void @test_lleqsc_sext_store(i8 signext %a, i8 signext %b) {
87 ; CHECK-LABEL: test_lleqsc_sext_store:
88 ; CHECK: # BB#0: # %entry
89 ; CHECK-NEXT: xor r3, r3, r4
90 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
91 ; CHECK-NEXT: cntlzw r3, r3
92 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
93 ; CHECK-NEXT: rldicr r3, r3, 58, 0
94 ; CHECK-NEXT: sradi r3, r3, 63
95 ; CHECK-NEXT: stb r3, 0(r4)
96 ; CHECK-NEXT: blr
97 entry:
98 %cmp = icmp eq i8 %a, %b
99 %conv3 = sext i1 %cmp to i8
100 store i8 %conv3, i8* @glob, align 1
101 ret void
102 }
103
104 ; Function Attrs: norecurse nounwind
105 define void @test_lleqsc_z_store(i8 signext %a) {
106 ; CHECK-LABEL: test_lleqsc_z_store:
107 ; CHECK: # BB#0: # %entry
108 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
109 ; CHECK-NEXT: cntlzw r3, r3
110 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
111 ; CHECK-NEXT: srwi r3, r3, 5
112 ; CHECK-NEXT: stb r3, 0(r4)
113 ; CHECK-NEXT: blr
114 entry:
115 %cmp = icmp eq i8 %a, 0
116 %conv2 = zext i1 %cmp to i8
117 store i8 %conv2, i8* @glob, align 1
118 ret void
119 }
120
121 ; Function Attrs: norecurse nounwind
122 define void @test_lleqsc_sext_z_store(i8 signext %a) {
123 ; CHECK-LABEL: test_lleqsc_sext_z_store:
124 ; CHECK: # BB#0: # %entry
125 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
126 ; CHECK-NEXT: cntlzw r3, r3
127 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
128 ; CHECK-NEXT: rldicr r3, r3, 58, 0
129 ; CHECK-NEXT: sradi r3, r3, 63
130 ; CHECK-NEXT: stb r3, 0(r4)
131 ; CHECK-NEXT: blr
132 entry:
133 %cmp = icmp eq i8 %a, 0
134 %conv2 = sext i1 %cmp to i8
135 store i8 %conv2, i8* @glob, align 1
136 ret void
137 }
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
7
8 @glob = common local_unnamed_addr global i32 0, align 4
9
10 ; Function Attrs: norecurse nounwind readnone
11 define i64 @test_lleqsi(i32 signext %a, i32 signext %b) {
12 ; CHECK-LABEL: test_lleqsi:
13 ; CHECK: # BB#0: # %entry
14 ; CHECK-NEXT: xor r3, r3, r4
15 ; CHECK-NEXT: cntlzw r3, r3
16 ; CHECK-NEXT: srwi r3, r3, 5
17 ; CHECK-NEXT: blr
18 entry:
19 %cmp = icmp eq i32 %a, %b
20 %conv1 = zext i1 %cmp to i64
21 ret i64 %conv1
22 }
23
24 ; Function Attrs: norecurse nounwind readnone
25 define i64 @test_lleqsi_sext(i32 signext %a, i32 signext %b) {
26 ; CHECK-LABEL: test_lleqsi_sext:
27 ; CHECK: # BB#0: # %entry
28 ; CHECK-NEXT: xor r3, r3, r4
29 ; CHECK-NEXT: cntlzw r3, r3
30 ; CHECK-NEXT: rldicr r3, r3, 58, 0
31 ; CHECK-NEXT: sradi r3, r3, 63
32 ; CHECK-NEXT: blr
33 entry:
34 %cmp = icmp eq i32 %a, %b
35 %conv1 = sext i1 %cmp to i64
36 ret i64 %conv1
37 }
38
39 ; Function Attrs: norecurse nounwind readnone
40 define i64 @test_lleqsi_z(i32 signext %a) {
41 ; CHECK-LABEL: test_lleqsi_z:
42 ; CHECK: # BB#0: # %entry
43 ; CHECK-NEXT: cntlzw r3, r3
44 ; CHECK-NEXT: srwi r3, r3, 5
45 ; CHECK-NEXT: blr
46 entry:
47 %cmp = icmp eq i32 %a, 0
48 %conv1 = zext i1 %cmp to i64
49 ret i64 %conv1
50 }
51
52 ; Function Attrs: norecurse nounwind readnone
53 define i64 @test_lleqsi_sext_z(i32 signext %a) {
54 ; CHECK-LABEL: test_lleqsi_sext_z:
55 ; CHECK: # BB#0: # %entry
56 ; CHECK-NEXT: cntlzw r3, r3
57 ; CHECK-NEXT: rldicr r3, r3, 58, 0
58 ; CHECK-NEXT: sradi r3, r3, 63
59 ; CHECK-NEXT: blr
60 entry:
61 %cmp = icmp eq i32 %a, 0
62 %conv1 = sext i1 %cmp to i64
63 ret i64 %conv1
64 }
65
66 ; Function Attrs: norecurse nounwind
67 define void @test_lleqsi_store(i32 signext %a, i32 signext %b) {
68 ; CHECK-LABEL: test_lleqsi_store:
69 ; CHECK: # BB#0: # %entry
70 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
71 ; CHECK-NEXT: xor r3, r3, r4
72 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
73 ; CHECK-NEXT: cntlzw r3, r3
74 ; CHECK-NEXT: srwi r3, r3, 5
75 ; CHECK-NEXT: stw r3, 0(r12)
76 ; CHECK-NEXT: blr
77 entry:
78 %cmp = icmp eq i32 %a, %b
79 %conv = zext i1 %cmp to i32
80 store i32 %conv, i32* @glob, align 4
81 ret void
82 }
83
84 ; Function Attrs: norecurse nounwind
85 define void @test_lleqsi_sext_store(i32 signext %a, i32 signext %b) {
86 ; CHECK-LABEL: test_lleqsi_sext_store:
87 ; CHECK: # BB#0: # %entry
88 ; CHECK-NEXT: xor r3, r3, r4
89 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
90 ; CHECK-NEXT: cntlzw r3, r3
91 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
92 ; CHECK-NEXT: rldicr r3, r3, 58, 0
93 ; CHECK-NEXT: sradi r3, r3, 63
94 ; CHECK-NEXT: stw r3, 0(r4)
95 ; CHECK-NEXT: blr
96 entry:
97 %cmp = icmp eq i32 %a, %b
98 %sub = sext i1 %cmp to i32
99 store i32 %sub, i32* @glob, align 4
100 ret void
101 }
102
103 ; Function Attrs: norecurse nounwind
104 define void @test_lleqsi_z_store(i32 signext %a) {
105 ; CHECK-LABEL: test_lleqsi_z_store:
106 ; CHECK: # BB#0: # %entry
107 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
108 ; CHECK-NEXT: cntlzw r3, r3
109 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
110 ; CHECK-NEXT: srwi r3, r3, 5
111 ; CHECK-NEXT: stw r3, 0(r4)
112 ; CHECK-NEXT: blr
113 ; CHECKNEXT: blr
114 entry:
115 %cmp = icmp eq i32 %a, 0
116 %conv = zext i1 %cmp to i32
117 store i32 %conv, i32* @glob, align 4
118 ret void
119 }
120
121 ; Function Attrs: norecurse nounwind
122 define void @test_lleqsi_sext_z_store(i32 signext %a) {
123 ; CHECK-LABEL: test_lleqsi_sext_z_store:
124 ; CHECK: # BB#0: # %entry
125 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
126 ; CHECK-NEXT: cntlzw r3, r3
127 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
128 ; CHECK-NEXT: rldicr r3, r3, 58, 0
129 ; CHECK-NEXT: sradi r3, r3, 63
130 ; CHECK-NEXT: stw r3, 0(r4)
131 ; CHECK-NEXT: blr
132 entry:
133 %cmp = icmp eq i32 %a, 0
134 %sub = sext i1 %cmp to i32
135 store i32 %sub, i32* @glob, align 4
136 ret void
137 }
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
7
8 @glob = common local_unnamed_addr global i16 0, align 2
9
10 ; Function Attrs: norecurse nounwind readnone
11 define i64 @test_lleqss(i16 signext %a, i16 signext %b) {
12 ; CHECK-LABEL: test_lleqss:
13 ; CHECK: # BB#0: # %entry
14 ; CHECK-NEXT: xor r3, r3, r4
15 ; CHECK-NEXT: cntlzw r3, r3
16 ; CHECK-NEXT: srwi r3, r3, 5
17 ; CHECK-NEXT: blr
18 entry:
19 %cmp = icmp eq i16 %a, %b
20 %conv3 = zext i1 %cmp to i64
21 ret i64 %conv3
22 }
23
24 ; Function Attrs: norecurse nounwind readnone
25 define i64 @test_lleqss_sext(i16 signext %a, i16 signext %b) {
26 ; CHECK-LABEL: test_lleqss_sext:
27 ; CHECK: # BB#0: # %entry
28 ; CHECK-NEXT: xor r3, r3, r4
29 ; CHECK-NEXT: cntlzw r3, r3
30 ; CHECK-NEXT: rldicr r3, r3, 58, 0
31 ; CHECK-NEXT: sradi r3, r3, 63
32 ; CHECK-NEXT: blr
33 entry:
34 %cmp = icmp eq i16 %a, %b
35 %conv3 = sext i1 %cmp to i64
36 ret i64 %conv3
37 }
38
39 ; Function Attrs: norecurse nounwind readnone
40 define i64 @test_lleqss_z(i16 signext %a) {
41 ; CHECK-LABEL: test_lleqss_z:
42 ; CHECK: # BB#0: # %entry
43 ; CHECK-NEXT: cntlzw r3, r3
44 ; CHECK-NEXT: srwi r3, r3, 5
45 ; CHECK-NEXT: blr
46 entry:
47 %cmp = icmp eq i16 %a, 0
48 %conv2 = zext i1 %cmp to i64
49 ret i64 %conv2
50 }
51
52 ; Function Attrs: norecurse nounwind readnone
53 define i64 @test_lleqss_sext_z(i16 signext %a) {
54 ; CHECK-LABEL: test_lleqss_sext_z:
55 ; CHECK: # BB#0: # %entry
56 ; CHECK-NEXT: cntlzw r3, r3
57 ; CHECK-NEXT: rldicr r3, r3, 58, 0
58 ; CHECK-NEXT: sradi r3, r3, 63
59 ; CHECK-NEXT: blr
60 entry:
61 %cmp = icmp eq i16 %a, 0
62 %conv2 = sext i1 %cmp to i64
63 ret i64 %conv2
64 }
65
66 ; Function Attrs: norecurse nounwind
67 define void @test_lleqss_store(i16 signext %a, i16 signext %b) {
68 ; CHECK-LABEL: test_lleqss_store:
69 ; CHECK: # BB#0: # %entry
70 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
71 ; CHECK-NEXT: xor r3, r3, r4
72 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
73 ; CHECK-NEXT: cntlzw r3, r3
74 ; CHECK-NEXT: srwi r3, r3, 5
75 ; CHECK-NEXT: sth r3, 0(r12)
76 ; CHECK-NEXT: blr
77 entry:
78 %cmp = icmp eq i16 %a, %b
79 %conv3 = zext i1 %cmp to i16
80 store i16 %conv3, i16* @glob, align 2
81 ret void
82 }
83
84 ; Function Attrs: norecurse nounwind
85 define void @test_lleqss_sext_store(i16 signext %a, i16 signext %b) {
86 ; CHECK-LABEL: test_lleqss_sext_store:
87 ; CHECK: # BB#0: # %entry
88 ; CHECK-NEXT: xor r3, r3, r4
89 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
90 ; CHECK-NEXT: cntlzw r3, r3
91 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
92 ; CHECK-NEXT: rldicr r3, r3, 58, 0
93 ; CHECK-NEXT: sradi r3, r3, 63
94 ; CHECK-NEXT: sth r3, 0(r4)
95 ; CHECK-NEXT: blr
96 entry:
97 %cmp = icmp eq i16 %a, %b
98 %conv3 = sext i1 %cmp to i16
99 store i16 %conv3, i16* @glob, align 2
100 ret void
101 }
102
103 ; Function Attrs: norecurse nounwind
104 define void @test_lleqss_z_store(i16 signext %a) {
105 ; CHECK-LABEL: test_lleqss_z_store:
106 ; CHECK: # BB#0: # %entry
107 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
108 ; CHECK-NEXT: cntlzw r3, r3
109 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
110 ; CHECK-NEXT: srwi r3, r3, 5
111 ; CHECK-NEXT: sth r3, 0(r4)
112 ; CHECK-NEXT: blr
113 entry:
114 %cmp = icmp eq i16 %a, 0
115 %conv2 = zext i1 %cmp to i16
116 store i16 %conv2, i16* @glob, align 2
117 ret void
118 }
119
120 ; Function Attrs: norecurse nounwind
121 define void @test_lleqss_sext_z_store(i16 signext %a) {
122 ; CHECK-LABEL: test_lleqss_sext_z_store:
123 ; CHECK: # BB#0: # %entry
124 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
125 ; CHECK-NEXT: cntlzw r3, r3
126 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
127 ; CHECK-NEXT: rldicr r3, r3, 58, 0
128 ; CHECK-NEXT: sradi r3, r3, 63
129 ; CHECK-NEXT: sth r3, 0(r4)
130 ; CHECK-NEXT: blr
131 entry:
132 %cmp = icmp eq i16 %a, 0
133 %conv2 = sext i1 %cmp to i16
134 store i16 %conv2, i16* @glob, align 2
135 ret void
136 }
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
7
8 @glob = common local_unnamed_addr global i8 0, align 1
9
10 ; Function Attrs: norecurse nounwind readnone
11 define i64 @test_llequc(i8 zeroext %a, i8 zeroext %b) {
12 ; CHECK-LABEL: test_llequc:
13 ; CHECK: # BB#0: # %entry
14 ; CHECK-NEXT: xor r3, r3, r4
15 ; CHECK-NEXT: cntlzw r3, r3
16 ; CHECK-NEXT: srwi r3, r3, 5
17 ; CHECK-NEXT: blr
18 entry:
19 %cmp = icmp eq i8 %a, %b
20 %conv3 = zext i1 %cmp to i64
21 ret i64 %conv3
22 }
23
24 ; Function Attrs: norecurse nounwind readnone
25 define i64 @test_llequc_sext(i8 zeroext %a, i8 zeroext %b) {
26 ; CHECK-LABEL: test_llequc_sext:
27 ; CHECK: # BB#0: # %entry
28 ; CHECK-NEXT: xor r3, r3, r4
29 ; CHECK-NEXT: cntlzw r3, r3
30 ; CHECK-NEXT: rldicr r3, r3, 58, 0
31 ; CHECK-NEXT: sradi r3, r3, 63
32 ; CHECK-NEXT: blr
33 entry:
34 %cmp = icmp eq i8 %a, %b
35 %conv3 = sext i1 %cmp to i64
36 ret i64 %conv3
37 }
38
39 ; Function Attrs: norecurse nounwind readnone
40 define i64 @test_llequc_z(i8 zeroext %a) {
41 ; CHECK-LABEL: test_llequc_z:
42 ; CHECK: # BB#0: # %entry
43 ; CHECK-NEXT: cntlzw r3, r3
44 ; CHECK-NEXT: srwi r3, r3, 5
45 ; CHECK-NEXT: blr
46 entry:
47 %cmp = icmp eq i8 %a, 0
48 %conv2 = zext i1 %cmp to i64
49 ret i64 %conv2
50 }
51
52 ; Function Attrs: norecurse nounwind readnone
53 define i64 @test_llequc_sext_z(i8 zeroext %a) {
54 ; CHECK-LABEL: test_llequc_sext_z:
55 ; CHECK: # BB#0: # %entry
56 ; CHECK-NEXT: cntlzw r3, r3
57 ; CHECK-NEXT: rldicr r3, r3, 58, 0
58 ; CHECK-NEXT: sradi r3, r3, 63
59 ; CHECK-NEXT: blr
60 entry:
61 %cmp = icmp eq i8 %a, 0
62 %conv2 = sext i1 %cmp to i64
63 ret i64 %conv2
64 }
65
66 ; Function Attrs: norecurse nounwind
67 define void @test_llequc_store(i8 zeroext %a, i8 zeroext %b) {
68 ; CHECK-LABEL: test_llequc_store:
69 ; CHECK: # BB#0: # %entry
70 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
71 ; CHECK-NEXT: xor r3, r3, r4
72 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
73 ; CHECK-NEXT: cntlzw r3, r3
74 ; CHECK-NEXT: srwi r3, r3, 5
75 ; CHECK-NEXT: stb r3, 0(r12)
76 ; CHECK-NEXT: blr
77 entry:
78 %cmp = icmp eq i8 %a, %b
79 %conv3 = zext i1 %cmp to i8
80 store i8 %conv3, i8* @glob, align 1
81 ret void
82 }
83
84 ; Function Attrs: norecurse nounwind
85 define void @test_llequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
86 ; CHECK-LABEL: test_llequc_sext_store:
87 ; CHECK: # BB#0: # %entry
88 ; CHECK-NEXT: xor r3, r3, r4
89 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
90 ; CHECK-NEXT: cntlzw r3, r3
91 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
92 ; CHECK-NEXT: rldicr r3, r3, 58, 0
93 ; CHECK-NEXT: sradi r3, r3, 63
94 ; CHECK-NEXT: stb r3, 0(r4)
95 ; CHECK-NEXT: blr
96 entry:
97 %cmp = icmp eq i8 %a, %b
98 %conv3 = sext i1 %cmp to i8
99 store i8 %conv3, i8* @glob, align 1
100 ret void
101 }
102
103 ; Function Attrs: norecurse nounwind
104 define void @test_llequc_z_store(i8 zeroext %a) {
105 ; CHECK-LABEL: test_llequc_z_store:
106 ; CHECK: # BB#0: # %entry
107 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
108 ; CHECK-NEXT: cntlzw r3, r3
109 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
110 ; CHECK-NEXT: srwi r3, r3, 5
111 ; CHECK-NEXT: stb r3, 0(r4)
112 ; CHECK-NEXT: blr
113 entry:
114 %cmp = icmp eq i8 %a, 0
115 %conv2 = zext i1 %cmp to i8
116 store i8 %conv2, i8* @glob, align 1
117 ret void
118 }
119
120 ; Function Attrs: norecurse nounwind
121 define void @test_llequc_sext_z_store(i8 zeroext %a) {
122 ; CHECK-LABEL: test_llequc_sext_z_store:
123 ; CHECK: # BB#0: # %entry
124 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
125 ; CHECK-NEXT: cntlzw r3, r3
126 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
127 ; CHECK-NEXT: rldicr r3, r3, 58, 0
128 ; CHECK-NEXT: sradi r3, r3, 63
129 ; CHECK-NEXT: stb r3, 0(r4)
130 ; CHECK-NEXT: blr
131 entry:
132 %cmp = icmp eq i8 %a, 0
133 %conv2 = sext i1 %cmp to i8
134 store i8 %conv2, i8* @glob, align 1
135 ret void
136 }
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
7
8 @glob = common local_unnamed_addr global i32 0, align 4
9
10 ; Function Attrs: norecurse nounwind readnone
11 define i64 @test_llequi(i32 zeroext %a, i32 zeroext %b) {
12 ; CHECK-LABEL: test_llequi:
13 ; CHECK: # BB#0: # %entry
14 ; CHECK-NEXT: xor r3, r3, r4
15 ; CHECK-NEXT: cntlzw r3, r3
16 ; CHECK-NEXT: srwi r3, r3, 5
17 ; CHECK-NEXT: blr
18 entry:
19 %cmp = icmp eq i32 %a, %b
20 %conv1 = zext i1 %cmp to i64
21 ret i64 %conv1
22 }
23
24 ; Function Attrs: norecurse nounwind readnone
25 define i64 @test_llequi_sext(i32 zeroext %a, i32 zeroext %b) {
26 ; CHECK-LABEL: test_llequi_sext:
27 ; CHECK: # BB#0: # %entry
28 ; CHECK-NEXT: xor r3, r3, r4
29 ; CHECK-NEXT: cntlzw r3, r3
30 ; CHECK-NEXT: rldicr r3, r3, 58, 0
31 ; CHECK-NEXT: sradi r3, r3, 63
32 ; CHECK-NEXT: blr
33 entry:
34 %cmp = icmp eq i32 %a, %b
35 %conv1 = sext i1 %cmp to i64
36 ret i64 %conv1
37 }
38
39 ; Function Attrs: norecurse nounwind readnone
40 define i64 @test_llequi_z(i32 zeroext %a) {
41 ; CHECK-LABEL: test_llequi_z:
42 ; CHECK: # BB#0: # %entry
43 ; CHECK-NEXT: cntlzw r3, r3
44 ; CHECK-NEXT: srwi r3, r3, 5
45 ; CHECK-NEXT: blr
46 entry:
47 %cmp = icmp eq i32 %a, 0
48 %conv1 = zext i1 %cmp to i64
49 ret i64 %conv1
50 }
51
52 ; Function Attrs: norecurse nounwind readnone
53 define i64 @test_llequi_sext_z(i32 zeroext %a) {
54 ; CHECK-LABEL: test_llequi_sext_z:
55 ; CHECK: # BB#0: # %entry
56 ; CHECK-NEXT: cntlzw r3, r3
57 ; CHECK-NEXT: rldicr r3, r3, 58, 0
58 ; CHECK-NEXT: sradi r3, r3, 63
59 ; CHECK-NEXT: blr
60 entry:
61 %cmp = icmp eq i32 %a, 0
62 %conv1 = sext i1 %cmp to i64
63 ret i64 %conv1
64 }
65
66 ; Function Attrs: norecurse nounwind
67 define void @test_llequi_store(i32 zeroext %a, i32 zeroext %b) {
68 ; CHECK-LABEL: test_llequi_store:
69 ; CHECK: # BB#0: # %entry
70 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
71 ; CHECK-NEXT: xor r3, r3, r4
72 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
73 ; CHECK-NEXT: cntlzw r3, r3
74 ; CHECK-NEXT: srwi r3, r3, 5
75 ; CHECK-NEXT: stw r3, 0(r12)
76 ; CHECK-NEXT: blr
77 entry:
78 %cmp = icmp eq i32 %a, %b
79 %conv = zext i1 %cmp to i32
80 store i32 %conv, i32* @glob, align 4
81 ret void
82 }
83
84 ; Function Attrs: norecurse nounwind
85 define void @test_llequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
86 ; CHECK-LABEL: test_llequi_sext_store:
87 ; CHECK: # BB#0: # %entry
88 ; CHECK-NEXT: xor r3, r3, r4
89 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
90 ; CHECK-NEXT: cntlzw r3, r3
91 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
92 ; CHECK-NEXT: rldicr r3, r3, 58, 0
93 ; CHECK-NEXT: sradi r3, r3, 63
94 ; CHECK-NEXT: stw r3, 0(r4)
95 ; CHECK-NEXT: blr
96 entry:
97 %cmp = icmp eq i32 %a, %b
98 %sub = sext i1 %cmp to i32
99 store i32 %sub, i32* @glob, align 4
100 ret void
101 }
102
103 ; Function Attrs: norecurse nounwind
104 define void @test_llequi_z_store(i32 zeroext %a) {
105 ; CHECK-LABEL: test_llequi_z_store:
106 ; CHECK: # BB#0: # %entry
107 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
108 ; CHECK-NEXT: cntlzw r3, r3
109 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
110 ; CHECK-NEXT: srwi r3, r3, 5
111 ; CHECK-NEXT: stw r3, 0(r4)
112 ; CHECK-NEXT: blr
113 entry:
114 %cmp = icmp eq i32 %a, 0
115 %conv = zext i1 %cmp to i32
116 store i32 %conv, i32* @glob, align 4
117 ret void
118 }
119
120 ; Function Attrs: norecurse nounwind
121 define void @test_llequi_sext_z_store(i32 zeroext %a) {
122 ; CHECK-LABEL: test_llequi_sext_z_store:
123 ; CHECK: # BB#0: # %entry
124 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
125 ; CHECK-NEXT: cntlzw r3, r3
126 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
127 ; CHECK-NEXT: rldicr r3, r3, 58, 0
128 ; CHECK-NEXT: sradi r3, r3, 63
129 ; CHECK-NEXT: stw r3, 0(r4)
130 ; CHECK-NEXT: blr
131 entry:
132 %cmp = icmp eq i32 %a, 0
133 %sub = sext i1 %cmp to i32
134 store i32 %sub, i32* @glob, align 4
135 ret void
136 }
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
7
8 @glob = common local_unnamed_addr global i16 0, align 2
9
10 ; Function Attrs: norecurse nounwind readnone
11 define i64 @test_llequs(i16 zeroext %a, i16 zeroext %b) {
12 ; CHECK-LABEL: test_llequs:
13 ; CHECK: # BB#0: # %entry
14 ; CHECK-NEXT: xor r3, r3, r4
15 ; CHECK-NEXT: cntlzw r3, r3
16 ; CHECK-NEXT: srwi r3, r3, 5
17 ; CHECK-NEXT: blr
18 entry:
19 %cmp = icmp eq i16 %a, %b
20 %conv3 = zext i1 %cmp to i64
21 ret i64 %conv3
22 }
23
24 ; Function Attrs: norecurse nounwind readnone
25 define i64 @test_llequs_sext(i16 zeroext %a, i16 zeroext %b) {
26 ; CHECK-LABEL: test_llequs_sext:
27 ; CHECK: # BB#0: # %entry
28 ; CHECK-NEXT: xor r3, r3, r4
29 ; CHECK-NEXT: cntlzw r3, r3
30 ; CHECK-NEXT: rldicr r3, r3, 58, 0
31 ; CHECK-NEXT: sradi r3, r3, 63
32 ; CHECK-NEXT: blr
33 entry:
34 %cmp = icmp eq i16 %a, %b
35 %conv3 = sext i1 %cmp to i64
36 ret i64 %conv3
37 }
38
39 ; Function Attrs: norecurse nounwind readnone
40 define i64 @test_llequs_z(i16 zeroext %a) {
41 ; CHECK-LABEL: test_llequs_z:
42 ; CHECK: # BB#0: # %entry
43 ; CHECK-NEXT: cntlzw r3, r3
44 ; CHECK-NEXT: srwi r3, r3, 5
45 ; CHECK-NEXT: blr
46 entry:
47 %cmp = icmp eq i16 %a, 0
48 %conv2 = zext i1 %cmp to i64
49 ret i64 %conv2
50 }
51
52 ; Function Attrs: norecurse nounwind readnone
53 define i64 @test_llequs_sext_z(i16 zeroext %a) {
54 ; CHECK-LABEL: test_llequs_sext_z:
55 ; CHECK: # BB#0: # %entry
56 ; CHECK-NEXT: cntlzw r3, r3
57 ; CHECK-NEXT: rldicr r3, r3, 58, 0
58 ; CHECK-NEXT: sradi r3, r3, 63
59 ; CHECK-NEXT: blr
60 entry:
61 %cmp = icmp eq i16 %a, 0
62 %conv2 = sext i1 %cmp to i64
63 ret i64 %conv2
64 }
65
66 ; Function Attrs: norecurse nounwind
67 define void @test_llequs_store(i16 zeroext %a, i16 zeroext %b) {
68 ; CHECK-LABEL: test_llequs_store:
69 ; CHECK: # BB#0: # %entry
70 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
71 ; CHECK-NEXT: xor r3, r3, r4
72 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
73 ; CHECK-NEXT: cntlzw r3, r3
74 ; CHECK-NEXT: srwi r3, r3, 5
75 ; CHECK-NEXT: sth r3, 0(r12)
76 ; CHECK-NEXT: blr
77 entry:
78 %cmp = icmp eq i16 %a, %b
79 %conv3 = zext i1 %cmp to i16
80 store i16 %conv3, i16* @glob, align 2
81 ret void
82 }
83
84 ; Function Attrs: norecurse nounwind
85 define void @test_llequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
86 ; CHECK-LABEL: test_llequs_sext_store:
87 ; CHECK: # BB#0: # %entry
88 ; CHECK-NEXT: xor r3, r3, r4
89 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
90 ; CHECK-NEXT: cntlzw r3, r3
91 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
92 ; CHECK-NEXT: rldicr r3, r3, 58, 0
93 ; CHECK-NEXT: sradi r3, r3, 63
94 ; CHECK-NEXT: sth r3, 0(r4)
95 ; CHECK-NEXT: blr
96 entry:
97 %cmp = icmp eq i16 %a, %b
98 %conv3 = sext i1 %cmp to i16
99 store i16 %conv3, i16* @glob, align 2
100 ret void
101 }
102
103 ; Function Attrs: norecurse nounwind
104 define void @test_llequs_z_store(i16 zeroext %a) {
105 ; CHECK-LABEL: test_llequs_z_store:
106 ; CHECK: # BB#0: # %entry
107 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
108 ; CHECK-NEXT: cntlzw r3, r3
109 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
110 ; CHECK-NEXT: srwi r3, r3, 5
111 ; CHECK-NEXT: sth r3, 0(r4)
112 ; CHECK-NEXT: blr
113 entry:
114 %cmp = icmp eq i16 %a, 0
115 %conv2 = zext i1 %cmp to i16
116 store i16 %conv2, i16* @glob, align 2
117 ret void
118 }
119
120 ; Function Attrs: norecurse nounwind
121 define void @test_llequs_sext_z_store(i16 zeroext %a) {
122 ; CHECK-LABEL: test_llequs_sext_z_store:
123 ; CHECK: # BB#0: # %entry
124 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
125 ; CHECK-NEXT: cntlzw r3, r3
126 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
127 ; CHECK-NEXT: rldicr r3, r3, 58, 0
128 ; CHECK-NEXT: sradi r3, r3, 63
129 ; CHECK-NEXT: sth r3, 0(r4)
130 ; CHECK-NEXT: blr
131 entry:
132 %cmp = icmp eq i16 %a, 0
133 %conv2 = sext i1 %cmp to i16
134 store i16 %conv2, i16* @glob, align 2
135 ret void
136 }